1 files changed, 418 insertions, 0 deletions
diff --git a/package/boot/uboot-layerscape/patches/0013-armv8-fsl-layerscape-Add-support-of-QorIQ-LS1012A-So.patch b/package/boot/uboot-layerscape/patches/0013-armv8-fsl-layerscape-Add-support-of-QorIQ-LS1012A-So.patch
new file mode 100644
index 0000000000..ea7ab962b8
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0013-armv8-fsl-layerscape-Add-support-of-QorIQ-LS1012A-So.patch
@@ -0,0 +1,418 @@
+From 53ffd67d944fa23037e7f97e583fae300d4367f7 Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Sat, 23 Apr 2016 15:23:52 +0530
+Subject: [PATCH 13/93] armv8: fsl-layerscape: Add support of QorIQ LS1012A
+ SoC
+
+[context adjustment]
+
+The QorIQ LS1012A processor, optimized for battery-backed or
+USB-powered, integrates a single ARM Cortex-A53 core with a hardware
+packet forwarding engine and high-speed interfaces to deliver
+line-rate networking performance.
+
+This patch add support of LS1012A SoC along with
+ - Update platform & DDR clock read logic as per SVR
+ - Define MMDC controller register set.
+ - Update LUT base address for PCIe
+ - Avoid L3 platform cache compilation
+ - Update USB address, errata
+ - SerDes table
+
+Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
+Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
+---
+ arch/arm/cpu/armv8/fsl-layerscape/Makefile         |    4 ++
+ .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c |   24 +++++--
+ arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S       |    2 +
+ arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c |   74 ++++++++++++++++++++
+ arch/arm/cpu/armv8/fsl-layerscape/soc.c            |    6 +-
+ arch/arm/include/asm/arch-fsl-layerscape/config.h  |   32 +++++++++
+ arch/arm/include/asm/arch-fsl-layerscape/cpu.h     |    1 +
+ .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |    1 +
+ .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |    4 ++
+ arch/arm/include/asm/arch-fsl-layerscape/soc.h     |    1 +
+ include/fsl_mmdc.h                                 |   53 ++++++++++++++
+ include/linux/usb/xhci-fsl.h                       |    4 ++
+ 12 files changed, 199 insertions(+), 7 deletions(-)
+ create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
+ create mode 100644 include/fsl_mmdc.h
+
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+index 27bfeb1..03f73d1 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
++++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+@@ -33,3 +33,7 @@ endif
+ ifneq ($(CONFIG_LS1043A),)
+ obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
+ endif
++
++ifneq ($(CONFIG_LS1012A),)
++obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o
++endif
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+index 078b087..63e5bed 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
++++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+@@ -33,6 +33,7 @@ void get_sys_info(struct sys_info *sys_info)
+ #endif
+ 	struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
+ 	unsigned int cpu;
++	unsigned int svr, ver;
+ 	const u8 core_cplx_pll[8] = {
+ 		[0] = 0,	/* CC1 PPL / 1 */
+ 		[1] = 0,	/* CC1 PPL / 2 */
+@@ -59,12 +60,20 @@ void get_sys_info(struct sys_info *sys_info)
+ 	sys_info->freq_ddrbus = sysclk;
+ #endif
+ 
+-	sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
+-			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
+-			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
+-	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
+-			FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
+-			FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
++	svr = gur_in32(&gur->svr);
++	ver = SVR_SOC_VER(svr);
++	if (ver == SVR_LS1012) {
++		sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
++				FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
++				FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
++	} else {
++		sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
++				FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
++				FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
++		sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
++				FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
++				FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
++	}
+ 
+ 	for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
+ 		ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
+@@ -83,6 +92,9 @@ void get_sys_info(struct sys_info *sys_info)
+ 			freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
+ 	}
+ 
++	if (ver == SVR_LS1012)
++		sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
++
+ #define HWA_CGA_M1_CLK_SEL	0xe0000000
+ #define HWA_CGA_M1_CLK_SHIFT	29
+ #ifdef CONFIG_SYS_DPAA_FMAN
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+index 5f5bfb9..b40834a 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
++++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+@@ -184,6 +184,7 @@ ENTRY(lowlevel_init)
+ 	ret
+ ENDPROC(lowlevel_init)
+ 
++#ifdef CONFIG_FSL_LSCH3
+ hnf_pstate_poll:
+ 	/* x0 has the desired status, return 0 for success, 1 for timeout
+ 	 * clobber x1, x2, x3, x4, x6, x7
+@@ -261,6 +262,7 @@ ENTRY(__asm_flush_l3_cache)
+ 	mov	lr, x29
+ 	ret
+ ENDPROC(__asm_flush_l3_cache)
++#endif
+ 
+ #ifdef CONFIG_MP
+ 	/* Keep literals not used by the secondary boot code outside it */
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
+new file mode 100644
+index 0000000..ff0903c
+--- /dev/null
++++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
+@@ -0,0 +1,74 @@
++/*
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#include <common.h>
++#include <asm/arch/fsl_serdes.h>
++#include <asm/arch/immap_lsch2.h>
++
++struct serdes_config {
++	u32 protocol;
++	u8 lanes[SRDS_MAX_LANES];
++};
++
++static struct serdes_config serdes1_cfg_tbl[] = {
++	{0x2208, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, SATA1} },
++	{0x0008, {NONE, NONE, NONE, SATA1} },
++	{0x3508, {SGMII_FM1_DTSEC1, PCIE1, NONE, SATA1} },
++	{0x3305, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} },
++	{0x2205, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, PCIE1} },
++	{0x2305, {SGMII_2500_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} },
++	{0x9508, {TX_CLK, PCIE1, NONE, SATA1} },
++	{0x3905, {SGMII_FM1_DTSEC1, TX_CLK, NONE, PCIE1} },
++	{0x9305, {TX_CLK, SGMII_FM1_DTSEC2, NONE, PCIE1} },
++	{}
++};
++
++static struct serdes_config *serdes_cfg_tbl[] = {
++	serdes1_cfg_tbl,
++};
++
++enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
++{
++	struct serdes_config *ptr;
++
++	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
++		return 0;
++
++	ptr = serdes_cfg_tbl[serdes];
++	while (ptr->protocol) {
++		if (ptr->protocol == cfg)
++			return ptr->lanes[lane];
++		ptr++;
++	}
++
++	return 0;
++}
++
++int is_serdes_prtcl_valid(int serdes, u32 prtcl)
++{
++	int i;
++	struct serdes_config *ptr;
++
++	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
++		return 0;
++
++	ptr = serdes_cfg_tbl[serdes];
++	while (ptr->protocol) {
++		if (ptr->protocol == prtcl)
++			break;
++		ptr++;
++	}
++
++	if (!ptr->protocol)
++		return 0;
++
++	for (i = 0; i < SRDS_MAX_LANES; i++) {
++		if (ptr->lanes[i] != NONE)
++			return 1;
++	}
++
++	return 0;
++}
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+index 23f0c88..ec561a7 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
++++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+@@ -12,8 +12,10 @@
+ #include <asm/io.h>
+ #include <asm/global_data.h>
+ #include <asm/arch-fsl-layerscape/config.h>
++#ifdef CONFIG_SYS_FSL_DDR
+ #include <fsl_ddr_sdram.h>
+ #include <fsl_ddr.h>
++#endif
+ #ifdef CONFIG_CHAIN_OF_TRUST
+ #include <fsl_validate.h>
+ #endif
+@@ -46,14 +48,16 @@ static void erratum_a009008(void)
+ static void erratum_a009798(void)
+ {
+ #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+-#if defined(CONFIG_LS1043A)
++#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
+ 	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ 	u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
+ 	scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4 , val & USB_SQRXTUNE);
++#if defined(CONFIG_LS1043A)
+ 	val = gur_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
+ 	scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4 , val & USB_SQRXTUNE);
+ 	val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
+ 	scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4 , val & USB_SQRXTUNE);
++#endif
+ #elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+ 	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ 	u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
+index f876c56..6ea4e8e 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
+@@ -14,8 +14,11 @@
+ #else
+ #define CONFIG_SYS_FSL_DDRC_ARM_GEN3	/* Enable Freescale ARM DDR3 driver */
+ #endif
++
++#ifndef CONFIG_LS1012A
+ #define CONFIG_SYS_FSL_DDR		/* Freescale DDR driver */
+ #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_5_0
++#endif
+ 
+ /*
+  * Reserve secure memory
+@@ -205,6 +208,35 @@
+ #define CONFIG_SYS_FSL_ERRATUM_A008997
+ #define CONFIG_SYS_FSL_ERRATUM_A009007
+ #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
++#elif defined(CONFIG_LS1012A)
++#define CONFIG_MAX_CPUS                         1
++#define CONFIG_SYS_CACHELINE_SIZE		64
++#define CONFIG_NUM_DDR_CONTROLLERS		1
++#define CONFIG_SYS_CCSRBAR_DEFAULT		0x01000000
++#define CONFIG_SYS_FSL_SEC_COMPAT		5
++#undef	CONFIG_SYS_FSL_DDRC_ARM_GEN3
++
++#define CONFIG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */
++#define CONFIG_SYS_FSL_OCRAM_SIZE		0x200000 /* 2 MiB */
++
++#define GICD_BASE		0x01401000
++#define GICC_BASE		0x01402000
++
++#define CONFIG_SYS_FSL_CCSR_GUR_BE
++#define CONFIG_SYS_FSL_CCSR_SCFG_BE
++#define CONFIG_SYS_FSL_ESDHC_BE
++#define CONFIG_SYS_FSL_WDOG_BE
++#define CONFIG_SYS_FSL_DSPI_BE
++#define CONFIG_SYS_FSL_QSPI_BE
++#define CONFIG_SYS_FSL_PEX_LUT_BE
++
++#define SRDS_MAX_LANES		4
++#define CONFIG_SYS_FSL_SRDS_1
++#define CONFIG_SYS_FSL_PCIE_COMPAT		"fsl,qoriq-pcie-v2.4"
++#define CONFIG_SYS_FSL_SEC_BE
++
++#define CONFIG_SYS_FSL_ERRATUM_A009798
++
+ #else
+ #error SoC not defined
+ #endif
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+index a7522da..e4ff990 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+@@ -14,6 +14,7 @@ static struct cpu_type cpu_type_list[] = {
+ 	CPU_TYPE_ENTRY(LS1043, LS1043, 4),
+ 	CPU_TYPE_ENTRY(LS1023, LS1023, 2),
+ 	CPU_TYPE_ENTRY(LS2040, LS2040, 4),
++	CPU_TYPE_ENTRY(LS1012, LS1012, 1),
+ };
+ 
+ #ifndef CONFIG_SYS_DCACHE_OFF
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+index 7096dac..4a3f4f3 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+@@ -134,6 +134,7 @@ enum srds_prtcl {
+ 	SGMII_2500_FM2_DTSEC6,
+ 	SGMII_2500_FM2_DTSEC9,
+ 	SGMII_2500_FM2_DTSEC10,
++	TX_CLK,
+ 	SERDES_PRCTL_COUNT
+ };
+ 
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+index 2852f9c..5b026f8 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+@@ -62,7 +62,11 @@
+ #define CONFIG_SYS_PCIE2_PHYS_ADDR		0x4800000000ULL
+ #define CONFIG_SYS_PCIE3_PHYS_ADDR		0x5000000000ULL
+ /* LUT registers */
++#ifdef CONFIG_LS1012A
++#define PCIE_LUT_BASE				0xC0000
++#else
+ #define PCIE_LUT_BASE				0x10000
++#endif
+ #define PCIE_LUT_LCTRL0				0x7F8
+ #define PCIE_LUT_DBG				0x7FC
+ 
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+index 56989e1..0822b49 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+@@ -41,6 +41,7 @@ struct cpu_type {
+ 	{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
+ 
+ #define SVR_WO_E		0xFFFFFE
++#define SVR_LS1012		0x870400
+ #define SVR_LS1043		0x879200
+ #define SVR_LS1023		0x879208
+ #define SVR_LS2045		0x870120
+diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h
+new file mode 100644
+index 0000000..3df822e
+--- /dev/null
++++ b/include/fsl_mmdc.h
+@@ -0,0 +1,53 @@
++/*
++ * Copyright 2015 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#ifndef FSL_MMDC_H
++#define FSL_MMDC_H
++
++/* MMDC Registers */
++struct mmdc_p_regs {
++	u32 mdctl;
++	u32 mdpdc;
++	u32 mdotc;
++	u32 mdcfg0;
++	u32 mdcfg1;
++	u32 mdcfg2;
++	u32 mdmisc;
++	u32 mdscr;
++	u32 mdref;
++	u32 res1[2];
++	u32 mdrwd;
++	u32 mdor;
++	u32 mdmrr;
++	u32 mdcfg3lp;
++	u32 mdmr4;
++	u32 mdasp;
++	u32 res3[239];
++	u32 maarcr;
++	u32 mapsr;
++	u32 res4[254];
++	u32 mpzqhwctrl;
++	u32 res5[2];
++	u32 mpwldectrl0;
++	u32 mpwldectrl1;
++	u32 res6;
++	u32 mpodtctrl;
++	u32 mprddqby0dl;
++	u32 mprddqby1dl;
++	u32 mprddqby2dl;
++	u32 mprddqby3dl;
++	u32 res7[4];
++	u32 mpdgctrl0;
++	u32 mpdgctrl1;
++	u32 res8;
++	u32 mprddlctl;
++	u32 res9;
++	u32 mpwrdlctl;
++	u32 res10[25];
++	u32 mpmur0;
++};
++
++#endif /* FSL_MMDC_H */
+diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
+index 4966608..72a5d5b 100644
+--- a/include/linux/usb/xhci-fsl.h
++++ b/include/linux/usb/xhci-fsl.h
+@@ -66,6 +66,10 @@ struct fsl_xhci {
+ #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
+ #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR
+ #define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR
++#elif defined(CONFIG_LS1012A)
++#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
++#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
++#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
+ #endif
+ 
+ #define FSL_USB_XHCI_ADDR	{CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
+-- 
+1.7.9.5
+