diff options
| -rw-r--r-- | package/boot/uboot-rockchip/Makefile | 6 | ||||
| -rw-r--r-- | package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch | 10 | ||||
| -rw-r--r-- | package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch | 571 | ||||
| -rw-r--r-- | package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-plat.c (renamed from package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-platdata.c) | 91 | ||||
| -rw-r--r-- | package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h | 24 |
5 files changed, 31 insertions, 671 deletions
diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index 393e8c3a9f..645422aca4 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -5,10 +5,10 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk -PKG_VERSION:=2021.01 +PKG_VERSION:=2021.04 PKG_RELEASE:=1 -PKG_HASH:=b407e1510a74e863b8b5cb42a24625344f0e0c2fc7582d8c866bd899367d0454 +PKG_HASH:=0d438b1bb5cceb57a18ea2de4a0d51f7be5b05b98717df05938636e0aadfe11a PKG_MAINTAINER:=Tobias Maedel <openwrt@tbspace.de> @@ -75,7 +75,7 @@ ifneq ($(OF_PLATDATA),) mkdir -p $(PKG_BUILD_DIR)/tpl/dts mkdir -p $(PKG_BUILD_DIR)/include/generated - $(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-platdata.c $(PKG_BUILD_DIR)/tpl/dts/dt-platdata.c + $(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-plat.c $(PKG_BUILD_DIR)/tpl/dts/dt-plat.c $(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-structs-gen.h $(PKG_BUILD_DIR)/include/generated/dt-structs-gen.h endif diff --git a/package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch b/package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch index bd401103ea..61a56c2afc 100644 --- a/package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch +++ b/package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch @@ -17,15 +17,13 @@ Signed-off-by: David Bauer <mail@david-bauer.net> --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl -@@ -321,12 +321,6 @@ PHONY += dts_dir +@@ -329,10 +329,6 @@ PHONY += dts_dir dts_dir: $(shell [ -d $(obj)/dts ] || mkdir -p $(obj)/dts) --include/generated/dt-structs-gen.h: $(obj)/$(SPL_BIN).dtb dts_dir FORCE -- $(call if_changed,dtoch) -- --$(obj)/dts/dt-platdata.c: $(obj)/$(SPL_BIN).dtb dts_dir FORCE -- $(call if_changed,dtocc) +-include/generated/dt-structs-gen.h $(u-boot-spl-platdata_c) &: \ +- $(obj)/$(SPL_BIN).dtb dts_dir FORCE +- $(call if_changed,dtoc) - ifdef CONFIG_SAMSUNG ifdef CONFIG_VAR_SIZE_SPL diff --git a/package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch b/package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch deleted file mode 100644 index 60416a6880..0000000000 --- a/package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch +++ /dev/null @@ -1,571 +0,0 @@ -From 4189a8db90ca7edc16cf9509576ca2e74f028c1c Mon Sep 17 00:00:00 2001 -From: David Bauer <mail@david-bauer.net> -Date: Thu, 7 Jan 2021 00:05:46 +0100 -Subject: [PATCH] rockchip: rk3328: Add support for FriendlyARM NanoPi R2S - -This adds support for the NanoPi R2S from FriendlyArm. - -Rockchip RK3328 SoC -1GB DDR4 RAM -Gigabit Ethernet (WAN) -Gigabit Ethernet (USB3) (LAN) -USB 2.0 Host Port -MicroSD slot -Reset button -WAN - LAN - SYS LED - -Signed-off-by: David Bauer <mail@david-bauer.net> ---- - arch/arm/dts/Makefile | 1 + - arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi | 40 +++ - arch/arm/dts/rk3328-nanopi-r2s.dts | 370 +++++++++++++++++++++ - board/rockchip/evb_rk3328/MAINTAINERS | 7 + - configs/nanopi-r2s-rk3328_defconfig | 98 ++++++ - 5 files changed, 516 insertions(+) - create mode 100644 arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi - create mode 100644 arch/arm/dts/rk3328-nanopi-r2s.dts - create mode 100644 configs/nanopi-r2s-rk3328_defconfig - ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -110,6 +110,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ - - dtb-$(CONFIG_ROCKCHIP_RK3328) += \ - rk3328-evb.dtb \ -+ rk3328-nanopi-r2s.dtb \ - rk3328-roc-cc.dtb \ - rk3328-rock64.dtb \ - rk3328-rock-pi-e.dtb ---- /dev/null -+++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi -@@ -0,0 +1,40 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd -+ * (C) Copyright 2020 David Bauer -+ */ -+ -+#include "rk3328-u-boot.dtsi" -+#include "rk3328-sdram-ddr4-666.dtsi" -+/ { -+ chosen { -+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; -+ }; -+}; -+ -+&gpio0 { -+ u-boot,dm-spl; -+}; -+ -+&pinctrl { -+ u-boot,dm-spl; -+}; -+ -+&sdmmc0m1_gpio { -+ u-boot,dm-spl; -+}; -+ -+&pcfg_pull_up_4ma { -+ u-boot,dm-spl; -+}; -+ -+/* Need this and all the pinctrl/gpio stuff above to set pinmux */ -+&vcc_sd { -+ u-boot,dm-spl; -+}; -+ -+&gmac2io { -+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -+ snps,reset-active-low; -+ snps,reset-delays-us = <0 10000 50000>; -+}; ---- /dev/null -+++ b/arch/arm/dts/rk3328-nanopi-r2s.dts -@@ -0,0 +1,370 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2020 David Bauer <mail@david-bauer.net> -+ */ -+ -+/dts-v1/; -+ -+#include <dt-bindings/input/input.h> -+#include <dt-bindings/gpio/gpio.h> -+#include "rk3328.dtsi" -+ -+/ { -+ model = "FriendlyElec NanoPi R2S"; -+ compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328"; -+ -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ gmac_clk: gmac-clock { -+ compatible = "fixed-clock"; -+ clock-frequency = <125000000>; -+ clock-output-names = "gmac_clkin"; -+ #clock-cells = <0>; -+ }; -+ -+ keys { -+ compatible = "gpio-keys"; -+ pinctrl-0 = <&reset_button_pin>; -+ pinctrl-names = "default"; -+ -+ reset { -+ label = "reset"; -+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; -+ linux,code = <KEY_RESTART>; -+ debounce-interval = <50>; -+ }; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; -+ pinctrl-names = "default"; -+ -+ lan_led: led-0 { -+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; -+ label = "nanopi-r2s:green:lan"; -+ }; -+ -+ sys_led: led-1 { -+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; -+ label = "nanopi-r2s:red:sys"; -+ }; -+ -+ wan_led: led-2 { -+ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; -+ label = "nanopi-r2s:green:wan"; -+ }; -+ }; -+ -+ vcc_io_sdio: sdmmcio-regulator { -+ compatible = "regulator-gpio"; -+ enable-active-high; -+ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; -+ pinctrl-0 = <&sdio_vcc_pin>; -+ pinctrl-names = "default"; -+ regulator-name = "vcc_io_sdio"; -+ regulator-always-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-settling-time-us = <5000>; -+ regulator-type = "voltage"; -+ startup-delay-us = <2000>; -+ states = <1800000 0x1 -+ 3300000 0x0>; -+ vin-supply = <&vcc_io_33>; -+ }; -+ -+ vcc_sd: sdmmc-regulator { -+ compatible = "regulator-fixed"; -+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; -+ pinctrl-0 = <&sdmmc0m1_gpio>; -+ pinctrl-names = "default"; -+ regulator-name = "vcc_sd"; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_io_33>; -+ }; -+ -+ vdd_5v: vdd-5v { -+ compatible = "regulator-fixed"; -+ regulator-name = "vdd_5v"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&cpu2 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&cpu3 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&gmac2io { -+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; -+ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; -+ clock_in_out = "input"; -+ phy-handle = <&rtl8211e>; -+ phy-mode = "rgmii"; -+ phy-supply = <&vcc_io_33>; -+ pinctrl-0 = <&rgmiim1_pins>; -+ pinctrl-names = "default"; -+ rx_delay = <0x18>; -+ snps,aal; -+ tx_delay = <0x24>; -+ status = "okay"; -+ -+ mdio { -+ compatible = "snps,dwmac-mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ rtl8211e: ethernet-phy@1 { -+ compatible = "ethernet-phy-id001c.c915", -+ "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ pinctrl-0 = <ð_phy_reset_pin>; -+ pinctrl-names = "default"; -+ reset-assert-us = <10000>; -+ reset-deassert-us = <50000>; -+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ status = "okay"; -+ -+ rk805: pmic@18 { -+ compatible = "rockchip,rk805"; -+ reg = <0x18>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>; -+ #clock-cells = <1>; -+ clock-output-names = "xin32k", "rk805-clkout2"; -+ gpio-controller; -+ #gpio-cells = <2>; -+ pinctrl-0 = <&pmic_int_l>; -+ pinctrl-names = "default"; -+ rockchip,system-power-controller; -+ wakeup-source; -+ -+ vcc1-supply = <&vdd_5v>; -+ vcc2-supply = <&vdd_5v>; -+ vcc3-supply = <&vdd_5v>; -+ vcc4-supply = <&vdd_5v>; -+ vcc5-supply = <&vcc_io_33>; -+ vcc6-supply = <&vdd_5v>; -+ -+ regulators { -+ vdd_log: DCDC_REG1 { -+ regulator-name = "vdd_log"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1450000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1000000>; -+ }; -+ }; -+ -+ vdd_arm: DCDC_REG2 { -+ regulator-name = "vdd_arm"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1450000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <950000>; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_io_33: DCDC_REG4 { -+ regulator-name = "vcc_io_33"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcc_18: LDO_REG1 { -+ regulator-name = "vcc_18"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc18_emmc: LDO_REG2 { -+ regulator-name = "vcc18_emmc"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdd_10: LDO_REG3 { -+ regulator-name = "vdd_10"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1000000>; -+ regulator-max-microvolt = <1000000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1000000>; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&io_domains { -+ pmuio-supply = <&vcc_io_33>; -+ vccio1-supply = <&vcc_io_33>; -+ vccio2-supply = <&vcc18_emmc>; -+ vccio3-supply = <&vcc_io_sdio>; -+ vccio4-supply = <&vcc_18>; -+ vccio5-supply = <&vcc_io_33>; -+ vccio6-supply = <&vcc_io_33>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ button { -+ reset_button_pin: reset-button-pin { -+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ ethernet-phy { -+ eth_phy_reset_pin: eth-phy-reset-pin { -+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ leds { -+ lan_led_pin: lan-led-pin { -+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ sys_led_pin: sys-led-pin { -+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wan_led_pin: wan-led-pin { -+ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pmic { -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ sd { -+ sdio_vcc_pin: sdio-vcc-pin { -+ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; -+ -+&pwm2 { -+ status = "okay"; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ disable-wp; -+ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; -+ pinctrl-names = "default"; -+ sd-uhs-sdr12; -+ sd-uhs-sdr25; -+ sd-uhs-sdr50; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc_sd>; -+ vqmmc-supply = <&vcc_io_sdio>; -+ status = "okay"; -+}; -+ -+&tsadc { -+ rockchip,hw-tshut-mode = <0>; -+ rockchip,hw-tshut-polarity = <0>; -+ status = "okay"; -+}; -+ -+&u2phy { -+ status = "okay"; -+}; -+ -+&u2phy_host { -+ status = "okay"; -+}; -+ -+&u2phy_otg { -+ status = "okay"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&usb20_otg { -+ status = "okay"; -+ dr_mode = "host"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; ---- a/board/rockchip/evb_rk3328/MAINTAINERS -+++ b/board/rockchip/evb_rk3328/MAINTAINERS -@@ -5,6 +5,13 @@ F: board/rockchip/evb_rk3328 - F: include/configs/evb_rk3328.h - F: configs/evb-rk3328_defconfig - -+NANOPI-R2S-RK3328 -+M: David Bauer <mail@david-bauer.net> -+S: Maintained -+F: configs/nanopi-r2s-rk3328_defconfig -+F: arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi -+F: arch/arm/dts/rk3328-nanopi-r2s.dts -+ - ROC-RK3328-CC - M: Loic Devulder <ldevulder@suse.com> - M: Chen-Yu Tsai <wens@csie.org> ---- /dev/null -+++ b/configs/nanopi-r2s-rk3328_defconfig -@@ -0,0 +1,98 @@ -+CONFIG_ARM=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00200000 -+CONFIG_SPL_GPIO_SUPPORT=y -+CONFIG_ENV_OFFSET=0x3F8000 -+CONFIG_ROCKCHIP_RK3328=y -+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_TPL_LIBCOMMON_SUPPORT=y -+CONFIG_TPL_LIBGENERIC_SUPPORT=y -+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_DEBUG_UART_BASE=0xFF130000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SYSINFO=y -+CONFIG_DEBUG_UART=y -+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 -+# CONFIG_ANDROID_BOOT_IMAGE is not set -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s.dtb" -+CONFIG_MISC_INIT_R=y -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_TPL_SYS_MALLOC_SIMPLE=y -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_I2C_SUPPORT=y -+CONFIG_SPL_POWER_SUPPORT=y -+CONFIG_SPL_ATF=y -+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TIME=y -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_TPL_OF_CONTROL=y -+CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2s" -+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_TPL_OF_PLATDATA=y -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_TPL_DM=y -+CONFIG_REGMAP=y -+CONFIG_SPL_REGMAP=y -+CONFIG_TPL_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_SPL_SYSCON=y -+CONFIG_TPL_SYSCON=y -+CONFIG_CLK=y -+CONFIG_SPL_CLK=y -+CONFIG_FASTBOOT_BUF_ADDR=0x800800 -+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_SF_DEFAULT_SPEED=20000000 -+CONFIG_DM_ETH=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PINCTRL=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_SPL_DM_REGULATOR=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_SPL_DM_REGULATOR_FIXED=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_RAM=y -+CONFIG_SPL_RAM=y -+CONFIG_TPL_RAM=y -+CONFIG_DM_RESET=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYSRESET=y -+# CONFIG_TPL_SYSRESET is not set -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC2=y -+CONFIG_USB_DWC3=y -+# CONFIG_USB_DWC3_GADGET is not set -+CONFIG_USB_GADGET=y -+CONFIG_USB_GADGET_DWC2_OTG=y -+CONFIG_SPL_TINY_MEMSET=y -+CONFIG_TPL_TINY_MEMSET=y -+CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-platdata.c b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-plat.c index 17e1e302a5..1818461ec8 100644 --- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-platdata.c +++ b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-plat.c @@ -1,11 +1,12 @@ /* * DO NOT MODIFY * - * This file was generated by dtoc from a .dtb (device tree binary) file. + * Declares the U_BOOT_DRIVER() records and platform data. + * This was generated by dtoc from a .dtb (device tree binary) file. */ -/* Allow use of U_BOOT_DEVICE() in this file */ -#define DT_PLATDATA_C +/* Allow use of U_BOOT_DRVINFO() in this file */ +#define DT_PLAT_C #include <common.h> #include <dm.h> @@ -16,10 +17,10 @@ static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { .reg = {0xff440000, 0x1000}, .rockchip_grf = 0x3a, }; -U_BOOT_DEVICE(clock_controller_at_ff440000) = { +U_BOOT_DRVINFO(clock_controller_at_ff440000) = { .name = "rockchip_rk3328_cru", - .platdata = &dtv_clock_controller_at_ff440000, - .platdata_size = sizeof(dtv_clock_controller_at_ff440000), + .plat = &dtv_clock_controller_at_ff440000, + .plat_size = sizeof(dtv_clock_controller_at_ff440000), .parent_idx = -1, }; @@ -53,30 +54,14 @@ static struct dtd_rockchip_rk3328_dmc dtv_dmc = { 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9}, }; -U_BOOT_DEVICE(dmc) = { +U_BOOT_DRVINFO(dmc) = { .name = "rockchip_rk3328_dmc", - .platdata = &dtv_dmc, - .platdata_size = sizeof(dtv_dmc), + .plat = &dtv_dmc, + .plat_size = sizeof(dtv_dmc), .parent_idx = -1, }; -/* Node /pinctrl/gpio0@ff210000 index 2 */ -static struct dtd_rockchip_gpio_bank dtv_gpio0_at_ff210000 = { - .clocks = { - {0, {200}},}, - .gpio_controller = true, - .interrupt_controller = true, - .interrupts = {0x0, 0x33, 0x4}, - .reg = {0xff210000, 0x100}, -}; -U_BOOT_DEVICE(gpio0_at_ff210000) = { - .name = "rockchip_gpio_bank", - .platdata = &dtv_gpio0_at_ff210000, - .platdata_size = sizeof(dtv_gpio0_at_ff210000), - .parent_idx = 4, -}; - -/* Node /mmc@ff500000 index 3 */ +/* Node /mmc@ff500000 index 2 */ static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = { .bus_width = 0x4, .cap_sd_highspeed = true, @@ -100,44 +85,14 @@ static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = { .vmmc_supply = 0x4b, .vqmmc_supply = 0x1e, }; -U_BOOT_DEVICE(mmc_at_ff500000) = { +U_BOOT_DRVINFO(mmc_at_ff500000) = { .name = "rockchip_rk3288_dw_mshc", - .platdata = &dtv_mmc_at_ff500000, - .platdata_size = sizeof(dtv_mmc_at_ff500000), - .parent_idx = -1, -}; - -/* Node /pinctrl index 4 */ -static struct dtd_rockchip_rk3328_pinctrl dtv_pinctrl = { - .ranges = true, - .rockchip_grf = 0x3a, -}; -U_BOOT_DEVICE(pinctrl) = { - .name = "rockchip_rk3328_pinctrl", - .platdata = &dtv_pinctrl, - .platdata_size = sizeof(dtv_pinctrl), - .parent_idx = -1, -}; - -/* Node /sdmmc-regulator index 5 */ -static struct dtd_regulator_fixed dtv_sdmmc_regulator = { - .gpio = {0x61, 0x1e, 0x1}, - .pinctrl_0 = 0x67, - .pinctrl_names = "default", - .regulator_boot_on = true, - .regulator_max_microvolt = 0x325aa0, - .regulator_min_microvolt = 0x325aa0, - .regulator_name = "vcc_sd", - .vin_supply = 0x1c, -}; -U_BOOT_DEVICE(sdmmc_regulator) = { - .name = "regulator_fixed", - .platdata = &dtv_sdmmc_regulator, - .platdata_size = sizeof(dtv_sdmmc_regulator), + .plat = &dtv_mmc_at_ff500000, + .plat_size = sizeof(dtv_mmc_at_ff500000), .parent_idx = -1, }; -/* Node /serial@ff130000 index 6 */ +/* Node /serial@ff130000 index 3 */ static struct dtd_ns16550_serial dtv_serial_at_ff130000 = { .clock_frequency = 0x16e3600, .clocks = { @@ -152,23 +107,21 @@ static struct dtd_ns16550_serial dtv_serial_at_ff130000 = { .reg_io_width = 0x4, .reg_shift = 0x2, }; -U_BOOT_DEVICE(serial_at_ff130000) = { +U_BOOT_DRVINFO(serial_at_ff130000) = { .name = "ns16550_serial", - .platdata = &dtv_serial_at_ff130000, - .platdata_size = sizeof(dtv_serial_at_ff130000), + .plat = &dtv_serial_at_ff130000, + .plat_size = sizeof(dtv_serial_at_ff130000), .parent_idx = -1, }; -/* Node /syscon@ff100000 index 7 */ +/* Node /syscon@ff100000 index 4 */ static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { .reg = {0xff100000, 0x1000}, }; -U_BOOT_DEVICE(syscon_at_ff100000) = { +U_BOOT_DRVINFO(syscon_at_ff100000) = { .name = "rockchip_rk3328_grf", - .platdata = &dtv_syscon_at_ff100000, - .platdata_size = sizeof(dtv_syscon_at_ff100000), + .plat = &dtv_syscon_at_ff100000, + .plat_size = sizeof(dtv_syscon_at_ff100000), .parent_idx = -1, }; -void dm_populate_phandle_data(void) { -} diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h index 847b121a34..b1ff08a927 100644 --- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h +++ b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h @@ -1,7 +1,8 @@ /* * DO NOT MODIFY * - * This file was generated by dtoc from a .dtb (device tree binary) file. + * Defines the structs used to hold devicetree data. + * This was generated by dtoc from a .dtb (device tree binary) file. */ #include <stdbool.h> @@ -18,23 +19,6 @@ struct dtd_ns16550_serial { fdt32_t reg_io_width; fdt32_t reg_shift; }; -struct dtd_regulator_fixed { - fdt32_t gpio[3]; - fdt32_t pinctrl_0; - const char * pinctrl_names; - bool regulator_boot_on; - fdt32_t regulator_max_microvolt; - fdt32_t regulator_min_microvolt; - const char * regulator_name; - fdt32_t vin_supply; -}; -struct dtd_rockchip_gpio_bank { - struct phandle_1_arg clocks[1]; - bool gpio_controller; - bool interrupt_controller; - fdt32_t interrupts[3]; - fdt64_t reg[2]; -}; struct dtd_rockchip_rk3288_dw_mshc { fdt32_t bus_width; bool cap_sd_highspeed; @@ -65,7 +49,3 @@ struct dtd_rockchip_rk3328_dmc { struct dtd_rockchip_rk3328_grf { fdt64_t reg[2]; }; -struct dtd_rockchip_rk3328_pinctrl { - bool ranges; - fdt32_t rockchip_grf; -}; |