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-rw-r--r--package/boot/uboot-envtools/files/realtek1
-rw-r--r--target/linux/realtek/dts-5.10/rtl8382_d-link_dgs-1210-20.dts104
-rw-r--r--target/linux/realtek/image/rtl838x.mk6
3 files changed, 111 insertions, 0 deletions
diff --git a/package/boot/uboot-envtools/files/realtek b/package/boot/uboot-envtools/files/realtek
index af48d27078..93cccfdc3e 100644
--- a/package/boot/uboot-envtools/files/realtek
+++ b/package/boot/uboot-envtools/files/realtek
@@ -9,6 +9,7 @@ board=$(board_name)
case "$board" in
d-link,dgs-1210-16|\
+d-link,dgs-1210-20|\
d-link,dgs-1210-28|\
d-link,dgs-1210-10p|\
zyxel,gs1900-8|\
diff --git a/target/linux/realtek/dts-5.10/rtl8382_d-link_dgs-1210-20.dts b/target/linux/realtek/dts-5.10/rtl8382_d-link_dgs-1210-20.dts
new file mode 100644
index 0000000000..cd495bc343
--- /dev/null
+++ b/target/linux/realtek/dts-5.10/rtl8382_d-link_dgs-1210-20.dts
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl8382_d-link_dgs-1210.dtsi"
+
+/ {
+ compatible = "d-link,dgs-1210-20", "realtek,rtl838x-soc";
+ model = "D-Link DGS-1210-20";
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio1 34 GPIO_ACTIVE_LOW>;
+ open-source;
+ };
+
+ keys {
+ compatible = "gpio-keys-polled";
+ poll-interval = <20>;
+
+ reset {
+ label = "reset";
+ gpios = <&gpio1 33 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ gpio1: rtl8231-gpio {
+ compatible = "realtek,rtl8231-gpio";
+ #gpio-cells = <2>;
+ gpio-controller;
+ indirect-access-bus-id = <0>;
+ };
+};
+
+&ethernet0 {
+ mdio: mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <&ethernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ EXTERNAL_PHY(0)
+ EXTERNAL_PHY(1)
+ EXTERNAL_PHY(2)
+ EXTERNAL_PHY(3)
+ EXTERNAL_PHY(4)
+ EXTERNAL_PHY(5)
+ EXTERNAL_PHY(6)
+ EXTERNAL_PHY(7)
+
+ INTERNAL_PHY(8)
+ INTERNAL_PHY(9)
+ INTERNAL_PHY(10)
+ INTERNAL_PHY(11)
+ INTERNAL_PHY(12)
+ INTERNAL_PHY(13)
+ INTERNAL_PHY(14)
+ INTERNAL_PHY(15)
+
+ EXTERNAL_SFP_PHY(24)
+ EXTERNAL_SFP_PHY(25)
+ EXTERNAL_SFP_PHY(26)
+ EXTERNAL_SFP_PHY(27)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(0, 1, qsgmii)
+ SWITCH_PORT(1, 2, qsgmii)
+ SWITCH_PORT(2, 3, qsgmii)
+ SWITCH_PORT(3, 4, qsgmii)
+ SWITCH_PORT(4, 5, qsgmii)
+ SWITCH_PORT(5, 6, qsgmii)
+ SWITCH_PORT(6, 7, qsgmii)
+ SWITCH_PORT(7, 8, qsgmii)
+
+ SWITCH_PORT(8, 9, internal)
+ SWITCH_PORT(9, 10, internal)
+ SWITCH_PORT(10, 11, internal)
+ SWITCH_PORT(11, 12, internal)
+ SWITCH_PORT(12, 13, internal)
+ SWITCH_PORT(13, 14, internal)
+ SWITCH_PORT(14, 15, internal)
+ SWITCH_PORT(15, 16, internal)
+
+ SWITCH_PORT(24, 17, qsgmii)
+ SWITCH_PORT(25, 18, qsgmii)
+ SWITCH_PORT(26, 19, qsgmii)
+ SWITCH_PORT(27, 20, qsgmii)
+
+ port@28 {
+ ethernet = <&ethernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
diff --git a/target/linux/realtek/image/rtl838x.mk b/target/linux/realtek/image/rtl838x.mk
index 289e37db16..df145cfb69 100644
--- a/target/linux/realtek/image/rtl838x.mk
+++ b/target/linux/realtek/image/rtl838x.mk
@@ -30,6 +30,12 @@ define Device/d-link_dgs-1210-16
endef
TARGET_DEVICES += d-link_dgs-1210-16
+define Device/d-link_dgs-1210-20
+ $(Device/d-link_dgs-1210)
+ DEVICE_MODEL := DGS-1210-20
+endef
+TARGET_DEVICES += d-link_dgs-1210-20
+
define Device/d-link_dgs-1210-28
$(Device/d-link_dgs-1210)
DEVICE_MODEL := DGS-1210-28