diff options
33 files changed, 423 insertions, 432 deletions
diff --git a/target/linux/ipq40xx/patches-5.4/0001-v5.7-ARM-qcom-Add-support-for-IPQ40xx.patch b/target/linux/ipq40xx/patches-5.4/0001-v5.7-ARM-qcom-Add-support-for-IPQ40xx.patch new file mode 100644 index 0000000000..8aa71f360f --- /dev/null +++ b/target/linux/ipq40xx/patches-5.4/0001-v5.7-ARM-qcom-Add-support-for-IPQ40xx.patch @@ -0,0 +1,42 @@ +From f125e2d4339dda6937865f975470b29c84714c9b Mon Sep 17 00:00:00 2001 +From: Christian Lamparter <chunkeey@gmail.com> +Date: Mon, 6 Jan 2020 14:57:15 +0100 +Subject: [PATCH] ARM: qcom: Add support for IPQ40xx + +Add support for the Qualcomm IPQ40xx SoC in Kconfig. +Also add its appropriate textofs. + +Signed-off-by: Christian Lamparter <chunkeey@gmail.com> +Signed-off-by: John Crispin <john@phrozen.org> +Tested-by: Robert Marko <robert.marko@sartura.hr> +Cc: Luka Perkov <luka.perkov@sartura.hr> +Signed-off-by: Arnd Bergmann <arnd@arndb.de> +--- + arch/arm/Makefile | 1 + + arch/arm/mach-qcom/Kconfig | 5 +++++ + 2 files changed, 6 insertions(+) + +--- a/arch/arm/Makefile ++++ b/arch/arm/Makefile +@@ -152,6 +152,7 @@ textofs-$(CONFIG_PM_H1940) := 0x001 + ifeq ($(CONFIG_ARCH_SA1100),y) + textofs-$(CONFIG_SA1111) := 0x00208000 + endif ++textofs-$(CONFIG_ARCH_IPQ40XX) := 0x00208000 + textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000 + textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000 + textofs-$(CONFIG_ARCH_MESON) := 0x00208000 +--- a/arch/arm/mach-qcom/Kconfig ++++ b/arch/arm/mach-qcom/Kconfig +@@ -12,6 +12,11 @@ menuconfig ARCH_QCOM + + if ARCH_QCOM + ++config ARCH_IPQ40XX ++ bool "Enable support for IPQ40XX" ++ select CLKSRC_QCOM ++ select HAVE_ARM_ARCH_TIMER ++ + config ARCH_MSM8X60 + bool "Enable support for MSM8X60" + select CLKSRC_QCOM diff --git a/target/linux/ipq40xx/patches-5.4/088-v5.6-regulator-add-IPQ4019-SDHCI-VQMMC-LDO-driver.patch b/target/linux/ipq40xx/patches-5.4/0002-01-v5.6-regulator-add-IPQ4019-SDHCI-VQMMC-LDO-driver.patch index aaf8c807ed..aaf8c807ed 100644 --- a/target/linux/ipq40xx/patches-5.4/088-v5.6-regulator-add-IPQ4019-SDHCI-VQMMC-LDO-driver.patch +++ b/target/linux/ipq40xx/patches-5.4/0002-01-v5.6-regulator-add-IPQ4019-SDHCI-VQMMC-LDO-driver.patch diff --git a/target/linux/ipq40xx/patches-5.4/089-v5.5-ARM-dts-qcom-ipq4019-Add-SDHCI-controller-node.patch b/target/linux/ipq40xx/patches-5.4/0002-02-v5.5-ARM-dts-qcom-ipq4019-Add-SDHCI-controller-node.patch index b3e0a20b32..25fce8daf0 100644 --- a/target/linux/ipq40xx/patches-5.4/089-v5.5-ARM-dts-qcom-ipq4019-Add-SDHCI-controller-node.patch +++ b/target/linux/ipq40xx/patches-5.4/0002-02-v5.5-ARM-dts-qcom-ipq4019-Add-SDHCI-controller-node.patch @@ -15,7 +15,7 @@ Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi -@@ -209,6 +209,18 @@ +@@ -206,6 +206,18 @@ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/target/linux/ipq40xx/patches-5.4/0003-v5.6-ARM-dts-qcom-Add-nodes-for-SMP-boot-in-IPQ40xx.patch b/target/linux/ipq40xx/patches-5.4/0003-v5.6-ARM-dts-qcom-Add-nodes-for-SMP-boot-in-IPQ40xx.patch new file mode 100644 index 0000000000..3a4127febf --- /dev/null +++ b/target/linux/ipq40xx/patches-5.4/0003-v5.6-ARM-dts-qcom-Add-nodes-for-SMP-boot-in-IPQ40xx.patch @@ -0,0 +1,71 @@ +From 5e4548922009870a38bcf1d887317676d4e08f54 Mon Sep 17 00:00:00 2001 +From: Damir Franusic <damir.franusic@sartura.hr> +Date: Thu, 21 Nov 2019 16:29:02 +0100 +Subject: [PATCH] ARM: dts: qcom: Add nodes for SMP boot in IPQ40xx + +Add missing nodes and properties to enable SMP +support on IPQ40xx devices. + +Booting without "saw_l2" node: + +[ 0.001400] CPU: Testing write buffer coherency: ok +[ 0.001856] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 +[ 0.060163] Setting up static identity map for 0x80300000 - 0x80300060 +[ 0.080140] rcu: Hierarchical SRCU implementation. +[ 0.120258] smp: Bringing up secondary CPUs ... +[ 0.200540] CPU1: failed to boot: -19 +[ 0.280689] CPU2: failed to boot: -19 +[ 0.360874] CPU3: failed to boot: -19 +[ 0.360966] smp: Brought up 1 node, 1 CPU +[ 0.360979] SMP: Total of 1 processors activated (96.00 BogoMIPS). +[ 0.360988] CPU: All CPU(s) started in SVC mode. + +Then, booting with "saw_l2" node present (this patch applied): + +[ 0.001450] CPU: Testing write buffer coherency: ok +[ 0.001904] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 +[ 0.060161] Setting up static identity map for 0x80300000 - 0x80300060 +[ 0.080137] rcu: Hierarchical SRCU implementation. +[ 0.120252] smp: Bringing up secondary CPUs ... +[ 0.200958] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001 +[ 0.281091] CPU2: thread -1, cpu 2, socket 0, mpidr 80000002 +[ 0.361264] CPU3: thread -1, cpu 3, socket 0, mpidr 80000003 +[ 0.361430] smp: Brought up 1 node, 4 CPUs +[ 0.361460] SMP: Total of 4 processors activated (384.00 BogoMIPS). +[ 0.361469] CPU: All CPU(s) started in SVC mode. + +Signed-off-by: Damir Franusic <damir.franusic@sartura.hr> +Cc: Luka Perkov <luka.perkov@sartura.hr> +Cc: Robert Marko <robert.marko@sartura.hr> +Cc: Andy Gross <agross@kernel.org> +Cc: Rob Herring <robh+dt@kernel.org> +Cc: linux-arm-msm@vger.kernel.org +Link: https://lore.kernel.org/r/20191121152902.21394-1-damir.franusic@gmail.com +Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> +--- + arch/arm/boot/dts/qcom-ipq4019.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi +@@ -102,6 +102,7 @@ + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; ++ qcom,saw = <&saw_l2>; + }; + }; + +@@ -353,6 +354,12 @@ + regulator; + }; + ++ saw_l2: regulator@b012000 { ++ compatible = "qcom,saw2"; ++ reg = <0xb012000 0x1000>; ++ regulator; ++ }; ++ + blsp1_uart1: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78af000 0x200>; diff --git a/target/linux/ipq40xx/patches-5.4/0003-v5.7-ARM-dts-qcom-add-gpio-ranges-property.patch b/target/linux/ipq40xx/patches-5.4/0003-v5.7-ARM-dts-qcom-add-gpio-ranges-property.patch new file mode 100644 index 0000000000..6922bc8ff3 --- /dev/null +++ b/target/linux/ipq40xx/patches-5.4/0003-v5.7-ARM-dts-qcom-add-gpio-ranges-property.patch @@ -0,0 +1,119 @@ +From 8b99dc0922618062a1589ebd74df6108b4f9ac22 Mon Sep 17 00:00:00 2001 +From: Christian Lamparter <chunkeey@gmail.com> +Date: Wed, 8 Jan 2020 13:54:55 +0100 +Subject: [PATCH] ARM: dts: qcom: add gpio-ranges property + +This patch adds the gpio-ranges property to almost all of +the Qualcomm ARM platforms that utilize the pinctrl-msm +framework. + +The gpio-ranges property is part of the gpiolib subsystem. +As a result, the binding text is available in section +"2.1 gpio- and pin-controller interaction" of +Documentation/devicetree/bindings/gpio/gpio.txt + +For more information please see the patch titled: +"pinctrl: msm: fix gpio-hog related boot issues" from +this series. + +Reported-by: Sven Eckelmann <sven.eckelmann@openmesh.com> +Tested-by: Sven Eckelmann <sven.eckelmann@openmesh.com> [ipq4019] +Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> +Reviewed-by: Linus Walleij <linus.walleij@linaro.org> +Signed-off-by: Christian Lamparter <chunkeey@gmail.com> +Tested-by: Robert Marko <robert.marko@sartura.hr> [ipq4019] +Cc: Luka Perkov <luka.perkov@sartura.hr> +Signed-off-by: Robert Marko <robert.marko@sartura.hr> +Link: https://lore.kernel.org/r/20200108125455.308969-1-robert.marko@sartura.hr +Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> +--- + arch/arm/boot/dts/qcom-apq8064.dtsi | 1 + + arch/arm/boot/dts/qcom-apq8084.dtsi | 1 + + arch/arm/boot/dts/qcom-ipq4019.dtsi | 1 + + arch/arm/boot/dts/qcom-ipq8064.dtsi | 1 + + arch/arm/boot/dts/qcom-mdm9615.dtsi | 1 + + arch/arm/boot/dts/qcom-msm8660.dtsi | 1 + + arch/arm/boot/dts/qcom-msm8960.dtsi | 1 + + arch/arm/boot/dts/qcom-msm8974.dtsi | 1 + + 8 files changed, 8 insertions(+) + +--- a/arch/arm/boot/dts/qcom-apq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-apq8064.dtsi +@@ -350,6 +350,7 @@ + reg = <0x800000 0x4000>; + + gpio-controller; ++ gpio-ranges = <&tlmm_pinmux 0 0 90>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; +--- a/arch/arm/boot/dts/qcom-apq8084.dtsi ++++ b/arch/arm/boot/dts/qcom-apq8084.dtsi +@@ -401,6 +401,7 @@ + compatible = "qcom,apq8084-pinctrl"; + reg = <0xfd510000 0x4000>; + gpio-controller; ++ gpio-ranges = <&tlmm 0 0 147>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; +--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi +@@ -201,6 +201,7 @@ + compatible = "qcom,ipq4019-pinctrl"; + reg = <0x01000000 0x300000>; + gpio-controller; ++ gpio-ranges = <&tlmm 0 0 100>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -119,6 +119,7 @@ + reg = <0x800000 0x4000>; + + gpio-controller; ++ gpio-ranges = <&qcom_pinmux 0 0 69>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; +--- a/arch/arm/boot/dts/qcom-mdm9615.dtsi ++++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi +@@ -128,6 +128,7 @@ + msmgpio: pinctrl@800000 { + compatible = "qcom,mdm9615-pinctrl"; + gpio-controller; ++ gpio-ranges = <&msmgpio 0 0 88>; + #gpio-cells = <2>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; +--- a/arch/arm/boot/dts/qcom-msm8660.dtsi ++++ b/arch/arm/boot/dts/qcom-msm8660.dtsi +@@ -115,6 +115,7 @@ + reg = <0x800000 0x4000>; + + gpio-controller; ++ gpio-ranges = <&tlmm 0 0 173>; + #gpio-cells = <2>; + interrupts = <0 16 0x4>; + interrupt-controller; +--- a/arch/arm/boot/dts/qcom-msm8960.dtsi ++++ b/arch/arm/boot/dts/qcom-msm8960.dtsi +@@ -107,6 +107,7 @@ + msmgpio: pinctrl@800000 { + compatible = "qcom,msm8960-pinctrl"; + gpio-controller; ++ gpio-ranges = <&msmgpio 0 0 152>; + #gpio-cells = <2>; + interrupts = <0 16 0x4>; + interrupt-controller; +--- a/arch/arm/boot/dts/qcom-msm8974.dtsi ++++ b/arch/arm/boot/dts/qcom-msm8974.dtsi +@@ -707,6 +707,7 @@ + compatible = "qcom,msm8974-pinctrl"; + reg = <0xfd510000 0x4000>; + gpio-controller; ++ gpio-ranges = <&msmgpio 0 0 146>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; diff --git a/target/linux/ipq40xx/patches-5.4/086-ipq40xx-fix-high-resolution-timer.patch b/target/linux/ipq40xx/patches-5.4/0004-v5.8-ARM-dts-qcom-ipq4019-fix-high-resolution-timer.patch index 3bfd0d99e0..f82021f4cd 100644 --- a/target/linux/ipq40xx/patches-5.4/086-ipq40xx-fix-high-resolution-timer.patch +++ b/target/linux/ipq40xx/patches-5.4/0004-v5.8-ARM-dts-qcom-ipq4019-fix-high-resolution-timer.patch @@ -1,7 +1,7 @@ -From 09f145f417a5d64d6b8d4476699dfb0eccc6c784 Mon Sep 17 00:00:00 2001 +From 8acc36189dcaf4487d8c6ba7445948f39b1d248a Mon Sep 17 00:00:00 2001 From: Abhishek Sahu <absahu@codeaurora.org> -Date: Tue, 7 May 2019 10:14:05 +0300 -Subject: [PATCH] ipq40xx: fix high resolution timer +Date: Fri, 3 Apr 2020 13:40:40 +0200 +Subject: [PATCH] ARM: dts: qcom: ipq4019: fix high resolution timer Cherry-picked from CAF QSDK repo. Original commit message: @@ -10,9 +10,13 @@ mode and clock source operates in 10ms resolution. The always-on property needs to be given for timer device tree node to make clock source working in 1ns resolution. -Change-Id: I7c00b3c74d97c2a30ac9f05e18b511a0550fd459 Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Pavel Kubelun <be.dissent@gmail.com> +Signed-off-by: Christian Lamparter <chunkeey@gmail.com> +Tested-by: Robert Marko <robert.marko@sartura.hr> +Cc: Luka Perkov <luka.perkov@sartura.hr> +Link: https://lore.kernel.org/r/20200403114040.349787-1-robert.marko@sartura.hr +Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/ipq40xx/patches-5.4/0005-v5.8-02-ARM-dts-qcom-ipq4019-add-MDIO-node.patch b/target/linux/ipq40xx/patches-5.4/0005-v5.8-02-ARM-dts-qcom-ipq4019-add-MDIO-node.patch new file mode 100644 index 0000000000..1976686e8f --- /dev/null +++ b/target/linux/ipq40xx/patches-5.4/0005-v5.8-02-ARM-dts-qcom-ipq4019-add-MDIO-node.patch @@ -0,0 +1,57 @@ +From 9c8c0f70ec6fdac2398632c723c48277be09b7c0 Mon Sep 17 00:00:00 2001 +From: Robert Marko <robert.marko@sartura.hr> +Date: Thu, 30 Apr 2020 11:07:07 +0200 +Subject: [PATCH] ARM: dts: qcom: ipq4019: add MDIO node + +This patch adds the necessary MDIO interface node +to the Qualcomm IPQ4019 DTSI. + +Built-in QCA8337N switch is managed using it, +and since we have a driver for it lets add it. + +Signed-off-by: Christian Lamparter <chunkeey@gmail.com> +Signed-off-by: Robert Marko <robert.marko@sartura.hr> +Reviewed-by: Andrew Lunn <andrew@lunn.ch> +Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> +Cc: Luka Perkov <luka.perkov@sartura.hr> +Signed-off-by: David S. Miller <davem@davemloft.net> +--- + arch/arm/boot/dts/qcom-ipq4019.dtsi | 28 ++++++++++++++++++++++++++++ + 1 file changed, 28 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi +@@ -577,5 +577,33 @@ + "legacy"; + status = "disabled"; + }; ++ ++ mdio: mdio@90000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "qcom,ipq4019-mdio"; ++ reg = <0x90000 0x64>; ++ status = "disabled"; ++ ++ ethphy0: ethernet-phy@0 { ++ reg = <0>; ++ }; ++ ++ ethphy1: ethernet-phy@1 { ++ reg = <1>; ++ }; ++ ++ ethphy2: ethernet-phy@2 { ++ reg = <2>; ++ }; ++ ++ ethphy3: ethernet-phy@3 { ++ reg = <3>; ++ }; ++ ++ ethphy4: ethernet-phy@4 { ++ reg = <4>; ++ }; ++ }; + }; + }; diff --git a/target/linux/ipq40xx/patches-5.4/039-crypto-qce-add-CRYPTO_ALG_KERN_DRIVER_ONLY-flag.patch b/target/linux/ipq40xx/patches-5.4/0006-v5.5-crypto-qce-add-CRYPTO_ALG_KERN_DRIVER_ONLY-flag.patch index 415d6fff99..415d6fff99 100644 --- a/target/linux/ipq40xx/patches-5.4/039-crypto-qce-add-CRYPTO_ALG_KERN_DRIVER_ONLY-flag.patch +++ b/target/linux/ipq40xx/patches-5.4/0006-v5.5-crypto-qce-add-CRYPTO_ALG_KERN_DRIVER_ONLY-flag.patch diff --git a/target/linux/ipq40xx/patches-5.4/040-crypto-qce-switch-to-skcipher-API.patch b/target/linux/ipq40xx/patches-5.4/0007-v5.5-crypto-qce-switch-to-skcipher-API.patch index 4dcb942150..4dcb942150 100644 --- a/target/linux/ipq40xx/patches-5.4/040-crypto-qce-switch-to-skcipher-API.patch +++ b/target/linux/ipq40xx/patches-5.4/0007-v5.5-crypto-qce-switch-to-skcipher-API.patch diff --git a/target/linux/ipq40xx/patches-5.4/041-crypto-qce-fix-ctr-aes-qce-block-chunk-sizes.patch b/target/linux/ipq40xx/patches-5.4/0008-v5.6-crypto-qce-fix-ctr-aes-qce-block-chunk-sizes.patch index ac4f163f4a..ac4f163f4a 100644 --- a/target/linux/ipq40xx/patches-5.4/041-crypto-qce-fix-ctr-aes-qce-block-chunk-sizes.patch +++ b/target/linux/ipq40xx/patches-5.4/0008-v5.6-crypto-qce-fix-ctr-aes-qce-block-chunk-sizes.patch diff --git a/target/linux/ipq40xx/patches-5.4/042-crypto-qce-fix-xts-aes-qce-key-sizes.patch b/target/linux/ipq40xx/patches-5.4/0009-v5.6-crypto-qce-fix-xts-aes-qce-key-sizes.patch index 4dcf1ac726..4dcf1ac726 100644 --- a/target/linux/ipq40xx/patches-5.4/042-crypto-qce-fix-xts-aes-qce-key-sizes.patch +++ b/target/linux/ipq40xx/patches-5.4/0009-v5.6-crypto-qce-fix-xts-aes-qce-key-sizes.patch diff --git a/target/linux/ipq40xx/patches-5.4/043-crypto-qce-save-a-sg-table-slot-for-result-buf.patch b/target/linux/ipq40xx/patches-5.4/0010-v5.6-crypto-qce-save-a-sg-table-slot-for-result-buf.patch index 2385d483f2..2385d483f2 100644 --- a/target/linux/ipq40xx/patches-5.4/043-crypto-qce-save-a-sg-table-slot-for-result-buf.patch +++ b/target/linux/ipq40xx/patches-5.4/0010-v5.6-crypto-qce-save-a-sg-table-slot-for-result-buf.patch diff --git a/target/linux/ipq40xx/patches-5.4/044-crypto-qce-update-the-skcipher-IV.patch b/target/linux/ipq40xx/patches-5.4/0011-v5.6-crypto-qce-update-the-skcipher-IV.patch index 5efdb72c44..5efdb72c44 100644 --- a/target/linux/ipq40xx/patches-5.4/044-crypto-qce-update-the-skcipher-IV.patch +++ b/target/linux/ipq40xx/patches-5.4/0011-v5.6-crypto-qce-update-the-skcipher-IV.patch diff --git a/target/linux/ipq40xx/patches-5.4/046-crypto-qce-initialize-fallback-only-for-AES.patch b/target/linux/ipq40xx/patches-5.4/0012-v5.6-crypto-qce-initialize-fallback-only-for-AES.patch index 84aef04ef4..84aef04ef4 100644 --- a/target/linux/ipq40xx/patches-5.4/046-crypto-qce-initialize-fallback-only-for-AES.patch +++ b/target/linux/ipq40xx/patches-5.4/0012-v5.6-crypto-qce-initialize-fallback-only-for-AES.patch diff --git a/target/linux/ipq40xx/patches-5.4/051-crypto-qce-allow-building-only-hashes-ciphers.patch b/target/linux/ipq40xx/patches-5.4/0013-v5.6-crypto-qce-allow-building-only-hashes-ciphers.patch index 5f350183d8..bcd5551f54 100644 --- a/target/linux/ipq40xx/patches-5.4/051-crypto-qce-allow-building-only-hashes-ciphers.patch +++ b/target/linux/ipq40xx/patches-5.4/0013-v5.6-crypto-qce-allow-building-only-hashes-ciphers.patch @@ -94,8 +94,8 @@ Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> + +endchoice - config CRYPTO_DEV_QCE_SW_MAX_LEN - int "Default maximum request size to use software for AES" + config CRYPTO_DEV_QCOM_RNG + tristate "Qualcomm Random Number Generator Driver" --- a/drivers/crypto/qce/Makefile +++ b/drivers/crypto/qce/Makefile @@ -2,6 +2,7 @@ @@ -111,7 +111,7 @@ Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> +qcrypto-$(CONFIG_CRYPTO_DEV_QCE_SKCIPHER) += skcipher.o --- a/drivers/crypto/qce/common.c +++ b/drivers/crypto/qce/common.c -@@ -43,52 +43,56 @@ qce_clear_array(struct qce_device *qce, +@@ -45,52 +45,56 @@ qce_clear_array(struct qce_device *qce, qce_write(qce, offset + i * sizeof(u32), 0); } @@ -204,7 +204,7 @@ Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> static u32 qce_auth_cfg(unsigned long flags, u32 key_size) { u32 cfg = 0; -@@ -135,88 +139,6 @@ static u32 qce_auth_cfg(unsigned long fl +@@ -137,88 +141,6 @@ static u32 qce_auth_cfg(unsigned long fl return cfg; } @@ -293,7 +293,7 @@ Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> static int qce_setup_regs_ahash(struct crypto_async_request *async_req, u32 totallen, u32 offset) { -@@ -301,6 +223,87 @@ go_proc: +@@ -303,6 +225,87 @@ go_proc: return 0; } @@ -381,7 +381,7 @@ Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> static int qce_setup_regs_skcipher(struct crypto_async_request *async_req, u32 totallen, u32 offset) -@@ -382,15 +385,20 @@ static int qce_setup_regs_skcipher(struc +@@ -384,15 +387,20 @@ static int qce_setup_regs_skcipher(struc return 0; } diff --git a/target/linux/ipq40xx/patches-5.4/047-crypto-qce-use-cryptlen-when-adding-extra-sgl.patch b/target/linux/ipq40xx/patches-5.4/0014-v5.7-crypto-qce-use-cryptlen-when-adding-extra-sgl.patch index 160420b485..160420b485 100644 --- a/target/linux/ipq40xx/patches-5.4/047-crypto-qce-use-cryptlen-when-adding-extra-sgl.patch +++ b/target/linux/ipq40xx/patches-5.4/0014-v5.7-crypto-qce-use-cryptlen-when-adding-extra-sgl.patch diff --git a/target/linux/ipq40xx/patches-5.4/048-crypto-qce-use-AES-fallback-for-small-requests.patch b/target/linux/ipq40xx/patches-5.4/0015-v5.7-crypto-qce-use-AES-fallback-for-small-requests.patch index d9a6c4dff9..55d15f56b5 100644 --- a/target/linux/ipq40xx/patches-5.4/048-crypto-qce-use-AES-fallback-for-small-requests.patch +++ b/target/linux/ipq40xx/patches-5.4/0015-v5.7-crypto-qce-use-AES-fallback-for-small-requests.patch @@ -28,9 +28,9 @@ Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig -@@ -628,6 +628,29 @@ config CRYPTO_DEV_QCE - hardware. To compile this driver as a module, choose M here. The - module will be called qcrypto. +@@ -683,6 +683,29 @@ choice + + endchoice +config CRYPTO_DEV_QCE_SW_MAX_LEN + int "Default maximum request size to use software for AES" diff --git a/target/linux/ipq40xx/patches-5.4/049-crypto-qce-handle-AES-XTS-cases-that-qce-fails.patch b/target/linux/ipq40xx/patches-5.4/0016-v5.7-crypto-qce-handle-AES-XTS-cases-that-qce-fails.patch index 18beda6296..18beda6296 100644 --- a/target/linux/ipq40xx/patches-5.4/049-crypto-qce-handle-AES-XTS-cases-that-qce-fails.patch +++ b/target/linux/ipq40xx/patches-5.4/0016-v5.7-crypto-qce-handle-AES-XTS-cases-that-qce-fails.patch diff --git a/target/linux/ipq40xx/patches-5.4/076-phy-qcom-ipq4019-usb-add-driver-for-QCOM-IPQ4019.patch b/target/linux/ipq40xx/patches-5.4/0017-v5.8-phy-add-driver-for-Qualcomm-IPQ40xx-USB-PHY.patch index 6ded0e9bad..ad09a9f250 100644 --- a/target/linux/ipq40xx/patches-5.4/076-phy-qcom-ipq4019-usb-add-driver-for-QCOM-IPQ4019.patch +++ b/target/linux/ipq40xx/patches-5.4/0017-v5.8-phy-add-driver-for-Qualcomm-IPQ40xx-USB-PHY.patch @@ -1,18 +1,21 @@ -From 633f0e08498aebfdb932bd71319b4cb136709499 Mon Sep 17 00:00:00 2001 -From: John Crispin <john@phrozen.org> -Date: Tue, 24 Jul 2018 14:45:49 +0200 -Subject: [PATCH 2/3] phy: qcom-ipq4019-usb: add driver for QCOM/IPQ4019 +From 3c9d8f6c03a2cda1849ec3c84f82ec030d1f49ef Mon Sep 17 00:00:00 2001 +From: Robert Marko <robert.marko@sartura.hr> +Date: Sun, 3 May 2020 22:18:22 +0200 +Subject: [PATCH] phy: add driver for Qualcomm IPQ40xx USB PHY -Add a driver to setup the USB phy on Qualcom Dakota SoCs. -The driver sets up HS and SS phys. In case of HS some magic values need to -be written to magic offsets. These were taken from the SDK driver. +Add a driver to setup the USB PHY-s on Qualcom m IPQ40xx series SoCs. +The driver sets up HS and SS phys. Signed-off-by: John Crispin <john@phrozen.org> +Signed-off-by: Robert Marko <robert.marko@sartura.hr> +Cc: Luka Perkov <luka.perkov@sartura.hr> +Link: https://lore.kernel.org/r/20200503201823.531757-1-robert.marko@sartura.hr +Signed-off-by: Vinod Koul <vkoul@kernel.org> --- - drivers/phy/qualcomm/Kconfig | 7 ++ + drivers/phy/qualcomm/Kconfig | 7 + drivers/phy/qualcomm/Makefile | 1 + - drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c | 188 ++++++++++++++++++++++++++++ - 3 files changed, 196 insertions(+) + drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c | 148 ++++++++++++++++++++ + 3 files changed, 156 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c --- a/drivers/phy/qualcomm/Kconfig @@ -22,33 +25,35 @@ Signed-off-by: John Crispin <john@phrozen.org> select GENERIC_PHY +config PHY_QCOM_IPQ4019_USB -+ tristate "Qualcomm IPQ4019 USB PHY module" -+ depends on OF && ARCH_QCOM ++ tristate "Qualcomm IPQ4019 USB PHY driver" ++ depends on OF && (ARCH_QCOM || COMPILE_TEST) + select GENERIC_PHY + help -+ Support for the USB PHY on QCOM IPQ4019/Dakota chipsets. ++ Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s. + config PHY_QCOM_IPQ806X_SATA tristate "Qualcomm IPQ806x SATA SerDes/PHY driver" depends on ARCH_QCOM +--- a/drivers/phy/qualcomm/Makefile ++++ b/drivers/phy/qualcomm/Makefile +@@ -1,6 +1,7 @@ + # SPDX-License-Identifier: GPL-2.0 + obj-$(CONFIG_PHY_ATH79_USB) += phy-ath79-usb.o + obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o ++obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o + obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o + obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o + obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c -@@ -0,0 +1,188 @@ +@@ -0,0 +1,148 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2018 John Crispin <john@phrozen.org> + * + * Based on code from + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. + */ + +#include <linux/delay.h> @@ -58,29 +63,11 @@ Signed-off-by: John Crispin <john@phrozen.org> +#include <linux/module.h> +#include <linux/mutex.h> +#include <linux/of_platform.h> ++#include <linux/of_device.h> +#include <linux/phy/phy.h> +#include <linux/platform_device.h> +#include <linux/reset.h> + -+/* -+ * Magic registers copied from the SDK driver code -+ */ -+#define PHY_CTRL0_ADDR 0x000 -+#define PHY_CTRL1_ADDR 0x004 -+#define PHY_CTRL2_ADDR 0x008 -+#define PHY_CTRL3_ADDR 0x00C -+#define PHY_CTRL4_ADDR 0x010 -+#define PHY_MISC_ADDR 0x024 -+#define PHY_IPG_ADDR 0x030 -+ -+#define PHY_CTRL0_VAL 0xA4600015 -+#define PHY_CTRL1_VAL 0x09500000 -+#define PHY_CTRL2_VAL 0x00058180 -+#define PHY_CTRL3_VAL 0x6DB6DCD6 -+#define PHY_CTRL4_VAL 0x836DB6DB -+#define PHY_MISC_VAL 0x3803FB0C -+#define PHY_IPG_VAL 0x47323232 -+ +struct ipq4019_usb_phy { + struct device *dev; + struct phy *phy; @@ -137,15 +124,6 @@ Signed-off-by: John Crispin <john@phrozen.org> + reset_control_deassert(phy->srif_rst); + msleep(10); + -+ writel(PHY_CTRL0_VAL, phy->base + PHY_CTRL0_ADDR); -+ writel(PHY_CTRL1_VAL, phy->base + PHY_CTRL1_ADDR); -+ writel(PHY_CTRL2_VAL, phy->base + PHY_CTRL2_ADDR); -+ writel(PHY_CTRL3_VAL, phy->base + PHY_CTRL3_ADDR); -+ writel(PHY_CTRL4_VAL, phy->base + PHY_CTRL4_ADDR); -+ writel(PHY_MISC_VAL, phy->base + PHY_MISC_ADDR); -+ writel(PHY_IPG_VAL, phy->base + PHY_IPG_ADDR); -+ msleep(10); -+ + reset_control_deassert(phy->por_rst); + + return 0; @@ -169,11 +147,6 @@ Signed-off-by: John Crispin <john@phrozen.org> + struct resource *res; + struct phy_provider *phy_provider; + struct ipq4019_usb_phy *phy; -+ const struct of_device_id *match; -+ -+ match = of_match_device(ipq4019_usb_phy_of_match, &pdev->dev); -+ if (!match) -+ return -ENODEV; + + phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); + if (!phy) @@ -198,7 +171,7 @@ Signed-off-by: John Crispin <john@phrozen.org> + if (IS_ERR(phy->srif_rst)) + return PTR_ERR(phy->srif_rst); + -+ phy->phy = devm_phy_create(dev, NULL, match->data); ++ phy->phy = devm_phy_create(dev, NULL, of_device_get_match_data(dev)); + if (IS_ERR(phy->phy)) { + dev_err(dev, "failed to create PHY\n"); + return PTR_ERR(phy->phy); @@ -222,13 +195,3 @@ Signed-off-by: John Crispin <john@phrozen.org> +MODULE_DESCRIPTION("QCOM/IPQ4019 USB phy driver"); +MODULE_AUTHOR("John Crispin <john@phrozen.org>"); +MODULE_LICENSE("GPL v2"); ---- a/drivers/phy/qualcomm/Makefile -+++ b/drivers/phy/qualcomm/Makefile -@@ -1,6 +1,7 @@ - # SPDX-License-Identifier: GPL-2.0 - obj-$(CONFIG_PHY_ATH79_USB) += phy-ath79-usb.o - obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o -+obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o - obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o - obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o - obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o diff --git a/target/linux/ipq40xx/patches-5.4/090-pinctrl-msm-open-drain.patch b/target/linux/ipq40xx/patches-5.4/0018-v5.9-pinctrl-msm-open-drain.patch index 5cd4ccc30f..5cd4ccc30f 100644 --- a/target/linux/ipq40xx/patches-5.4/090-pinctrl-msm-open-drain.patch +++ b/target/linux/ipq40xx/patches-5.4/0018-v5.9-pinctrl-msm-open-drain.patch diff --git a/target/linux/ipq40xx/patches-5.4/304-mtd-spi-nor-Add-support-for-mx25r3235f.patch b/target/linux/ipq40xx/patches-5.4/0019-v5.6-mtd-spi-nor-Add-support-for-mx25r3235f.patch index e0078b7260..97433b030e 100644 --- a/target/linux/ipq40xx/patches-5.4/304-mtd-spi-nor-Add-support-for-mx25r3235f.patch +++ b/target/linux/ipq40xx/patches-5.4/0019-v5.6-mtd-spi-nor-Add-support-for-mx25r3235f.patch @@ -1,6 +1,6 @@ -From 158acdbf0336f601971637f988b57a6a67a0869b Mon Sep 17 00:00:00 2001 +From 707745e8d4e75b638b990d67950ab292b3b8ea2a Mon Sep 17 00:00:00 2001 From: David Bauer <mail@david-bauer.net> -Date: Sun, 15 Dec 2019 13:10:50 +0100 +Date: Mon, 16 Dec 2019 01:36:46 +0100 Subject: [PATCH] mtd: spi-nor: Add support for mx25r3235f Add MTD support for the Macronix MX25R3235F SPI NOR chip from Macronix. @@ -8,7 +8,10 @@ The chip has 4MB of total capacity, divided into a total of 64 sectors, each 64KB sized. The chip also supports 4KB large sectors. Additionally, it supports dual and quad read modes. +Functionality was verified on an HPE/Aruba AP-303 board. + Signed-off-by: David Bauer <mail@david-bauer.net> +Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> --- drivers/mtd/spi-nor/spi-nor.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/linux/ipq40xx/patches-5.4/071-02-ipq40xx-Fix-booting-secondary-cores.patch b/target/linux/ipq40xx/patches-5.4/071-02-ipq40xx-Fix-booting-secondary-cores.patch deleted file mode 100644 index 631a1307dd..0000000000 --- a/target/linux/ipq40xx/patches-5.4/071-02-ipq40xx-Fix-booting-secondary-cores.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 8a4540321e8bcf7a5b485c332a2e78f3501c78ed Mon Sep 17 00:00:00 2001 -From: Robert Marko <robimarko@gmail.com> -Date: Thu, 29 Nov 2018 22:29:36 +0100 -Subject: [PATCH] ipq40xx: Fix booting secondary cores - -Add the second part of old 071-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch -We dont modify the patch itself as its upstream and this change is not. - -Originally added by Mantas Pucka Mantas Pucka <mantas@8devices.com> - -Signed-off-by: Robert Marko <robimarko@gmail.com> ---- - arch/arm/boot/dts/qcom-ipq4019.dtsi | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi -@@ -102,6 +102,7 @@ - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; -+ qcom,saw = <&saw_l2>; - }; - }; - -@@ -341,6 +342,12 @@ - regulator; - }; - -+ saw_l2: regulator@b012000 { -+ compatible = "qcom,saw2"; -+ reg = <0xb012000 0x1000>; -+ regulator; -+ }; -+ - blsp1_uart1: serial@78af000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x78af000 0x200>; diff --git a/target/linux/ipq40xx/patches-5.4/074-ARM-qcom-Add-IPQ4019-SoC-support.patch b/target/linux/ipq40xx/patches-5.4/074-ARM-qcom-Add-IPQ4019-SoC-support.patch deleted file mode 100644 index 16ac94fd37..0000000000 --- a/target/linux/ipq40xx/patches-5.4/074-ARM-qcom-Add-IPQ4019-SoC-support.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 89b43d59ec8c9cda588555eb1f2754dd19ef5144 Mon Sep 17 00:00:00 2001 -From: Christian Lamparter <chunkeey@gmail.com> -Date: Sun, 22 Jul 2018 12:07:57 +0200 -Subject: [PATCH 8/8] ARM: qcom: Add IPQ4019 SoC support - -Add support for the Qualcomm Atheros IPQ4019 SoC. - -Signed-off-by: Christian Lamparter <chunkeey@gmail.com> -Signed-off-by: John Crispin <john@phrozen.org> ---- - arch/arm/Makefile | 1 + - arch/arm/mach-qcom/Kconfig | 5 +++++ - 2 files changed, 6 insertions(+) - ---- a/arch/arm/Makefile -+++ b/arch/arm/Makefile -@@ -156,6 +156,7 @@ textofs-$(CONFIG_ARCH_MSM8X60) := 0x0020 - textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000 - textofs-$(CONFIG_ARCH_MESON) := 0x00208000 - textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000 -+textofs-$(CONFIG_ARCH_IPQ40XX) := 0x00208000 - - # Machine directory name. This list is sorted alphanumerically - # by CONFIG_* macro name. ---- a/arch/arm/mach-qcom/Kconfig -+++ b/arch/arm/mach-qcom/Kconfig -@@ -28,4 +28,9 @@ config ARCH_MDM9615 - bool "Enable support for MDM9615" - select CLKSRC_QCOM - -+config ARCH_IPQ40XX -+ bool "Enable support for IPQ40XX" -+ select CLKSRC_QCOM -+ select HAVE_ARM_ARCH_TIMER -+ - endif diff --git a/target/linux/ipq40xx/patches-5.4/075-dt-bindings-phy-qcom-ipq4019-usb-add-binding-documen.patch b/target/linux/ipq40xx/patches-5.4/075-dt-bindings-phy-qcom-ipq4019-usb-add-binding-documen.patch deleted file mode 100644 index e7407bcbab..0000000000 --- a/target/linux/ipq40xx/patches-5.4/075-dt-bindings-phy-qcom-ipq4019-usb-add-binding-documen.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 5f01733dc755dfadfa51b7b3c6c160e632fc6002 Mon Sep 17 00:00:00 2001 -From: John Crispin <john@phrozen.org> -Date: Tue, 24 Jul 2018 15:09:36 +0200 -Subject: [PATCH 1/3] dt-bindings: phy-qcom-ipq4019-usb: add binding document - -This patch adds the binding documentation for the HS/SS USB PHY found -inside Qualcom Dakota SoCs. - -Signed-off-by: John Crispin <john@phrozen.org> ---- - .../bindings/phy/phy-qcom-ipq4019-usb.txt | 21 +++++++++++++++++++++ - 1 file changed, 21 insertions(+) - create mode 100644 Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt - ---- /dev/null -+++ b/Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt -@@ -0,0 +1,21 @@ -+Qualcom Dakota HS/SS USB PHY -+ -+Required properties: -+ - compatible: "qcom,usb-ss-ipq4019-phy", -+ "qcom,usb-hs-ipq4019-phy" -+ - reg: offset and length of the registers -+ - #phy-cells: should be 0 -+ - resets: the reset controllers as listed below -+ - reset-names: the names of the reset controllers -+ "por_rst" - the POR reset line for SS and HS phys -+ "srif_rst" - the SRIF reset line for HS phys -+Example: -+ -+hsphy@a8000 { -+ compatible = "qcom,usb-hs-ipq4019-phy"; -+ phy-cells = <0>; -+ reg = <0xa8000 0x40>; -+ resets = <&gcc USB2_HSPHY_POR_ARES>, -+ <&gcc USB2_HSPHY_S_ARES>; -+ reset-names = "por_rst", "srif_rst"; -+}; diff --git a/target/linux/ipq40xx/patches-5.4/080-ARM-dts-qcom-add-gpio-ranges-property.patch b/target/linux/ipq40xx/patches-5.4/080-ARM-dts-qcom-add-gpio-ranges-property.patch deleted file mode 100644 index 972bdb7497..0000000000 --- a/target/linux/ipq40xx/patches-5.4/080-ARM-dts-qcom-add-gpio-ranges-property.patch +++ /dev/null @@ -1,70 +0,0 @@ -From patchwork Mon May 21 20:57:38 2018 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [v5,3/4] ARM: dts: qcom: add gpio-ranges property -X-Patchwork-Submitter: Christian Lamparter <chunkeey@gmail.com> -X-Patchwork-Id: 917856 -Message-Id: <0ae3376606a89bcdf3fe753a5c967f7103699e09.1526935804.git.chunkeey@gmail.com> -To: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, - linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org -Cc: Bjorn Andersson <bjorn.andersson@linaro.org>, - Linus Walleij <linus.walleij@linaro.org>, - Stephen Boyd <sboyd@kernel.org>, David Brown <david.brown@linaro.org>, - Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, - Andy Gross <andy.gross@linaro.org>, - Sven Eckelmann <sven.eckelmann@openmesh.com> -Date: Mon, 21 May 2018 22:57:38 +0200 -From: Christian Lamparter <chunkeey@gmail.com> -List-Id: <linux-gpio.vger.kernel.org> - -This patch adds the gpio-ranges property to almost all of -the Qualcomm ARM platforms that utilize the pinctrl-msm -framework. - -The gpio-ranges property is part of the gpiolib subsystem. -As a result, the binding text is available in section -"2.1 gpio- and pin-controller interaction" of -Documentation/devicetree/bindings/gpio/gpio.txt - -For more information please see the patch titled: -"pinctrl: msm: fix gpio-hog related boot issues" from -this series. - -Reported-by: Sven Eckelmann <sven.eckelmann@openmesh.com> -Tested-by: Sven Eckelmann <sven.eckelmann@openmesh.com> [ipq4019] -Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> -Signed-off-by: Christian Lamparter <chunkeey@gmail.com> -Reviewed-by: Linus Walleij <linus.walleij@linaro.org> ---- -To help with git bisect, the DT update patch has been intentionally -placed after the "pinctrl: msm: fix gpio-hog related boot issues". -Otherwise - if the order was reveresed - and bisect decides to split -between these two patches, the gpiochip_add_pin_ranges() function -will be executed twice with the same parameters for the same pinctrl. ---- - arch/arm/boot/dts/qcom-apq8064.dtsi | 1 + - arch/arm/boot/dts/qcom-apq8084.dtsi | 1 + - arch/arm/boot/dts/qcom-ipq4019.dtsi | 1 + - arch/arm/boot/dts/qcom-ipq8064.dtsi | 1 + - arch/arm/boot/dts/qcom-mdm9615.dtsi | 1 + - arch/arm/boot/dts/qcom-msm8660.dtsi | 1 + - arch/arm/boot/dts/qcom-msm8960.dtsi | 1 + - arch/arm/boot/dts/qcom-msm8974.dtsi | 1 + - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 3 ++- - arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 + - arch/arm64/boot/dts/qcom/msm8992.dtsi | 1 + - arch/arm64/boot/dts/qcom/msm8994.dtsi | 1 + - arch/arm64/boot/dts/qcom/msm8996.dtsi | 1 + - 13 files changed, 14 insertions(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi -@@ -201,6 +201,7 @@ - compatible = "qcom,ipq4019-pinctrl"; - reg = <0x01000000 0x300000>; - gpio-controller; -+ gpio-ranges = <&tlmm 0 0 100>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; diff --git a/target/linux/ipq40xx/patches-5.4/100-arm-dts-IPQ4019-add-SDHCI-VQMMC-LDO-node.patch b/target/linux/ipq40xx/patches-5.4/101-arm-dts-IPQ4019-add-SDHCI-VQMMC-LDO-node.patch index 14affc28c1..14affc28c1 100644 --- a/target/linux/ipq40xx/patches-5.4/100-arm-dts-IPQ4019-add-SDHCI-VQMMC-LDO-node.patch +++ b/target/linux/ipq40xx/patches-5.4/101-arm-dts-IPQ4019-add-SDHCI-VQMMC-LDO-node.patch diff --git a/target/linux/ipq40xx/patches-5.4/077-qcom-ipq4019-add-USB-devicetree-nodes.patch b/target/linux/ipq40xx/patches-5.4/102-ARM-dts-qcom-ipq4019-add-USB-devicetree-nodes.patch index 5efc08bcca..b033a1baee 100644 --- a/target/linux/ipq40xx/patches-5.4/077-qcom-ipq4019-add-USB-devicetree-nodes.patch +++ b/target/linux/ipq40xx/patches-5.4/102-ARM-dts-qcom-ipq4019-add-USB-devicetree-nodes.patch @@ -1,49 +1,23 @@ -From 1fc7d5523e21ed140fed43c4dde011a3b6d9ba08 Mon Sep 17 00:00:00 2001 +From 193856b5fe11c50a0b6ff22457dd674c1a45fec6 Mon Sep 17 00:00:00 2001 From: John Crispin <john@phrozen.org> -Date: Tue, 24 Jul 2018 14:47:55 +0200 -Subject: [PATCH 3/3] qcom: ipq4019: add USB devicetree nodes +Date: Wed, 9 Sep 2020 18:31:03 +0200 +Subject: [PATCH] ARM: dts: qcom: ipq4019: add USB devicetree nodes -This patch makes USB work on the Dakota EVB. +Since we now have driver for the USB PHY, and USB controller is already supported by the DWC3 driver lets add the necessary nodes to DTSI. Signed-off-by: John Crispin <john@phrozen.org> +Signed-off-by: Robert Marko <robert.marko@sartura.hr> +Cc: Luka Perkov <luka.perkov@sartura.hr> +Reviewed-by: Vinod Koul <vkoul@kernel.org> --- - arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 ++++++++ - arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++++++++++ - 2 files changed, 94 insertions(+) + arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++++++++++++ + 1 file changed, 74 insertions(+) ---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi -@@ -109,5 +109,25 @@ - wifi@a800000 { - status = "ok"; - }; -+ -+ usb3_ss_phy: ssphy@9a000 { -+ status = "okay"; -+ }; -+ -+ usb3_hs_phy: hsphy@a6000 { -+ status = "okay"; -+ }; -+ -+ usb3: usb3@8af8800 { -+ status = "okay"; -+ }; -+ -+ usb2_hs_phy: hsphy@a8000 { -+ status = "okay"; -+ }; -+ -+ usb2: usb2@60f8800 { -+ status = "okay"; -+ }; - }; - }; --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi -@@ -563,5 +563,79 @@ - "legacy"; - status = "disabled"; +@@ -615,5 +615,79 @@ + reg = <4>; + }; }; + + usb3_ss_phy: ssphy@9a000 { @@ -66,7 +40,7 @@ Signed-off-by: John Crispin <john@phrozen.org> + status = "disabled"; + }; + -+ usb3@8af8800 { ++ usb3: usb3@8af8800 { + compatible = "qcom,dwc3"; + reg = <0x8af8800 0x100>; + #address-cells = <1>; @@ -98,7 +72,7 @@ Signed-off-by: John Crispin <john@phrozen.org> + status = "disabled"; + }; + -+ usb2@60f8800 { ++ usb2: usb2@60f8800 { + compatible = "qcom,dwc3"; + reg = <0x60f8800 0x100>; + #address-cells = <1>; diff --git a/target/linux/ipq40xx/patches-5.4/103-arm-dts-qcom-ipq4019-add-more-labels.patch b/target/linux/ipq40xx/patches-5.4/103-arm-dts-qcom-ipq4019-add-more-labels.patch new file mode 100644 index 0000000000..0e215ee7cf --- /dev/null +++ b/target/linux/ipq40xx/patches-5.4/103-arm-dts-qcom-ipq4019-add-more-labels.patch @@ -0,0 +1,42 @@ +From caa3ee6b094ee18021943504c938919fcac325ec Mon Sep 17 00:00:00 2001 +From: Robert Marko <robert.marko@sartura.hr> +Date: Wed, 9 Sep 2020 20:40:33 +0200 +Subject: [PATCH] arm: dts: qcom: ipq4019: add more labels + +Lets add labels to more commonly used nodes for easier modification in board DTS files. + +Signed-off-by: Robert Marko <robert.marko@sartura.hr> +Cc: Luka Perkov <luka.perkov@sartura.hr> +--- + arch/arm/boot/dts/qcom-ipq4019.dtsi | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi +@@ -190,7 +190,7 @@ + reg = <0x1800000 0x60000>; + }; + +- rng@22000 { ++ prng: rng@22000 { + compatible = "qcom,prng"; + reg = <0x22000 0x140>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; +@@ -310,7 +310,7 @@ + status = "disabled"; + }; + +- crypto@8e3a000 { ++ crypto: crypto@8e3a000 { + compatible = "qcom,crypto-v5.1"; + reg = <0x08e3a000 0x6000>; + clocks = <&gcc GCC_CRYPTO_AHB_CLK>, +@@ -396,7 +396,7 @@ + dma-names = "rx", "tx"; + }; + +- watchdog@b017000 { ++ watchdog: watchdog@b017000 { + compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019"; + reg = <0xb017000 0x40>; + clocks = <&sleep_clk>; diff --git a/target/linux/ipq40xx/patches-5.4/081-clk-fix-apss-cpu-overclocking.patch b/target/linux/ipq40xx/patches-5.4/104-clk-fix-apss-cpu-overclocking.patch index 25a2020bd2..25a2020bd2 100644 --- a/target/linux/ipq40xx/patches-5.4/081-clk-fix-apss-cpu-overclocking.patch +++ b/target/linux/ipq40xx/patches-5.4/104-clk-fix-apss-cpu-overclocking.patch diff --git a/target/linux/ipq40xx/patches-5.4/701-dts-ipq4019-add-mdio-node.patch b/target/linux/ipq40xx/patches-5.4/701-dts-ipq4019-add-mdio-node.patch deleted file mode 100644 index b0a69433b1..0000000000 --- a/target/linux/ipq40xx/patches-5.4/701-dts-ipq4019-add-mdio-node.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 09ed737593f71bcca08a537a6c15264a1a6add08 Mon Sep 17 00:00:00 2001 -From: Christian Lamparter <chunkeey@gmail.com> -Date: Sun, 20 Nov 2016 01:10:33 +0100 -Subject: [PATCH] dts: ipq4019: add mdio node for ethernet - -This patch adds the mdio device-tree node. -This is where the switch is connected to, so it's needed -for the ethernet interfaces. - -Note: The driver isn't anywhere close to be upstream, -so the info might change. ---- - arch/arm/boot/dts/qcom-ipq4019.dtsi | 28 ++++++++++++++++++++++++++++ - 1 file changed, 28 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi -@@ -588,6 +588,34 @@ - status = "disabled"; - }; - -+ mdio: mdio@90000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "qcom,ipq4019-mdio"; -+ reg = <0x90000 0x64>; -+ status = "disabled"; -+ -+ ethphy0: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ -+ ethphy1: ethernet-phy@1 { -+ reg = <1>; -+ }; -+ -+ ethphy2: ethernet-phy@2 { -+ reg = <2>; -+ }; -+ -+ ethphy3: ethernet-phy@3 { -+ reg = <3>; -+ }; -+ -+ ethphy4: ethernet-phy@4 { -+ reg = <4>; -+ }; -+ }; -+ - usb3_ss_phy: ssphy@9a000 { - compatible = "qcom,usb-ss-ipq4019-phy"; - #phy-cells = <0>; diff --git a/target/linux/ipq40xx/patches-5.4/705-net-add-qualcomm-ar40xx-phy.patch b/target/linux/ipq40xx/patches-5.4/705-net-add-qualcomm-ar40xx-phy.patch index a90ae0eb89..4cdeab637a 100644 --- a/target/linux/ipq40xx/patches-5.4/705-net-add-qualcomm-ar40xx-phy.patch +++ b/target/linux/ipq40xx/patches-5.4/705-net-add-qualcomm-ar40xx-phy.patch @@ -8,7 +8,7 @@ + tristate "Driver for Qualcomm Atheros IPQ40XX switches" + depends on HAS_IOMEM && OF + select SWCONFIG -+ ---help--- ++ help + This is the driver for Qualcomm Atheros IPQ40XX ESS switches. + endif # PHYLIB diff --git a/target/linux/ipq40xx/patches-5.4/721-dts-ipq4019-add-ethernet-essedma-node.patch b/target/linux/ipq40xx/patches-5.4/721-dts-ipq4019-add-ethernet-essedma-node.patch deleted file mode 100644 index 6424dd5243..0000000000 --- a/target/linux/ipq40xx/patches-5.4/721-dts-ipq4019-add-ethernet-essedma-node.patch +++ /dev/null @@ -1,69 +0,0 @@ -From c611d3780fa101662a822d10acf8feb04ca97409 Mon Sep 17 00:00:00 2001 -From: Christian Lamparter <chunkeey@gmail.com> -Date: Sun, 20 Nov 2016 01:01:10 +0100 -Subject: [PATCH] dts: ipq4019: add ethernet ipqess node - -This patch adds the device-tree node for the ipqess ethernet -interfaces. - -Signed-off-by: Christian Lamparter <chunkeey@gmail.com> ---- - arch/arm/boot/dts/qcom-ipq4019.dtsi | 60 +++++++++++++++++++++++++++++++++++++ - 1 file changed, 60 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi -@@ -699,6 +699,53 @@ - }; - }; - -+ gmac: ethernet@c080000 { -+ compatible = "qcom,ipq4019-ess-edma"; -+ reg = <0xc080000 0x8000>; -+ interrupts = <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 243 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 254 IRQ_TYPE_EDGE_RISING>, -+ <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>; -+ -+ status = "disabled"; -+ -+ phy-mode = "internal"; -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ pause; -+ asym-pause; -+ }; -+ }; -+ - usb3_ss_phy: ssphy@9a000 { - compatible = "qcom,usb-ss-ipq4019-phy"; - #phy-cells = <0>; diff --git a/target/linux/ipq40xx/patches-5.4/900-dts-ipq4019-ap-dk01.1.patch b/target/linux/ipq40xx/patches-5.4/900-dts-ipq4019-ap-dk01.1.patch index 5157079762..5a245eb431 100644 --- a/target/linux/ipq40xx/patches-5.4/900-dts-ipq4019-ap-dk01.1.patch +++ b/target/linux/ipq40xx/patches-5.4/900-dts-ipq4019-ap-dk01.1.patch @@ -56,10 +56,11 @@ }; serial@78af000 { -@@ -110,6 +129,22 @@ +@@ -109,5 +128,41 @@ + wifi@a800000 { status = "ok"; }; - ++ + mdio@90000 { + status = "okay"; + }; @@ -76,9 +77,27 @@ + status = "okay"; + }; + - usb3_ss_phy: ssphy@9a000 { - status = "okay"; - }; ++ usb3_ss_phy: ssphy@9a000 { ++ status = "okay"; ++ }; ++ ++ usb3_hs_phy: hsphy@a6000 { ++ status = "okay"; ++ }; ++ ++ usb3: usb3@8af8800 { ++ status = "okay"; ++ }; ++ ++ usb2_hs_phy: hsphy@a8000 { ++ status = "okay"; ++ }; ++ ++ usb2: usb2@60f8800 { ++ status = "okay"; ++ }; + }; + }; --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts @@ -18,5 +18,73 @@ |