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-rw-r--r--target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_gmac.c8
-rw-r--r--target/linux/ath79/patches-4.14/0009-MIPS-ath79-add-lots-of-missing-registers.patch6
2 files changed, 13 insertions, 1 deletions
diff --git a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_gmac.c b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_gmac.c
index 2e5fb3a641..e69abb6438 100644
--- a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_gmac.c
+++ b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_gmac.c
@@ -57,6 +57,14 @@ static void ag71xx_setup_gmac_934x(struct device_node *np, void __iomem *base)
ag71xx_of_bit(np, "switch-phy-swap", &val, AR934X_ETH_CFG_SW_PHY_SWAP);
ag71xx_of_bit(np, "switch-only-mode", &val,
AR934X_ETH_CFG_SW_ONLY_MODE);
+ ag71xx_of_set(np, "rxdv-delay", &val,
+ AR934X_ETH_CFG_RDV_DELAY_SHIFT, 0x3);
+ ag71xx_of_set(np, "rxd-delay", &val,
+ AR934X_ETH_CFG_RXD_DELAY_SHIFT, 0x3);
+ ag71xx_of_set(np, "txd-delay", &val,
+ AR934X_ETH_CFG_TXD_DELAY_SHIFT, 0x3);
+ ag71xx_of_set(np, "txen-delay", &val,
+ AR934X_ETH_CFG_TXE_DELAY_SHIFT, 0x3);
__raw_writel(val, base + AR934X_GMAC_REG_ETH_CFG);
}
diff --git a/target/linux/ath79/patches-4.14/0009-MIPS-ath79-add-lots-of-missing-registers.patch b/target/linux/ath79/patches-4.14/0009-MIPS-ath79-add-lots-of-missing-registers.patch
index d1755394fa..ce6124f6e7 100644
--- a/target/linux/ath79/patches-4.14/0009-MIPS-ath79-add-lots-of-missing-registers.patch
+++ b/target/linux/ath79/patches-4.14/0009-MIPS-ath79-add-lots-of-missing-registers.patch
@@ -650,7 +650,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
/*
* SRIF block
-@@ -552,4 +1007,318 @@
+@@ -552,4 +1007,322 @@
#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
@@ -876,6 +876,10 @@ Signed-off-by: John Crispin <john@phrozen.org>
+#define AR934X_ETH_CFG_RDV_DELAY BIT(16)
+#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3
+#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
++#define AR934X_ETH_CFG_TXD_DELAY_MASK 0x3
++#define AR934X_ETH_CFG_TXD_DELAY_SHIFT 18
++#define AR934X_ETH_CFG_TXE_DELAY_MASK 0x3
++#define AR934X_ETH_CFG_TXE_DELAY_SHIFT 20
+
+/*
+ * QCA953X GMAC Interface