diff options
10 files changed, 1161 insertions, 0 deletions
diff --git a/target/linux/bcm4908/patches-5.10/037-v5.20-0001-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM63158.patch b/target/linux/bcm4908/patches-5.10/037-v5.20-0001-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM63158.patch new file mode 100644 index 0000000000..2a1260f73b --- /dev/null +++ b/target/linux/bcm4908/patches-5.10/037-v5.20-0001-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM63158.patch @@ -0,0 +1,199 @@ +From 076dcedc6628c6bf92bd17bfcf8fb7b1af62bfb6 Mon Sep 17 00:00:00 2001 +From: William Zhang <william.zhang@broadcom.com> +Date: Wed, 1 Jun 2022 15:56:51 -0700 +Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM63158 + +Add DTS for ARMv8 based broadband SoC BCM63158. bcm63158.dtsi is the +SoC description DTS header and bcm963158.dts is a simple DTS file for +Broadcom BCM963158 Reference board that only enable the UART port. + +Signed-off-by: William Zhang <william.zhang@broadcom.com> +Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> +--- + arch/arm64/boot/dts/broadcom/Makefile | 1 + + arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 2 + + .../boot/dts/broadcom/bcmbca/bcm63158.dtsi | 128 ++++++++++++++++++ + .../boot/dts/broadcom/bcmbca/bcm963158.dts | 30 ++++ + 4 files changed, 161 insertions(+) + create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/Makefile + create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi + create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts + +--- a/arch/arm64/boot/dts/broadcom/Makefile ++++ b/arch/arm64/boot/dts/broadcom/Makefile +@@ -6,5 +6,6 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rp + bcm2837-rpi-cm3-io3.dtb + + subdir-y += bcm4908 ++subdir-y += bcmbca + subdir-y += northstar2 + subdir-y += stingray +--- /dev/null ++++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile +@@ -0,0 +1,2 @@ ++# SPDX-License-Identifier: GPL-2.0 ++dtb-$(CONFIG_ARCH_BCMBCA) += bcm963158.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi +@@ -0,0 +1,128 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright 2022 Broadcom Ltd. ++ */ ++ ++#include <dt-bindings/interrupt-controller/irq.h> ++#include <dt-bindings/interrupt-controller/arm-gic.h> ++ ++/ { ++ compatible = "brcm,bcm63158", "brcm,bcmbca"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ interrupt-parent = <&gic>; ++ ++ cpus { ++ #address-cells = <2>; ++ #size-cells = <0>; ++ ++ B53_0: cpu@0 { ++ compatible = "brcm,brahma-b53"; ++ device_type = "cpu"; ++ reg = <0x0 0x0>; ++ next-level-cache = <&L2_0>; ++ enable-method = "psci"; ++ }; ++ ++ B53_1: cpu@1 { ++ compatible = "brcm,brahma-b53"; ++ device_type = "cpu"; ++ reg = <0x0 0x1>; ++ next-level-cache = <&L2_0>; ++ enable-method = "psci"; ++ }; ++ ++ B53_2: cpu@2 { ++ compatible = "brcm,brahma-b53"; ++ device_type = "cpu"; ++ reg = <0x0 0x2>; ++ next-level-cache = <&L2_0>; ++ enable-method = "psci"; ++ }; ++ ++ B53_3: cpu@3 { ++ compatible = "brcm,brahma-b53"; ++ device_type = "cpu"; ++ reg = <0x0 0x3>; ++ next-level-cache = <&L2_0>; ++ enable-method = "psci"; ++ }; ++ ++ L2_0: l2-cache0 { ++ compatible = "cache"; ++ }; ++ }; ++ ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, ++ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, ++ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, ++ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; ++ }; ++ ++ pmu: pmu { ++ compatible = "arm,cortex-a53-pmu"; ++ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-affinity = <&B53_0>, <&B53_1>, ++ <&B53_2>, <&B53_3>; ++ }; ++ ++ clocks: clocks { ++ periph_clk: periph-clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <200000000>; ++ }; ++ uart_clk: uart-clk { ++ compatible = "fixed-factor-clock"; ++ #clock-cells = <0>; ++ clocks = <&periph_clk>; ++ clock-div = <4>; ++ clock-mult = <1>; ++ }; ++ }; ++ ++ psci { ++ compatible = "arm,psci-0.2"; ++ method = "smc"; ++ }; ++ ++ axi@81000000 { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0x0 0x81000000 0x8000>; ++ ++ gic: interrupt-controller@1000 { ++ compatible = "arm,gic-400"; ++ #interrupt-cells = <3>; ++ interrupt-controller; ++ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; ++ reg = <0x1000 0x1000>, ++ <0x2000 0x2000>, ++ <0x4000 0x2000>, ++ <0x6000 0x2000>; ++ }; ++ }; ++ ++ bus@ff800000 { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0x0 0xff800000 0x800000>; ++ ++ uart0: serial@12000 { ++ compatible = "arm,pl011", "arm,primecell"; ++ reg = <0x12000 0x1000>; ++ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&uart_clk>, <&uart_clk>; ++ clock-names = "uartclk", "apb_pclk"; ++ status = "disabled"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts +@@ -0,0 +1,30 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright 2022 Broadcom Ltd. ++ */ ++ ++/dts-v1/; ++ ++#include "bcm63158.dtsi" ++ ++/ { ++ model = "Broadcom BCM963158 Reference Board"; ++ compatible = "brcm,bcm963158", "brcm,bcm63158", "brcm,bcmbca"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x0 0x0 0x08000000>; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; diff --git a/target/linux/bcm4908/patches-5.10/037-v5.20-0002-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM4912.patch b/target/linux/bcm4908/patches-5.10/037-v5.20-0002-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM4912.patch new file mode 100644 index 0000000000..5cdb9d1df1 --- /dev/null +++ b/target/linux/bcm4908/patches-5.10/037-v5.20-0002-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM4912.patch @@ -0,0 +1,191 @@ +From 1ba56aeb391401c4cb2126c39f90b3cdbfabdb3f Mon Sep 17 00:00:00 2001 +From: William Zhang <william.zhang@broadcom.com> +Date: Wed, 1 Jun 2022 13:17:34 -0700 +Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM4912 + +Add DTS for ARMv8 based broadband SoC BCM4912. bcm4912.dtsi is the +SoC description DTS header and bcm94912.dts is a simple DTS file for +Broadcom BCM94912 Reference board that only enable the UART port. + +Signed-off-by: William Zhang <william.zhang@broadcom.com> +Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> +Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> +--- + arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +- + .../boot/dts/broadcom/bcmbca/bcm4912.dtsi | 128 ++++++++++++++++++ + .../boot/dts/broadcom/bcmbca/bcm94912.dts | 30 ++++ + 3 files changed, 160 insertions(+), 1 deletion(-) + create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi + create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts + +--- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile ++++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile +@@ -1,2 +1,3 @@ + # SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_BCMBCA) += bcm963158.dtb ++dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \ ++ bcm963158.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi +@@ -0,0 +1,128 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright 2022 Broadcom Ltd. ++ */ ++ ++#include <dt-bindings/interrupt-controller/irq.h> ++#include <dt-bindings/interrupt-controller/arm-gic.h> ++ ++/ { ++ compatible = "brcm,bcm4912", "brcm,bcmbca"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ interrupt-parent = <&gic>; ++ ++ cpus { ++ #address-cells = <2>; ++ #size-cells = <0>; ++ ++ B53_0: cpu@0 { ++ compatible = "brcm,brahma-b53"; ++ device_type = "cpu"; ++ reg = <0x0 0x0>; ++ next-level-cache = <&L2_0>; ++ enable-method = "psci"; ++ }; ++ ++ B53_1: cpu@1 { ++ compatible = "brcm,brahma-b53"; ++ device_type = "cpu"; ++ reg = <0x0 0x1>; ++ next-level-cache = <&L2_0>; ++ enable-method = "psci"; ++ }; ++ ++ B53_2: cpu@2 { ++ compatible = "brcm,brahma-b53"; ++ device_type = "cpu"; ++ reg = <0x0 0x2>; ++ next-level-cache = <&L2_0>; ++ enable-method = "psci"; ++ }; ++ ++ B53_3: cpu@3 { ++ compatible = "brcm,brahma-b53"; ++ device_type = "cpu"; ++ reg = <0x0 0x3>; ++ next-level-cache = <&L2_0>; ++ enable-method = "psci"; ++ }; ++ ++ L2_0: l2-cache0 { ++ compatible = "cache"; ++ }; ++ }; ++ ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, ++ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, ++ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, ++ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; ++ }; ++ ++ pmu: pmu { ++ compatible = "arm,cortex-a53-pmu"; ++ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-affinity = <&B53_0>, <&B53_1>, ++ <&B53_2>, <&B53_3>; ++ }; ++ ++ clocks: clocks { ++ periph_clk: periph-clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <200000000>; ++ }; ++ uart_clk: uart-clk { ++ compatible = "fixed-factor-clock"; ++ #clock-cells = <0>; ++ clocks = <&periph_clk>; ++ clock-div = <4>; ++ clock-mult = <1>; ++ }; ++ }; ++ ++ psci { ++ compatible = "arm,psci-0.2"; ++ method = "smc"; ++ }; ++ ++ axi@81000000 { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0x0 0x81000000 0x8000>; ++ ++ gic: interrupt-controller@1000 { ++ compatible = "arm,gic-400"; ++ #interrupt-cells = <3>; ++ interrupt-controller; ++ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; ++ reg = <0x1000 0x1000>, ++ <0x2000 0x2000>, ++ <0x4000 0x2000>, ++ <0x6000 0x2000>; ++ }; ++ }; ++ ++ bus@ff800000 { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0x0 0xff800000 0x800000>; ++ ++ uart0: serial@12000 { ++ compatible = "arm,pl011", "arm,primecell"; ++ reg = <0x12000 0x1000>; ++ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&uart_clk>, <&uart_clk>; ++ clock-names = "uartclk", "apb_pclk"; ++ status = "disabled"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts +@@ -0,0 +1,30 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright 2022 Broadcom Ltd. ++ */ ++ ++/dts-v1/; ++ ++#include "bcm4912.dtsi" ++ ++/ { ++ model = "Broadcom BCM94912 Reference Board"; ++ compatible = "brcm,bcm94912", "brcm,bcm4912", "brcm,bcmbca"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x0 0x0 0x08000000>; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; diff --git a/target/linux/bcm4908/patches-5.10/037-v5.20-0003-ARM64-dts-Add-DTS-files-for-bcmbca-SoC-BCM6858.patch b/target/linux/bcm4908/patches-5.10/037-v5.20-0003-ARM64-dts-Add-DTS-files-for-bcmbca-SoC-BCM6858.patch new file mode 100644 index 0000000000..f10a44f890 --- /dev/null +++ b/target/linux/bcm4908/patches-5.10/037-v5.20-0003-ARM64-dts-Add-DTS-files-for-bcmbca-SoC-BCM6858.patch @@ -0,0 +1,184 @@ +From e663e06bd3f21e64bc2163910f626af68add6308 Mon Sep 17 00:00:00 2001 +From: Anand Gore <anand.gore@broadcom.com> +Date: Wed, 1 Jun 2022 13:19:56 -0700 +Subject: [PATCH] ARM64: dts: Add DTS files for bcmbca SoC BCM6858 + +Add DTS for ARMv8 based broadband SoC BCM6858. bcm6858.dtsi is the SoC +description DTS header and bcm96858.dts is a simple DTS file for +Broadcom BCM96858 Reference board that only enables the UART port. + +Signed-off-by: Anand Gore <anand.gore@broadcom.com> +Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> +--- + arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +- + .../boot/dts/broadcom/bcmbca/bcm6858.dtsi | 121 ++++++++++++++++++ + .../boot/dts/broadcom/bcmbca/bcm96858.dts | 30 +++++ + 3 files changed, 153 insertions(+), 1 deletion(-) + create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi + create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts + +--- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile ++++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile +@@ -1,3 +1,4 @@ + # SPDX-License-Identifier: GPL-2.0 + dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \ +- bcm963158.dtb ++ bcm963158.dtb \ ++ bcm96858.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi +@@ -0,0 +1,121 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright 2022 Broadcom Ltd. ++ */ ++ ++#include <dt-bindings/interrupt-controller/irq.h> ++#include <dt-bindings/interrupt-controller/arm-gic.h> ++ ++/ { ++ compatible = "brcm,bcm6858", "brcm,bcmbca"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ interrupt-parent = <&gic>; ++ ++ cpus { ++ #address-cells = <2>; ++ #size-cells = <0>; ++ ++ B53_0: cpu@0 { ++ compatible = "brcm,brahma-b53"; ++ device_type = "cpu"; ++ reg = <0x0 0x0>; ++ next-level-cache = <&L2_0>; ++ enable-method = "psci"; ++ }; ++ ++ B53_1: cpu@1 { ++ compatible = "brcm,brahma-b53"; ++ device_type = "cpu"; ++ reg = <0x0 0x1>; ++ next-level-cache = <&L2_0>; ++ enable-method = "psci"; ++ }; ++ ++ B53_2: cpu@2 { ++ compatible = "brcm,brahma-b53"; ++ device_type = "cpu"; ++ reg = <0x0 0x2>; ++ next-level-cache = <&L2_0>; ++ enable-method = "psci"; ++ }; ++ ++ B53_3: cpu@3 { ++ compatible = "brcm,brahma-b53"; ++ device_type = "cpu"; ++ reg = <0x0 0x3>; ++ next-level-cache = <&L2_0>; ++ enable-method = "psci"; ++ }; ++ L2_0: l2-cache0 { ++ compatible = "cache"; ++ }; ++ }; ++ ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, ++ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, ++ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, ++ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; ++ }; ++ ++ pmu: pmu { ++ compatible = "arm,armv8-pmuv3"; ++ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-affinity = <&B53_0>, <&B53_1>, ++ <&B53_2>, <&B53_3>; ++ }; ++ ++ clocks: clocks { ++ periph_clk:periph-clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <200000000>; ++ }; ++ }; ++ ++ psci { ++ compatible = "arm,psci-0.2"; ++ method = "smc"; ++ }; ++ ++ axi@81000000 { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0x0 0x81000000 0x8000>; ++ ++ gic: interrupt-controller@1000 { ++ compatible = "arm,gic-400"; ++ #interrupt-cells = <3>; ++ interrupt-controller; ++ reg = <0x1000 0x1000>, /* GICD */ ++ <0x2000 0x2000>, /* GICC */ ++ <0x4000 0x2000>, /* GICH */ ++ <0x6000 0x2000>; /* GICV */ ++ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | ++ IRQ_TYPE_LEVEL_HIGH)>; ++ }; ++ }; ++ ++ bus@ff800000 { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0x0 0xff800000 0x62000>; ++ ++ uart0: serial@640 { ++ compatible = "brcm,bcm6345-uart"; ++ reg = <0x640 0x18>; ++ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&periph_clk>; ++ clock-names = "refclk"; ++ status = "disabled"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts +@@ -0,0 +1,30 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright 2022 Broadcom Ltd. ++ */ ++ ++/dts-v1/; ++ ++#include "bcm6858.dtsi" ++ ++/ { ++ model = "Broadcom BCM96858 Reference Board"; ++ compatible = "brcm,bcm96858", "brcm,bcm6858", "brcm,bcmbca"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x0 0x0 0x08000000>; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; diff --git a/target/linux/bcm4908/patches-5.10/037-v5.20-0004-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM63146.patch b/target/linux/bcm4908/patches-5.10/037-v5.20-0004-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM63146.patch new file mode 100644 index 0000000000..793c5af738 --- /dev/null +++ b/target/linux/bcm4908/patches-5.10/037-v5.20-0004-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM63146.patch @@ -0,0 +1,174 @@ +From 82a58061ada60058ec00113c179380f945914709 Mon Sep 17 00:00:00 2001 +From: William Zhang <william.zhang@broadcom.com> +Date: Wed, 8 Jun 2022 11:00:59 -0700 +Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM63146 + +Add DTS for ARMv8 based broadband SoC BCM63146. bcm63146.dtsi is the +SoC description DTS header and bcm963146.dts is a simple DTS file for +Broadcom BCM963146 Reference board that only enable the UART port. + +Signed-off-by: William Zhang <william.zhang@broadcom.com> +Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> +--- + arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +- + .../boot/dts/broadcom/bcmbca/bcm63146.dtsi | 110 ++++++++++++++++++ + .../boot/dts/broadcom/bcmbca/bcm963146.dts | 30 +++++ + 3 files changed, 142 insertions(+), 1 deletion(-) + create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi + create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts + +--- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile ++++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile +@@ -1,4 +1,5 @@ + # SPDX-License-Identifier: GPL-2.0 + dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \ + bcm963158.dtb \ +- bcm96858.dtb ++ bcm96858.dtb \ ++ bcm963146.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi +@@ -0,0 +1,110 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright 2022 Broadcom Ltd. ++ */ ++ ++#include <dt-bindings/interrupt-controller/irq.h> ++#include <dt-bindings/interrupt-controller/arm-gic.h> ++ ++/ { ++ compatible = "brcm,bcm63146", "brcm,bcmbca"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ interrupt-parent = <&gic>; ++ ++ cpus { ++ #address-cells = <2>; ++ #size-cells = <0>; ++ ++ B53_0: cpu@0 { ++ compatible = "brcm,brahma-b53"; ++ device_type = "cpu"; ++ reg = <0x0 0x0>; ++ next-level-cache = <&L2_0>; ++ enable-method = "psci"; ++ }; ++ ++ B53_1: cpu@1 { ++ compatible = "brcm,brahma-b53"; ++ device_type = "cpu"; ++ reg = <0x0 0x1>; ++ next-level-cache = <&L2_0>; ++ enable-method = "psci"; ++ }; ++ ++ L2_0: l2-cache0 { ++ compatible = "cache"; ++ }; ++ }; ++ ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, ++ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, ++ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, ++ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; ++ }; ++ ++ pmu: pmu { ++ compatible = "arm,cortex-a53-pmu"; ++ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-affinity = <&B53_0>, <&B53_1>; ++ }; ++ ++ clocks: clocks { ++ periph_clk: periph-clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <200000000>; ++ }; ++ uart_clk: uart-clk { ++ compatible = "fixed-factor-clock"; ++ #clock-cells = <0>; ++ clocks = <&periph_clk>; ++ clock-div = <4>; ++ clock-mult = <1>; ++ }; ++ }; ++ ++ psci { ++ compatible = "arm,psci-0.2"; ++ method = "smc"; ++ }; ++ ++ axi@81000000 { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0x0 0x81000000 0x8000>; ++ ++ gic: interrupt-controller@1000 { ++ compatible = "arm,gic-400"; ++ #interrupt-cells = <3>; ++ interrupt-controller; ++ reg = <0x1000 0x1000>, ++ <0x2000 0x2000>, ++ <0x4000 0x2000>, ++ <0x6000 0x2000>; ++ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | ++ IRQ_TYPE_LEVEL_HIGH)>; ++ }; ++ }; ++ ++ bus@ff800000 { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0x0 0xff800000 0x800000>; ++ ++ uart0: serial@12000 { ++ compatible = "arm,pl011", "arm,primecell"; ++ reg = <0x12000 0x1000>; ++ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&uart_clk>, <&uart_clk>; ++ clock-names = "uartclk", "apb_pclk"; ++ status = "disabled"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts +@@ -0,0 +1,30 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright 2022 Broadcom Ltd. ++ */ ++ ++/dts-v1/; ++ ++#include "bcm63146.dtsi" ++ ++/ { ++ model = "Broadcom BCM963146 Reference Board"; ++ compatible = "brcm,bcm963146", "brcm,bcm63146", "brcm,bcmbca"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x0 0x0 0x08000000>; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; diff --git a/target/linux/bcm4908/patches-5.10/037-v5.20-0005-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM6856.patch b/target/linux/bcm4908/patches-5.10/037-v5.20-0005-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM6856.patch new file mode 100644 index 0000000000..0fdafb7f17 --- /dev/null +++ b/target/linux/bcm4908/patches-5.10/037-v5.20-0005-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM6856.patch @@ -0,0 +1,167 @@ +From 64eca7ad058cff861b48cdead8dee40dfc284e9e Mon Sep 17 00:00:00 2001 +From: William Zhang <william.zhang@broadcom.com> +Date: Wed, 8 Jun 2022 11:04:36 -0700 +Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM6856 + +Add DTS for ARMv8 based broadband SoC BCM6856. bcm6856.dtsi is the +SoC description DTS header and bcm96856.dts is a simple DTS file for +Broadcom BCM96956 Reference board that only enable the UART port. + +Signed-off-by: William Zhang <william.zhang@broadcom.com> +Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> +--- + arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +- + .../boot/dts/broadcom/bcmbca/bcm6856.dtsi | 103 ++++++++++++++++++ + .../boot/dts/broadcom/bcmbca/bcm96856.dts | 30 +++++ + 3 files changed, 135 insertions(+), 1 deletion(-) + create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi + create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts + +--- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile ++++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile +@@ -2,4 +2,5 @@ + dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \ + bcm963158.dtb \ + bcm96858.dtb \ +- bcm963146.dtb ++ bcm963146.dtb \ ++ bcm96856.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi +@@ -0,0 +1,103 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright 2022 Broadcom Ltd. ++ */ ++ ++#include <dt-bindings/interrupt-controller/irq.h> ++#include <dt-bindings/interrupt-controller/arm-gic.h> ++ ++/ { ++ compatible = "brcm,bcm6856", "brcm,bcmbca"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ interrupt-parent = <&gic>; ++ ++ cpus { ++ #address-cells = <2>; ++ #size-cells = <0>; ++ ++ B53_0: cpu@0 { ++ compatible = "brcm,brahma-b53"; ++ device_type = "cpu"; ++ reg = <0x0 0x0>; ++ next-level-cache = <&L2_0>; ++ enable-method = "psci"; ++ }; ++ ++ B53_1: cpu@1 { ++ compatible = "brcm,brahma-b53"; ++ device_type = "cpu"; ++ reg = <0x0 0x1>; ++ next-level-cache = <&L2_0>; ++ enable-method = "psci"; ++ }; ++ ++ L2_0: l2-cache0 { ++ compatible = "cache"; ++ }; ++ }; ++ ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, ++ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, ++ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, ++ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; ++ }; ++ ++ pmu: pmu { ++ compatible = "arm,cortex-a53-pmu"; ++ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-affinity = <&B53_0>, <&B53_1>; ++ }; ++ ++ clocks: clocks { ++ periph_clk:periph-clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <200000000>; ++ }; ++ }; ++ ++ psci { ++ compatible = "arm,psci-0.2"; ++ method = "smc"; ++ }; ++ ++ axi@81000000 { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0x0 0x81000000 0x8000>; ++ ++ gic: interrupt-controller@1000 { ++ compatible = "arm,gic-400"; ++ #interrupt-cells = <3>; ++ interrupt-controller; ++ reg = <0x1000 0x1000>, /* GICD */ ++ <0x2000 0x2000>, /* GICC */ ++ <0x4000 0x2000>, /* GICH */ ++ <0x6000 0x2000>; /* GICV */ ++ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | ++ IRQ_TYPE_LEVEL_HIGH)>; ++ }; ++ }; ++ ++ bus@ff800000 { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0x0 0xff800000 0x800000>; ++ ++ uart0: serial@640 { ++ compatible = "brcm,bcm6345-uart"; ++ reg = <0x640 0x18>; ++ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&periph_clk>; ++ clock-names = "refclk"; ++ status = "disabled"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts +@@ -0,0 +1,30 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright 2022 Broadcom Ltd. ++ */ ++ ++/dts-v1/; ++ ++#include "bcm6856.dtsi" ++ ++/ { ++ model = "Broadcom BCM96856 Reference Board"; ++ compatible = "brcm,bcm96856", "brcm,bcm6856", "brcm,bcmbca"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x0 0x0 0x08000000>; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; diff --git a/target/linux/bcm4908/patches-5.10/037-v5.20-0006-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM6813.patch b/target/linux/bcm4908/patches-5.10/037-v5.20-0006-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM6813.patch new file mode 100644 index 0000000000..58af85a68c --- /dev/null +++ b/target/linux/bcm4908/patches-5.10/037-v5.20-0006-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM6813.patch @@ -0,0 +1,192 @@ +From eab6bb0994b806525fc5e362e8b865f61c4a9e20 Mon Sep 17 00:00:00 2001 +From: William Zhang <william.zhang@broadcom.com> +Date: Thu, 9 Jun 2022 17:15:33 -0700 +Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM6813 + +Add DTS for ARMv8 based broadband SoC BCM6813. bcm6813.dtsi is the +SoC description DTS header and bcm96813.dts is a simple DTS file for +Broadcom BCM96813 Reference board that only enable the UART port. + +Signed-off-by: William Zhang <william.zhang@broadcom.com> +Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> +--- + arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +- + .../boot/dts/broadcom/bcmbca/bcm6813.dtsi | 128 ++++++++++++++++++ + .../boot/dts/broadcom/bcmbca/bcm96813.dts | 30 ++++ + 3 files changed, 160 insertions(+), 1 deletion(-) + create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi + create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts + +--- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile ++++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile +@@ -3,4 +3,5 @@ dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dt + bcm963158.dtb \ + bcm96858.dtb \ + bcm963146.dtb \ +- bcm96856.dtb ++ bcm96856.dtb \ ++ bcm96813.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi +@@ -0,0 +1,128 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright 2022 Broadcom Ltd. ++ */ ++ ++#include <dt-bindings/interrupt-controller/irq.h> ++#include <dt-bindings/interrupt-controller/arm-gic.h> ++ ++/ { ++ compatible = "brcm,bcm6813", "brcm,bcmbca"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ interrupt-parent = <&gic>; ++ ++ cpus { ++ #address-cells = <2>; ++ #size-cells = <0>; ++ ++ B53_0: cpu@0 { ++ compatible = "brcm,brahma-b53"; ++ device_type = "cpu"; ++ reg = <0x0 0x0>; ++ next-level-cache = <&L2_0>; ++ enable-method = "psci"; ++ }; ++ ++ B53_1: cpu@1 { ++ compatible = "brcm,brahma-b53"; ++ device_type = "cpu"; ++ reg = <0x0 0x1>; ++ next-level-cache = <&L2_0>; ++ enable-method = "psci"; ++ }; ++ ++ B53_2: cpu@2 { ++ compatible = "brcm,brahma-b53"; ++ device_type = "cpu"; ++ reg = <0x0 0x2>; ++ next-level-cache = <&L2_0>; ++ enable-method = "psci"; ++ }; ++ ++ B53_3: cpu@3 { ++ compatible = "brcm,brahma-b53"; ++ device_type = "cpu"; ++ reg = <0x0 0x3>; ++ next-level-cache = <&L2_0>; ++ enable-method = "psci"; ++ }; ++ ++ L2_0: l2-cache0 { ++ compatible = "cache"; ++ }; ++ }; ++ ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, ++ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, ++ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, ++ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; ++ }; ++ ++ pmu: pmu { ++ compatible = "arm,cortex-a53-pmu"; ++ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-affinity = <&B53_0>, <&B53_1>, ++ <&B53_2>, <&B53_3>; ++ }; ++ ++ clocks: clocks { ++ periph_clk: periph-clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <200000000>; ++ }; ++ uart_clk: uart-clk { ++ compatible = "fixed-factor-clock"; ++ #clock-cells = <0>; ++ clocks = <&periph_clk>; ++ clock-div = <4>; ++ clock-mult = <1>; ++ }; ++ }; ++ ++ psci { ++ compatible = "arm,psci-0.2"; ++ method = "smc"; ++ }; ++ ++ axi@81000000 { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0x0 0x81000000 0x8000>; ++ ++ gic: interrupt-controller@1000 { ++ compatible = "arm,gic-400"; ++ #interrupt-cells = <3>; ++ interrupt-controller; ++ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; ++ reg = <0x1000 0x1000>, ++ <0x2000 0x2000>, ++ <0x4000 0x2000>, ++ <0x6000 0x2000>; ++ }; ++ }; ++ ++ bus@ff800000 { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0x0 0xff800000 0x800000>; ++ ++ uart0: serial@12000 { ++ compatible = "arm,pl011", "arm,primecell"; ++ reg = <0x12000 0x1000>; ++ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&uart_clk>, <&uart_clk>; ++ clock-names = "uartclk", "apb_pclk"; ++ status = "disabled"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts +@@ -0,0 +1,30 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright 2022 Broadcom Ltd. ++ */ ++ ++/dts-v1/; ++ ++#include "bcm6813.dtsi" ++ ++/ { ++ model = "Broadcom BCM96813 Reference Board"; ++ compatible = "brcm,bcm96813", "brcm,bcm6813", "brcm,bcmbca"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x0 0x0 0x08000000>; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; diff --git a/target/linux/bcm4908/patches-5.10/037-v5.20-0001-arm64-dts-broadcom-align-gpio-key-node-names-with-dt.patch b/target/linux/bcm4908/patches-5.10/037-v5.20-0007-arm64-dts-broadcom-align-gpio-key-node-names-with-dt.patch index d0d6151957..d0d6151957 100644 --- a/target/linux/bcm4908/patches-5.10/037-v5.20-0001-arm64-dts-broadcom-align-gpio-key-node-names-with-dt.patch +++ b/target/linux/bcm4908/patches-5.10/037-v5.20-0007-arm64-dts-broadcom-align-gpio-key-node-names-with-dt.patch diff --git a/target/linux/bcm4908/patches-5.10/037-v5.20-0002-arm64-dts-broadcom-bcm4908-Fix-timer-node-for-BCM490.patch b/target/linux/bcm4908/patches-5.10/037-v5.20-0008-arm64-dts-broadcom-bcm4908-Fix-timer-node-for-BCM490.patch index c2b924a0fd..c2b924a0fd 100644 --- a/target/linux/bcm4908/patches-5.10/037-v5.20-0002-arm64-dts-broadcom-bcm4908-Fix-timer-node-for-BCM490.patch +++ b/target/linux/bcm4908/patches-5.10/037-v5.20-0008-arm64-dts-broadcom-bcm4908-Fix-timer-node-for-BCM490.patch diff --git a/target/linux/bcm4908/patches-5.10/037-v5.20-0003-arm64-dts-broadcom-bcm4908-Fix-cpu-node-for-smp-boot.patch b/target/linux/bcm4908/patches-5.10/037-v5.20-0009-arm64-dts-broadcom-bcm4908-Fix-cpu-node-for-smp-boot.patch index 482fd1cc98..482fd1cc98 100644 --- a/target/linux/bcm4908/patches-5.10/037-v5.20-0003-arm64-dts-broadcom-bcm4908-Fix-cpu-node-for-smp-boot.patch +++ b/target/linux/bcm4908/patches-5.10/037-v5.20-0009-arm64-dts-broadcom-bcm4908-Fix-cpu-node-for-smp-boot.patch diff --git a/target/linux/bcm4908/patches-5.10/037-v5.20-0010-arm64-dts-Add-base-DTS-file-for-bcmbca-device-Asus-G.patch b/target/linux/bcm4908/patches-5.10/037-v5.20-0010-arm64-dts-Add-base-DTS-file-for-bcmbca-device-Asus-G.patch new file mode 100644 index 0000000000..6f71c8b5fb --- /dev/null +++ b/target/linux/bcm4908/patches-5.10/037-v5.20-0010-arm64-dts-Add-base-DTS-file-for-bcmbca-device-Asus-G.patch @@ -0,0 +1,54 @@ +From f3f575c4bef95384e68de552c7b29938fd0d9201 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl> +Date: Wed, 13 Jul 2022 22:03:51 +0200 +Subject: [PATCH] arm64: dts: Add base DTS file for bcmbca device Asus + GT-AX6000 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +It's a home router with 1 GiB of RAM, 6 Ethernet ports, 2 USB ports. + +Signed-off-by: Rafał Miłecki <rafal@milecki.pl> +Acked-by: William Zhang <william.zhang@broadcom.com> +Link: https://lore.kernel.org/r/20220713200351.28526-2-zajec5@gmail.com +Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> +--- + arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 4 +++- + .../bcmbca/bcm4912-asus-gt-ax6000.dts | 19 +++++++++++++++++++ + 2 files changed, 22 insertions(+), 1 deletion(-) + create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm4912-asus-gt-ax6000.dts + +--- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile ++++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile +@@ -1,5 +1,7 @@ + # SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \ ++dtb-$(CONFIG_ARCH_BCMBCA) += \ ++ bcm4912-asus-gt-ax6000.dtb \ ++ bcm94912.dtb \ + bcm963158.dtb \ + bcm96858.dtb \ + bcm963146.dtb \ +--- /dev/null ++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912-asus-gt-ax6000.dts +@@ -0,0 +1,19 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++ ++/dts-v1/; ++ ++#include "bcm4912.dtsi" ++ ++/ { ++ compatible = "asus,gt-ax6000", "brcm,bcm4912", "brcm,bcmbca"; ++ model = "Asus GT-AX6000"; ++ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x00 0x00 0x00 0x40000000>; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; |