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-rw-r--r--package/boot/uboot-envtools/files/realtek1
-rw-r--r--target/linux/realtek/dts-5.10/rtl8382_zyxel_gs1900-24e.dts63
-rw-r--r--target/linux/realtek/image/rtl838x.mk8
3 files changed, 72 insertions, 0 deletions
diff --git a/package/boot/uboot-envtools/files/realtek b/package/boot/uboot-envtools/files/realtek
index 99a73a6ab1..af48d27078 100644
--- a/package/boot/uboot-envtools/files/realtek
+++ b/package/boot/uboot-envtools/files/realtek
@@ -17,6 +17,7 @@ zyxel,gs1900-8hp-v2|\
zyxel,gs1900-10hp|\
zyxel,gs1900-16|\
zyxel,gs1900-24-v1|\
+zyxel,gs1900-24e|\
zyxel,gs1900-24hp-v1|\
zyxel,gs1900-24hp-v2)
idx="$(find_mtd_index u-boot-env)"
diff --git a/target/linux/realtek/dts-5.10/rtl8382_zyxel_gs1900-24e.dts b/target/linux/realtek/dts-5.10/rtl8382_zyxel_gs1900-24e.dts
new file mode 100644
index 0000000000..3d00034a3b
--- /dev/null
+++ b/target/linux/realtek/dts-5.10/rtl8382_zyxel_gs1900-24e.dts
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_zyxel_gs1900.dtsi"
+
+/ {
+ compatible = "zyxel,gs1900-24e", "realtek,rtl838x-soc";
+ model = "ZyXEL GS1900-24E";
+};
+
+&mdio {
+ EXTERNAL_PHY(0)
+ EXTERNAL_PHY(1)
+ EXTERNAL_PHY(2)
+ EXTERNAL_PHY(3)
+ EXTERNAL_PHY(4)
+ EXTERNAL_PHY(5)
+ EXTERNAL_PHY(6)
+ EXTERNAL_PHY(7)
+
+ EXTERNAL_PHY(16)
+ EXTERNAL_PHY(17)
+ EXTERNAL_PHY(18)
+ EXTERNAL_PHY(19)
+ EXTERNAL_PHY(20)
+ EXTERNAL_PHY(21)
+ EXTERNAL_PHY(22)
+ EXTERNAL_PHY(23)
+};
+
+&switch0 {
+ ports {
+ SWITCH_PORT(1, 1, qsgmii)
+ SWITCH_PORT(0, 2, qsgmii)
+ SWITCH_PORT(3, 3, qsgmii)
+ SWITCH_PORT(2, 4, qsgmii)
+ SWITCH_PORT(5, 5, qsgmii)
+ SWITCH_PORT(4, 6, qsgmii)
+ SWITCH_PORT(7, 7, qsgmii)
+ SWITCH_PORT(6, 8, qsgmii)
+
+ SWITCH_PORT(9, 9, internal)
+ SWITCH_PORT(8, 10, internal)
+ SWITCH_PORT(11, 11, internal)
+ SWITCH_PORT(10, 12, internal)
+ SWITCH_PORT(13, 13, internal)
+ SWITCH_PORT(12, 14, internal)
+ SWITCH_PORT(15, 15, internal)
+ SWITCH_PORT(14, 16, internal)
+
+ SWITCH_PORT(17, 17, qsgmii)
+ SWITCH_PORT(16, 18, qsgmii)
+ SWITCH_PORT(19, 19, qsgmii)
+ SWITCH_PORT(18, 20, qsgmii)
+ SWITCH_PORT(21, 21, qsgmii)
+ SWITCH_PORT(20, 22, qsgmii)
+ SWITCH_PORT(23, 23, qsgmii)
+ SWITCH_PORT(22, 24, qsgmii)
+ };
+};
+
+&gpio1 {
+ /delete-node/ poe_enable;
+};
diff --git a/target/linux/realtek/image/rtl838x.mk b/target/linux/realtek/image/rtl838x.mk
index e17dc8c62d..289e37db16 100644
--- a/target/linux/realtek/image/rtl838x.mk
+++ b/target/linux/realtek/image/rtl838x.mk
@@ -153,6 +153,14 @@ define Device/zyxel_gs1900-24-v1
endef
TARGET_DEVICES += zyxel_gs1900-24-v1
+define Device/zyxel_gs1900-24e
+ $(Device/zyxel_gs1900)
+ SOC := rtl8382
+ DEVICE_MODEL := GS1900-24E
+ ZYXEL_VERS := AAHK
+endef
+TARGET_DEVICES += zyxel_gs1900-24e
+
define Device/zyxel_gs1900-24hp-v1
$(Device/zyxel_gs1900)
SOC := rtl8382