diff options
2 files changed, 4 insertions, 4 deletions
diff --git a/target/linux/ipq806x/patches-4.14/0038-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch b/target/linux/ipq806x/patches-4.14/0038-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch index e0157d56b8..f09197caa8 100644 --- a/target/linux/ipq806x/patches-4.14/0038-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch +++ b/target/linux/ipq806x/patches-4.14/0038-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch @@ -117,7 +117,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> + * H/W requires a 5us delay between disabling the bypass and + * de-asserting the reset. Delay 10us just to be safe. + */ -+ usleep_range(10, 100); ++ udelay(10); + + /* De-assert active-low PLL reset. */ + regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N); @@ -128,7 +128,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> + regmap_read(regmap, hd->status_reg, &val); + } while (!(val & BIT(hd->lock_bit))); + } else { -+ usleep_range(60, 100); ++ udelay(60); + } + + /* Enable PLL output. */ diff --git a/target/linux/ipq806x/patches-4.9/0038-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch b/target/linux/ipq806x/patches-4.9/0038-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch index 70926143ec..a2067572b1 100644 --- a/target/linux/ipq806x/patches-4.9/0038-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch +++ b/target/linux/ipq806x/patches-4.9/0038-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch @@ -117,7 +117,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> + * H/W requires a 5us delay between disabling the bypass and + * de-asserting the reset. Delay 10us just to be safe. + */ -+ usleep_range(10, 100); ++ udelay(10); + + /* De-assert active-low PLL reset. */ + regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N); @@ -128,7 +128,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> + regmap_read(regmap, hd->status_reg, &val); + } while (!(val & BIT(hd->lock_bit))); + } else { -+ usleep_range(60, 100); ++ udelay(60); + } + + /* Enable PLL output. */ |