diff options
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/ar71xx/dev-ar9xxx-wmac.c | 29 | ||||
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h | 2 |
2 files changed, 31 insertions, 0 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/dev-ar9xxx-wmac.c b/target/linux/ar71xx/files/arch/mips/ar71xx/dev-ar9xxx-wmac.c index d4104726b6..e5cd4d3ff4 100644 --- a/target/linux/ar71xx/files/arch/mips/ar71xx/dev-ar9xxx-wmac.c +++ b/target/linux/ar71xx/files/arch/mips/ar71xx/dev-ar9xxx-wmac.c @@ -68,6 +68,31 @@ static int ar933x_r1_get_wmac_revision(void) return ar71xx_soc_rev; } +static int ar933x_wmac_reset(void) +{ + unsigned retries = 0; + + ar71xx_device_stop(AR933X_RESET_WMAC); + ar71xx_device_start(AR933X_RESET_WMAC); + + while (1) { + u32 bootstrap; + + bootstrap = ar71xx_reset_rr(AR933X_RESET_REG_BOOTSTRAP); + if ((bootstrap & AR933X_BOOTSTRAP_EEPBUSY) == 0) + return 0; + + if (retries > 20) + break; + + udelay(10000); + retries++; + } + + pr_err("ar93xx: WMAC reset timed out"); + return -ETIMEDOUT; +} + static void ar933x_wmac_init(void) { ar9xxx_wmac_device.name = "ar933x_wmac"; @@ -78,6 +103,10 @@ static void ar933x_wmac_init(void) if (ar71xx_soc_rev == 1) ar9xxx_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision; + + ar9xxx_wmac_data.external_reset = ar933x_wmac_reset; + + ar933x_wmac_reset(); } static void ar934x_wmac_init(void) diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h index a001f89dbc..f78ae16651 100644 --- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h +++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h @@ -609,6 +609,7 @@ void ar71xx_ddr_flush(u32 reg); #define AR933X_RESET_REG_RESET_MODULE 0x1c #define AR933X_RESET_REG_BOOTSTRAP 0xac +#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) #define AR934X_RESET_REG_RESET_MODULE 0x1c @@ -672,6 +673,7 @@ void ar71xx_ddr_flush(u32 reg); #define AR724X_RESET_USB_PHY BIT(4) #define AR724X_RESET_USBSUS_OVERRIDE BIT(3) +#define AR933X_RESET_WMAC BIT(11) #define AR933X_RESET_GE1_MDIO BIT(23) #define AR933X_RESET_GE0_MDIO BIT(22) #define AR933X_RESET_GE1_MAC BIT(13) |