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authorJonas Gorski <jogo@openwrt.org>2015-02-27 17:40:17 +0000
committerJonas Gorski <jogo@openwrt.org>2015-02-27 17:40:17 +0000
commitd75cd5be3797f8927c2fd8b71939228c257d728e (patch)
tree42972c592cc07bebc2bcc7384e4da712dfa2bdd5 /tools/libelf
parent8ff23c60e21ce9e2e2f97f15410b57c02b16bdf2 (diff)
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b53: fix mmap register read/writes > 32 bit
For bcm63xx integrated switches, broadcom changed the data endianess to match the system endianess. But this only applies to within one word, which causes 48/64 bit values to be still split into their "litte endian" groups. E.g. 48 bit values (with 5 being the most significant byte) aligned 0x00 ..01 or 0123 0x04 2345 45.. will become 0x00 ..10 resp. 3210 0x04 5432 54.. Likewise for 64 bit values. Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 44568
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