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| author | Adrian Schmutzler <freifunk@adrianschmutzler.de> | 2018-01-19 14:45:42 +0100 |
|---|---|---|
| committer | Matthias Schiffer <mschiffer@universe-factory.net> | 2018-06-23 16:06:31 +0200 |
| commit | 5c5bf8b8658a588423f6ec445d7ef6a36f99a396 (patch) | |
| tree | b0f658286508b3ac5451f031f4c61b1cfaa643a9 /tools/firmware-utils/src/mkdlinkfw-lib.c | |
| parent | 2524febf7927a1bf430d64b7790feb126023e3d1 (diff) | |
| download | upstream-5c5bf8b8658a588423f6ec445d7ef6a36f99a396.tar.gz upstream-5c5bf8b8658a588423f6ec445d7ef6a36f99a396.tar.bz2 upstream-5c5bf8b8658a588423f6ec445d7ef6a36f99a396.zip | |
ar71xx: Add support for TP-Link CPE210 v2
This PR adds support for a popular low-cost 2.4GHz N based AP
Specifications:
- SoC: Qualcomm Atheros QCA9533 (650MHz)
- RAM: 64MB
- Storage: 8 MB SPI NOR
- Wireless: 2.4GHz N based built into SoC 2x2
- Ethernet: 1x 100/10 Mbps, integrated into SoC, 24V POE IN
Installation:
Flash factory image through stock firmware WEB UI
or through TFTP
To get to TFTP recovery just hold reset button while powering on for
around 4-5 seconds and release.
Rename factory image to recovery.bin
Stock TFTP server IP:192.168.0.100
Stock device TFTP adress:192.168.0.254
Notes:
TP-Link does not use bootstrap registers so without this patch reference
clock detects as 40MHz while it is actually 25MHz.
This is due to messed up bootstrap resistor configuration on the PCB.
Provided GPL code just forces 25MHz reference clock.
That causes booting with completely wrong clocks, for example, CPU tries
to boot at 1040MHz while the stock is 650MHz.
So this PR depends on PR #672 to remove 40MHz reference clock.
Thanks to Sven Eckelmann <sven@narfation.org> for properly patching that.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Diffstat (limited to 'tools/firmware-utils/src/mkdlinkfw-lib.c')
0 files changed, 0 insertions, 0 deletions