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authorFelix Fietkau <nbd@nbd.name>2018-03-12 10:28:03 +0100
committerFelix Fietkau <nbd@nbd.name>2018-03-12 12:19:07 +0100
commit16cec7ae67d9a1e88cb30b45f45596ba753b2afa (patch)
treed87f443c4d8a965b9b72f127d13ec12d78d88e56 /toolchain/gcc/patches/7.3.0/110-Fix-MIPS-PR-84790.patch
parentfe98f2679c2e73245c06a4b6a404abba4a915930 (diff)
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toolchain/gcc: merge pending fix for miscompiled MIPS16 code issue (GCC PR 84790)
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Diffstat (limited to 'toolchain/gcc/patches/7.3.0/110-Fix-MIPS-PR-84790.patch')
-rw-r--r--toolchain/gcc/patches/7.3.0/110-Fix-MIPS-PR-84790.patch20
1 files changed, 20 insertions, 0 deletions
diff --git a/toolchain/gcc/patches/7.3.0/110-Fix-MIPS-PR-84790.patch b/toolchain/gcc/patches/7.3.0/110-Fix-MIPS-PR-84790.patch
new file mode 100644
index 0000000000..643c5e68a8
--- /dev/null
+++ b/toolchain/gcc/patches/7.3.0/110-Fix-MIPS-PR-84790.patch
@@ -0,0 +1,20 @@
+Fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84790.
+MIPS16 functions have a static assembler prologue which clobbers
+registers v0 and v1. Add these register clobbers to function call
+instructions.
+
+--- a/gcc/config/mips/mips.c
++++ b/gcc/config/mips/mips.c
+@@ -3098,6 +3098,12 @@ mips_emit_call_insn (rtx pattern, rtx or
+ emit_insn (gen_update_got_version ());
+ }
+
++ if (TARGET_MIPS16 && TARGET_USE_GOT)
++ {
++ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS16_PIC_TEMP);
++ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS_PROLOGUE_TEMP (word_mode));
++ }
++
+ if (TARGET_MIPS16
+ && TARGET_EXPLICIT_RELOCS
+ && TARGET_CALL_CLOBBERED_GP)