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| author | Rui Salvaterra <rsalvaterra@gmail.com> | 2022-05-06 15:42:06 +0100 |
|---|---|---|
| committer | Paul Spooren <mail@aparcar.org> | 2022-06-01 14:59:49 +0200 |
| commit | c4bd303086012afe2aebd213c892363512138bb7 (patch) | |
| tree | b8d78ba52ead2356d7af766d802f1524a73d0c08 /toolchain/gcc/patches/12.1.0/110-Fix-MIPS-PR-84790.patch | |
| parent | 8885cf88279fd131c163d0ac34aeeef0bbff0ceb (diff) | |
| download | upstream-c4bd303086012afe2aebd213c892363512138bb7.tar.gz upstream-c4bd303086012afe2aebd213c892363512138bb7.tar.bz2 upstream-c4bd303086012afe2aebd213c892363512138bb7.zip | |
toolchain: add support for GCC 12
GCC 12.1 is out. Add support for it.
Deleted (upstreamed):
011-v12-configure-define-TARGET_LIBC_GNUSTACK-on-musl.patch
931-libffi-fix-MIPS-softfloat-build-issue.patch
Deleted (unneeded?)
970-macos_arm64-building-fix.patch
Other patches manually rebased due to C++ conversion and consequent file name
changing (.c to .cc).
Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
Diffstat (limited to 'toolchain/gcc/patches/12.1.0/110-Fix-MIPS-PR-84790.patch')
| -rw-r--r-- | toolchain/gcc/patches/12.1.0/110-Fix-MIPS-PR-84790.patch | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/toolchain/gcc/patches/12.1.0/110-Fix-MIPS-PR-84790.patch b/toolchain/gcc/patches/12.1.0/110-Fix-MIPS-PR-84790.patch new file mode 100644 index 0000000000..856fd6a46c --- /dev/null +++ b/toolchain/gcc/patches/12.1.0/110-Fix-MIPS-PR-84790.patch @@ -0,0 +1,20 @@ +Fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84790. +MIPS16 functions have a static assembler prologue which clobbers +registers v0 and v1. Add these register clobbers to function call +instructions. + +--- a/gcc/config/mips/mips.cc ++++ b/gcc/config/mips/mips.cc +@@ -3134,6 +3134,12 @@ mips_emit_call_insn (rtx pattern, rtx or + emit_insn (gen_update_got_version ()); + } + ++ if (TARGET_MIPS16 && TARGET_USE_GOT) ++ { ++ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS16_PIC_TEMP); ++ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS_PROLOGUE_TEMP (word_mode)); ++ } ++ + if (TARGET_MIPS16 + && TARGET_EXPLICIT_RELOCS + && TARGET_CALL_CLOBBERED_GP) |