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authorDENG Qingfang <dengqf6@mail2.sysu.edu.cn>2020-08-25 12:03:28 +0800
committerHauke Mehrtens <hauke@hauke-m.de>2020-08-31 22:11:23 +0200
commit21abc09cd6a106714664519283d0cb9e92ff7ef4 (patch)
treea6ab7e87f89c9be0d317ca185d06003b21e8e59d /toolchain/gcc/patches/10.2.0/110-Fix-MIPS-PR-84790.patch
parent69630140ec8542c955f5be4268ff4e53c6646f89 (diff)
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toolchain: Update GCC 10 to version 10.2.0
Signed-off-by: DENG Qingfang <dengqf6@mail2.sysu.edu.cn>
Diffstat (limited to 'toolchain/gcc/patches/10.2.0/110-Fix-MIPS-PR-84790.patch')
-rw-r--r--toolchain/gcc/patches/10.2.0/110-Fix-MIPS-PR-84790.patch20
1 files changed, 20 insertions, 0 deletions
diff --git a/toolchain/gcc/patches/10.2.0/110-Fix-MIPS-PR-84790.patch b/toolchain/gcc/patches/10.2.0/110-Fix-MIPS-PR-84790.patch
new file mode 100644
index 0000000000..82ac013d30
--- /dev/null
+++ b/toolchain/gcc/patches/10.2.0/110-Fix-MIPS-PR-84790.patch
@@ -0,0 +1,20 @@
+Fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84790.
+MIPS16 functions have a static assembler prologue which clobbers
+registers v0 and v1. Add these register clobbers to function call
+instructions.
+
+--- a/gcc/config/mips/mips.c
++++ b/gcc/config/mips/mips.c
+@@ -3132,6 +3132,12 @@ mips_emit_call_insn (rtx pattern, rtx or
+ emit_insn (gen_update_got_version ());
+ }
+
++ if (TARGET_MIPS16 && TARGET_USE_GOT)
++ {
++ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS16_PIC_TEMP);
++ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS_PROLOGUE_TEMP (word_mode));
++ }
++
+ if (TARGET_MIPS16
+ && TARGET_EXPLICIT_RELOCS
+ && TARGET_CALL_CLOBBERED_GP)