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authorChuanhong Guo <gch981213@gmail.com>2020-09-13 18:49:26 +0800
committerChuanhong Guo <gch981213@gmail.com>2020-09-13 18:49:26 +0800
commit6f2c95f0cf0519631adb5100ab71f908a2968cca (patch)
tree84f29c0c85be83492ed6e45e6edeadb5ad422682 /target
parentf0cc5f6c0a72b7da9ed5915cf561e2f81d514c68 (diff)
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ramips: mt7621: pbr-m1: add pcie reset for asm1061
this board has a pcie to sata bridge connected to pcie2 with a separated pcie reset on gpio7. add reset-gpios and corresponding pinctrl nodes into dts. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Diffstat (limited to 'target')
-rw-r--r--target/linux/ramips/dts/mt7621_d-team_pbr-m1.dts12
1 files changed, 12 insertions, 0 deletions
diff --git a/target/linux/ramips/dts/mt7621_d-team_pbr-m1.dts b/target/linux/ramips/dts/mt7621_d-team_pbr-m1.dts
index 6b4d3b35d4..1e17eadde1 100644
--- a/target/linux/ramips/dts/mt7621_d-team_pbr-m1.dts
+++ b/target/linux/ramips/dts/mt7621_d-team_pbr-m1.dts
@@ -144,8 +144,20 @@
};
};
+&pinctrl {
+ uart3_gpio: uart3-gpio {
+ uart3 {
+ groups = "uart3";
+ function = "gpio";
+ };
+ };
+};
+
&pcie {
status = "okay";
+ pinctrl-0 = <&pcie_pins>, <&uart3_gpio>;
+ reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>,
+ <&gpio 7 GPIO_ACTIVE_LOW>;
};
&pcie0 {