ramips: replace mt7621s hack with upstream patch

Refresh patches.

Tested on a dual-core MT7621 device (Ubiquiti ER-X) and a single-core
MT7621 device (Netgear R6220).

This change will make future kernel upgrades easier (avoids conflicts
with upstream).

Link: https://lore.kernel.org/lkml/20210407200738.149207-1-ilya.lipnitskiy@gmail.com/
Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
Cc: Chuanhong Guo <gch981213@gmail.com>

4 files changed, 80 insertions, 68 deletions

diff --git a/target/linux/ramips/patches-5.10/320-MIPS-add-support-for-buggy-MT7621S-core-detection.patch b/target/linux/ramips/patches-5.10/320-MIPS-add-support-for-buggy-MT7621S-core-detection.patch
new file mode 100644
index 0000000000..0eb6676414
--- /dev/null
+++ b/target/linux/ramips/patches-5.10/320-MIPS-add-support-for-buggy-MT7621S-core-detection.patch
@@ -0,0 +1,74 @@
+From 6decd1aad15f56b169217789630a0098b496de0e Mon Sep 17 00:00:00 2001
+From: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
+Date: Wed, 7 Apr 2021 13:07:38 -0700
+Subject: [PATCH] MIPS: add support for buggy MT7621S core detection
+
+Most MT7621 SoCs have 2 cores, which is detected and supported properly
+by CPS.
+
+Unfortunately, MT7621 SoC has a less common S variant with only one core.
+On MT7621S, GCR_CONFIG still reports 2 cores, which leads to hangs when
+starting SMP. CPULAUNCH registers can be used in that case to detect the
+absence of the second core and override the GCR_CONFIG PCORES field.
+
+Rework a long-standing OpenWrt patch to override the value of
+mips_cps_numcores on single-core MT7621 systems.
+
+Tested on a dual-core MT7621 device (Ubiquiti ER-X) and a single-core
+MT7621 device (Netgear R6220).
+
+Original 4.14 OpenWrt patch:
+Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=commitdiff;h=4cdbc90a376dd0555201c1434a2081e055e9ceb7
+Current 5.10 OpenWrt patch:
+Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=blob;f=target/linux/ramips/patches-5.10/320-mt7621-core-detect-hack.patch;h=c63f0f4c1ec742e24d8480e80553863744b58f6a;hb=10267e17299806f9885d086147878f6c492cb904
+
+Suggested-by: Felix Fietkau <nbd@nbd.name>
+Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ arch/mips/include/asm/mips-cps.h | 23 ++++++++++++++++++++++-
+ 1 file changed, 22 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/include/asm/mips-cps.h
++++ b/arch/mips/include/asm/mips-cps.h
+@@ -10,6 +10,8 @@
+ #include <linux/io.h>
+ #include <linux/types.h>
+ 
++#include <asm/mips-boards/launch.h>
++
+ extern unsigned long __cps_access_bad_size(void)
+ 	__compiletime_error("Bad size for CPS accessor");
+ 
+@@ -165,11 +167,30 @@ static inline uint64_t mips_cps_cluster_
+  */
+ static inline unsigned int mips_cps_numcores(unsigned int cluster)
+ {
++	unsigned int ncores;
++
+ 	if (!mips_cm_present())
+ 		return 0;
+ 
+ 	/* Add one before masking to handle 0xff indicating no cores */
+-	return (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES;
++	ncores = (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES;
++
++	if (IS_ENABLED(CONFIG_SOC_MT7621)) {
++		struct cpulaunch *launch;
++
++		/*
++		 * Ralink MT7621S SoC is single core, but the GCR_CONFIG method
++		 * always reports 2 cores. Check the second core's LAUNCH_FREADY
++		 * flag to detect if the second core is missing. This method
++		 * only works before the core has been started.
++		 */
++		launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
++		launch += 2; /* MT7621 has 2 VPEs per core */
++		if (!(launch->flags & LAUNCH_FREADY))
++			ncores = 1;
++	}
++
++	return ncores;
+ }
+ 
+ /**
diff --git a/target/linux/ramips/patches-5.10/320-mt7621-core-detect-hack.patch b/target/linux/ramips/patches-5.10/320-mt7621-core-detect-hack.patch
deleted file mode 100644
index c63f0f4c1e..0000000000
--- a/target/linux/ramips/patches-5.10/320-mt7621-core-detect-hack.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-There is a variant of MT7621 which contains only one CPU core instead of 2.
-This is not reflected in the config register, so the kernel detects more
-physical cores, which leads to a hang on SMP bringup.
-Add a hack to detect missing cores.
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
-
---- a/arch/mips/kernel/smp-cps.c
-+++ b/arch/mips/kernel/smp-cps.c
-@@ -43,6 +43,11 @@ static unsigned core_vpe_count(unsigned
- 	return mips_cps_numvps(cluster, core);
- }
- 
-+bool __weak plat_cpu_core_present(int core)
-+{
-+	return true;
-+}
-+
- static void __init cps_smp_setup(void)
- {
- 	unsigned int nclusters, ncores, nvpes, core_vpes;
-@@ -60,6 +65,8 @@ static void __init cps_smp_setup(void)
- 
- 		ncores = mips_cps_numcores(cl);
- 		for (c = 0; c < ncores; c++) {
-+			if (!plat_cpu_core_present(c))
-+				continue;
- 			core_vpes = core_vpe_count(cl, c);
- 
- 			if (c > 0)
---- a/arch/mips/ralink/mt7621.c
-+++ b/arch/mips/ralink/mt7621.c
-@@ -15,6 +15,7 @@
- #include <asm/mips-cps.h>
- #include <asm/mach-ralink/ralink_regs.h>
- #include <asm/mach-ralink/mt7621.h>
-+#include <asm/mips-boards/launch.h>
- 
- #include <pinmux.h>
- 
-@@ -146,6 +147,20 @@ static void soc_dev_init(struct ralink_s
- 	}
- }
- 
-+bool plat_cpu_core_present(int core)
-+{
-+	struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
-+
-+	if (!core)
-+		return true;
-+	launch += core * 2; /* 2 VPEs per core */
-+	if (!(launch->flags & LAUNCH_FREADY))
-+		return false;
-+	if (launch->flags & (LAUNCH_FGO | LAUNCH_FGONE))
-+		return false;
-+	return true;
-+}
-+
- void prom_soc_init(struct ralink_soc_info *soc_info)
- {
- 	void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
diff --git a/target/linux/ramips/patches-5.10/322-mt7621-fix-cpu-clk-add-clkdev.patch b/target/linux/ramips/patches-5.10/322-mt7621-fix-cpu-clk-add-clkdev.patch
index be5fee54b2..87f8081367 100644
--- a/target/linux/ramips/patches-5.10/322-mt7621-fix-cpu-clk-add-clkdev.patch
+++ b/target/linux/ramips/patches-5.10/322-mt7621-fix-cpu-clk-add-clkdev.patch
@@ -36,7 +36,7 @@
  #define MT7621_DDR2_SIZE_MAX		256
 --- a/arch/mips/ralink/mt7621.c
 +++ b/arch/mips/ralink/mt7621.c
-@@ -9,6 +9,10 @@
+@@ -9,12 +9,17 @@
  #include <linux/init.h>
  #include <linux/slab.h>
  #include <linux/sys_soc.h>
@@ -47,15 +47,14 @@
  
  #include <asm/mipsregs.h>
  #include <asm/smp-ops.h>
-@@ -16,6 +20,7 @@
+ #include <asm/mips-cps.h>
  #include <asm/mach-ralink/ralink_regs.h>
  #include <asm/mach-ralink/mt7621.h>
- #include <asm/mips-boards/launch.h>
 +#include <asm/time.h>
  
  #include <pinmux.h>
  
-@@ -106,11 +111,89 @@ static struct rt2880_pmx_group mt7621_pi
+@@ -105,11 +110,89 @@ static struct rt2880_pmx_group mt7621_pi
  	{ 0 }
  };
  
diff --git a/target/linux/ramips/patches-5.10/323-mt7621-memory-detect.patch b/target/linux/ramips/patches-5.10/323-mt7621-memory-detect.patch
index 6dd4a1daa9..e87263d3c9 100644
--- a/target/linux/ramips/patches-5.10/323-mt7621-memory-detect.patch
+++ b/target/linux/ramips/patches-5.10/323-mt7621-memory-detect.patch
@@ -58,7 +58,7 @@ Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
  #include <asm/mipsregs.h>
  #include <asm/smp-ops.h>
  #include <asm/mips-cps.h>
-@@ -55,6 +57,8 @@
+@@ -54,6 +56,8 @@
  #define MT7621_GPIO_MODE_SDHCI_SHIFT	18
  #define MT7621_GPIO_MODE_SDHCI_GPIO	1
  
@@ -67,7 +67,7 @@ Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
  static struct rt2880_pmx_func uart1_grp[] =  { FUNC("uart1", 0, 1, 2) };
  static struct rt2880_pmx_func i2c_grp[] =  { FUNC("i2c", 0, 3, 2) };
  static struct rt2880_pmx_func uart3_grp[] = {
-@@ -139,6 +143,26 @@ static struct clk *__init mt7621_add_sys
+@@ -138,6 +142,26 @@ static struct clk *__init mt7621_add_sys
  	return clk;
  }
  
@@ -94,7 +94,7 @@ Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
  void __init ralink_clk_init(void)
  {
  	u32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac;
-@@ -292,10 +316,7 @@ void prom_soc_init(struct ralink_soc_inf
+@@ -277,10 +301,7 @@ void prom_soc_init(struct ralink_soc_inf
  		(rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
  		(rev & CHIP_REV_ECO_MASK));