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authorChristian Lamparter <chunkeey@gmail.com>2019-12-05 01:11:01 +0100
committerPetr Štetiar <ynezz@true.cz>2019-12-19 22:41:57 +0100
commit61505922dc0ff846e576f6fd5626e2d7b6f8c3e5 (patch)
tree9ba45f8cab96793ed118a17d70872e07b48771cd /target
parentafcb78f1035da7ca93b2afc9305aab18e930c43d (diff)
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ipq806x: convert ipq8064 dtsi interrupts
Convert hardcoded interrupts value to types defined in gci include file. Interrupts sets to 0 are converted to IRQ_TYPE_LEVEL_HIGH to fix kernel warning. Same fix has been applied to arm64 dts. https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1797143 https://patchwork.kernel.org/patch/10367453/ https://patchwork.kernel.org/patch/10315315/ Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Diffstat (limited to 'target')
-rw-r--r--target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064.dtsi60
1 files changed, 33 insertions, 27 deletions
diff --git a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064.dtsi b/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 54869de44f..bdeec812f6 100644
--- a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -433,7 +433,8 @@
cpu-pmu {
compatible = "qcom,krait-pmu";
- interrupts = <1 10 0x304>;
+ interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
};
reserved-memory {
@@ -533,7 +534,7 @@
clock-names = "ahbix-clk",
"mi2s-osr-clk",
"mi2s-bit-clk";
- interrupts = <0 85 1>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "lpass-irq-lpaif";
reg = <0x28100000 0x10000>;
reg-names = "lpass-lpaif";
@@ -558,9 +559,9 @@
reg = <0x108000 0x1000>;
qcom,ipc = <&l2cc 0x8 2>;
- interrupts = <0 19 0>,
- <0 21 0>,
- <0 22 0>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ack",
"err",
"wakeup";
@@ -625,7 +626,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
- interrupts = <0 16 0x4>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
pcie0_pins: pcie0_pinmux {
mux {
@@ -666,11 +667,16 @@
timer@200a000 {
compatible = "qcom,kpss-timer", "qcom,msm-timer";
- interrupts = <1 1 0x301>,
- <1 2 0x301>,
- <1 3 0x301>,
- <1 4 0x301>,
- <1 5 0x301>;
+ interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_EDGE_RISING)>;
reg = <0x0200a000 0x100>;
clock-frequency = <25000000>,
<32768>;
@@ -737,7 +743,7 @@
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x12490000 0x1000>,
<0x12480000 0x1000>;
- interrupts = <0 195 0x0>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
@@ -746,7 +752,7 @@
i2c@124a0000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x124a0000 0x1000>;
- interrupts = <0 196 0>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
clock-names = "core", "iface";
@@ -775,7 +781,7 @@
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x16340000 0x1000>,
<0x16300000 0x1000>;
- interrupts = <0 152 0x0>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
@@ -784,7 +790,7 @@
i2c@16380000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x16380000 0x1000>;
- interrupts = <0 153 0>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
clock-names = "core", "iface";
@@ -812,7 +818,7 @@
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x1a240000 0x1000>,
<0x1a200000 0x1000>;
- interrupts = <0 154 0x0>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
@@ -821,7 +827,7 @@
i2c@1a280000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x1a280000 0x1000>;
- interrupts = <0 155 0>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
clock-names = "core", "iface";
@@ -834,7 +840,7 @@
spi@1a280000 {
compatible = "qcom,spi-qup-v1.1.1";
reg = <0x1a280000 0x1000>;
- interrupts = <0 155 0>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
clock-names = "core", "iface";
@@ -862,7 +868,7 @@
ports-implemented = <0x1>;
- interrupts = <0 209 0x0>;
+ interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SFAB_SATA_S_H_CLK>,
<&gcc SATA_H_CLK>,
@@ -899,7 +905,7 @@
reg = <0x900000 0x3680>;
nvmem-cells = <&tsens_calib>, <&tsens_backup>;
nvmem-cell-names = "calib", "calib_backup";
- interrupts = <0 178 0>;
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
#thermal-sensor-cells = <1>;
};
@@ -969,7 +975,7 @@
clock-names = "ref";
#phy-cells = <0>;
};
-
+
ss_phy_1: ss_phy_1 {
compatible = "qcom,dwc3-ss-usb-phy";
regmap = <&usb3_1>;
@@ -1021,7 +1027,7 @@
ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
- interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
@@ -1075,7 +1081,7 @@
ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
- interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
@@ -1129,7 +1135,7 @@
ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
- interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
@@ -1169,7 +1175,7 @@
adm_dma: dma@18300000 {
compatible = "qcom,adm";
reg = <0x18300000 0x100000>;
- interrupts = <0 170 0>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
@@ -1325,7 +1331,7 @@
sdcc1bam:dma@12402000 {
compatible = "qcom,bam-v1.3.0";
reg = <0x12402000 0x8000>;
- interrupts = <0 98 0>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC1_H_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
@@ -1335,7 +1341,7 @@
sdcc3bam:dma@12182000 {
compatible = "qcom,bam-v1.3.0";
reg = <0x12182000 0x8000>;
- interrupts = <0 96 0>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC3_H_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-08 16:22:26 +0000