diff options
| author | Thomas Reifferscheid <thomas@reifferscheid.org> | 2017-04-07 12:25:10 +0200 |
|---|---|---|
| committer | John Crispin <john@phrozen.org> | 2017-04-24 09:19:49 +0200 |
| commit | 8db079a9ff1756059250b801617a20baba214684 (patch) | |
| tree | 8da1d6cdf06bc845bfe9b9a4f2679cd538a9df10 /target | |
| parent | 2db05cd199999d9a3670e5287d067bdab0431f1a (diff) | |
| download | upstream-8db079a9ff1756059250b801617a20baba214684.tar.gz upstream-8db079a9ff1756059250b801617a20baba214684.tar.bz2 upstream-8db079a9ff1756059250b801617a20baba214684.zip | |
ipq8064: Fix dwc3 module unloading
The patch follows the qualcomm code comments setting
SSUSB_CTRL_TEST_POWERDOWN to 0x1 and is testing and clearing the
bit during USB superspeed PHY init. According to Andy Gross it
needs to be BIT(26).
Signed-off-by: Thomas Reifferscheid <thomas@reifferscheid.org>
Acked-by: Andy Gross <andy.gross@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/linux/ipq806x/patches-4.9/0032-phy-add-qcom-dwc3-phy.patch | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/target/linux/ipq806x/patches-4.9/0032-phy-add-qcom-dwc3-phy.patch b/target/linux/ipq806x/patches-4.9/0032-phy-add-qcom-dwc3-phy.patch index 39e918f193..261836e2c3 100644 --- a/target/linux/ipq806x/patches-4.9/0032-phy-add-qcom-dwc3-phy.patch +++ b/target/linux/ipq806x/patches-4.9/0032-phy-add-qcom-dwc3-phy.patch @@ -39,7 +39,7 @@ Signed-off-by: Andy Gross <agross@codeaurora.org> +obj-$(CONFIG_PHY_QCOM_DWC3) += phy-qcom-dwc3.o --- /dev/null +++ b/drivers/phy/phy-qcom-dwc3.c -@@ -0,0 +1,484 @@ +@@ -0,0 +1,492 @@ +/* Copyright (c) 2014-2015, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify @@ -99,7 +99,7 @@ Signed-off-by: Andy Gross <agross@codeaurora.org> + +/* PHY_CTRL_REG */ +#define SSUSB_CTRL_REF_USE_PAD BIT(28) -+#define SSUSB_CTRL_TEST_POWERDOWN BIT(27) ++#define SSUSB_CTRL_TEST_POWERDOWN BIT(26) +#define SSUSB_CTRL_LANE0_PWR_PRESENT BIT(24) +#define SSUSB_CTRL_SS_PHY_EN BIT(8) +#define SSUSB_CTRL_SS_PHY_RESET BIT(7) @@ -331,6 +331,14 @@ Signed-off-by: Andy Gross <agross@codeaurora.org> + + /* reset phy */ + data = readl(phy_dwc3->base + SSUSB_PHY_CTRL_REG); ++ ++ /* Test and clear SSUSB_CTRL_TEST_POWERDOWN */ ++ if (data & SSUSB_CTRL_TEST_POWERDOWN) { ++ qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG, ++ SSUSB_CTRL_TEST_POWERDOWN, 0x0); ++ data = readl(phy_dwc3->base + SSUSB_PHY_CTRL_REG); ++ } ++ + writel(data | SSUSB_CTRL_SS_PHY_RESET, + phy_dwc3->base + SSUSB_PHY_CTRL_REG); + usleep_range(2000, 2200); @@ -420,7 +428,7 @@ Signed-off-by: Andy Gross <agross@codeaurora.org> + qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG, + SSUSB_CTRL_REF_USE_PAD, 0x0); + qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG, -+ SSUSB_CTRL_TEST_POWERDOWN, 0x0); ++ SSUSB_CTRL_TEST_POWERDOWN, SSUSB_CTRL_TEST_POWERDOWN); + + return 0; +} |