diff options
| author | Koen Vandeputte <koen.vandeputte@ncentric.com> | 2018-10-10 11:42:42 +0200 |
|---|---|---|
| committer | Koen Vandeputte <koen.vandeputte@ncentric.com> | 2018-10-10 15:12:01 +0200 |
| commit | 13f283198ef49dedd49c106176f80dfffa16c3a8 (patch) | |
| tree | 33f816b19644afca9c3798a1120007ff45441dde /target | |
| parent | 77d004de6d09edc6d8a5cf77471d52d4865ae577 (diff) | |
| download | upstream-13f283198ef49dedd49c106176f80dfffa16c3a8.tar.gz upstream-13f283198ef49dedd49c106176f80dfffa16c3a8.tar.bz2 upstream-13f283198ef49dedd49c106176f80dfffa16c3a8.zip | |
ar71xx: remove linux 4.9 support
Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
Diffstat (limited to 'target')
92 files changed, 0 insertions, 8105 deletions
diff --git a/target/linux/ar71xx/config-4.9 b/target/linux/ar71xx/config-4.9 deleted file mode 100644 index 8d25692ec8..0000000000 --- a/target/linux/ar71xx/config-4.9 +++ /dev/null @@ -1,484 +0,0 @@ -CONFIG_AG71XX=y -CONFIG_AG71XX_AR8216_SUPPORT=y -# CONFIG_AG71XX_DEBUG is not set -# CONFIG_AG71XX_DEBUG_FS is not set -CONFIG_AR8216_PHY=y -CONFIG_AR8216_PHY_LEDS=y -CONFIG_ARCH_BINFMT_ELF_STATE=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_ARCH_DISCARD_MEMBLOCK=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set -CONFIG_ARCH_HAS_RESET_CONTROLLER=y -# CONFIG_ARCH_HAS_SG_CHAIN is not set -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_USE_BUILTIN_BSWAP=y -CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y -CONFIG_AT803X_PHY=y -CONFIG_ATH79=y -# CONFIG_ATH79_DEV_AP9X_PCI is not set -# CONFIG_ATH79_DEV_DSA is not set -# CONFIG_ATH79_DEV_ETH is not set -# CONFIG_ATH79_DEV_GPIO_BUTTONS is not set -# CONFIG_ATH79_DEV_LEDS_GPIO is not set -# CONFIG_ATH79_DEV_M25P80 is not set -# CONFIG_ATH79_DEV_SPI is not set -# CONFIG_ATH79_DEV_USB is not set -# CONFIG_ATH79_MACH_A60 is not set -# CONFIG_ATH79_MACH_ALFA_AP120C is not set -# CONFIG_ATH79_MACH_ALFA_AP96 is not set -# CONFIG_ATH79_MACH_ALFA_NX is not set -# CONFIG_ATH79_MACH_ALL0258N is not set -# CONFIG_ATH79_MACH_ALL0315N is not set -# CONFIG_ATH79_MACH_ANTMINER_S1 is not set -# CONFIG_ATH79_MACH_ANTMINER_S3 is not set -# CONFIG_ATH79_MACH_ANTROUTER_R1 is not set -# CONFIG_ATH79_MACH_AP121 is not set -# CONFIG_ATH79_MACH_AP121F is not set -# CONFIG_ATH79_MACH_AP132 is not set -# CONFIG_ATH79_MACH_AP136 is not set -# CONFIG_ATH79_MACH_AP143 is not set -# CONFIG_ATH79_MACH_AP147 is not set -# CONFIG_ATH79_MACH_AP152 is not set -# CONFIG_ATH79_MACH_AP531B0 is not set -# CONFIG_ATH79_MACH_AP81 is not set -# CONFIG_ATH79_MACH_AP90Q is not set -# CONFIG_ATH79_MACH_AP91_5G is not set -# CONFIG_ATH79_MACH_AP96 is not set -# CONFIG_ATH79_MACH_ARCHER_C25_V1 is not set -# CONFIG_ATH79_MACH_ARCHER_C58_V1 is not set -# CONFIG_ATH79_MACH_ARCHER_C59_V1 is not set -# CONFIG_ATH79_MACH_ARCHER_C59_V2 is not set -# CONFIG_ATH79_MACH_ARCHER_C60_V1 is not set -# CONFIG_ATH79_MACH_ARCHER_C60_V2 is not set -# CONFIG_ATH79_MACH_ARCHER_C7 is not set -# CONFIG_ATH79_MACH_ARDUINO_YUN is not set -# CONFIG_ATH79_MACH_AW_NR580 is not set -# CONFIG_ATH79_MACH_BHR_4GRV2 is not set -# CONFIG_ATH79_MACH_BHU_BXU2000N2_A is not set -# CONFIG_ATH79_MACH_BSB is not set -# CONFIG_ATH79_MACH_C55 is not set -# CONFIG_ATH79_MACH_C60 is not set -# CONFIG_ATH79_MACH_CAP324 is not set -# CONFIG_ATH79_MACH_CAP4200AG is not set -# CONFIG_ATH79_MACH_CARAMBOLA2 is not set -# CONFIG_ATH79_MACH_CF_E316N_V2 is not set -# CONFIG_ATH79_MACH_CF_E320N_V2 is not set -# CONFIG_ATH79_MACH_CF_E355AC is not set -# CONFIG_ATH79_MACH_CF_E375AC is not set -# CONFIG_ATH79_MACH_CF_E380AC_V1 is not set -# CONFIG_ATH79_MACH_CF_E380AC_V2 is not set -# CONFIG_ATH79_MACH_CF_E520N is not set -# CONFIG_ATH79_MACH_CF_E530N is not set -# CONFIG_ATH79_MACH_CPE505N is not set -# CONFIG_ATH79_MACH_CPE510 is not set -# CONFIG_ATH79_MACH_CPE830 is not set -# CONFIG_ATH79_MACH_CPE870 is not set -# CONFIG_ATH79_MACH_CR3000 is not set -# CONFIG_ATH79_MACH_CR5000 is not set -# CONFIG_ATH79_MACH_DAP_1330_A1 is not set -# CONFIG_ATH79_MACH_DAP_2695_A1 is not set -# CONFIG_ATH79_MACH_DB120 is not set -# CONFIG_ATH79_MACH_DGL_5500_A1 is not set -# CONFIG_ATH79_MACH_DHP_1565_A1 is not set -# CONFIG_ATH79_MACH_DIR_505_A1 is not set -# CONFIG_ATH79_MACH_DIR_600_A1 is not set -# CONFIG_ATH79_MACH_DIR_615_C1 is not set -# CONFIG_ATH79_MACH_DIR_615_I1 is not set -# CONFIG_ATH79_MACH_DIR_825_B1 is not set -# CONFIG_ATH79_MACH_DIR_825_C1 is not set -# CONFIG_ATH79_MACH_DIR_869_A1 is not set -# CONFIG_ATH79_MACH_DLAN_HOTSPOT is not set -# CONFIG_ATH79_MACH_DLAN_PRO_1200_AC is not set -# CONFIG_ATH79_MACH_DLAN_PRO_500_WP is not set -# CONFIG_ATH79_MACH_DOMYWIFI_DW33D is not set -# CONFIG_ATH79_MACH_DR342 is not set -# CONFIG_ATH79_MACH_DR344 is not set -# CONFIG_ATH79_MACH_DR531 is not set -# CONFIG_ATH79_MACH_DRAGINO2 is not set -# CONFIG_ATH79_MACH_E1700AC_V2 is not set -# CONFIG_ATH79_MACH_E2100L is not set -# CONFIG_ATH79_MACH_E558_V2 is not set -# CONFIG_ATH79_MACH_E600G_V2 is not set -# CONFIG_ATH79_MACH_E750A_V4 is not set -# CONFIG_ATH79_MACH_E750G_V8 is not set -# CONFIG_ATH79_MACH_EAP120 is not set -# CONFIG_ATH79_MACH_EAP300V2 is not set -# CONFIG_ATH79_MACH_EAP7660D is not set -# CONFIG_ATH79_MACH_EL_M150 is not set -# CONFIG_ATH79_MACH_EL_MINI is not set -# CONFIG_ATH79_MACH_ENS202EXT is not set -# CONFIG_ATH79_MACH_EPG5000 is not set -# CONFIG_ATH79_MACH_ESR1750 is not set -# CONFIG_ATH79_MACH_ESR900 is not set -# CONFIG_ATH79_MACH_EW_BALIN is not set -# CONFIG_ATH79_MACH_EW_DORIN is not set -# CONFIG_ATH79_MACH_F9K1115V2 is not set -# CONFIG_ATH79_MACH_FRITZ300E is not set -# CONFIG_ATH79_MACH_FRITZ4020 is not set -# CONFIG_ATH79_MACH_FRITZ450E is not set -# CONFIG_ATH79_MACH_GL_AR150 is not set -# CONFIG_ATH79_MACH_GL_AR300 is not set -# CONFIG_ATH79_MACH_GL_AR300M is not set -# CONFIG_ATH79_MACH_GL_AR750 is not set -# CONFIG_ATH79_MACH_GL_AR750S is not set -# CONFIG_ATH79_MACH_GL_DOMINO is not set -# CONFIG_ATH79_MACH_GL_INET is not set -# CONFIG_ATH79_MACH_GL_MIFI is not set -# CONFIG_ATH79_MACH_GL_USB150 is not set -# CONFIG_ATH79_MACH_GS_OOLITE_V1 is not set -# CONFIG_ATH79_MACH_GS_OOLITE_V5_2 is not set -# CONFIG_ATH79_MACH_HIVEAP_121 is not set -# CONFIG_ATH79_MACH_HIWIFI_HC6361 is not set -# CONFIG_ATH79_MACH_HORNET_UB is not set -# CONFIG_ATH79_MACH_JA76PF is not set -# CONFIG_ATH79_MACH_JWAP003 is not set -# CONFIG_ATH79_MACH_JWAP230 is not set -# CONFIG_ATH79_MACH_KOALA is not set -# CONFIG_ATH79_MACH_LAN_TURTLE is not set -# CONFIG_ATH79_MACH_LIMA is not set -# CONFIG_ATH79_MACH_MC_MAC1200R is not set -# CONFIG_ATH79_MACH_MR12 is not set -# CONFIG_ATH79_MACH_MR16 is not set -# CONFIG_ATH79_MACH_MR1750 is not set -# CONFIG_ATH79_MACH_MR18 is not set -# CONFIG_ATH79_MACH_MR600 is not set -# CONFIG_ATH79_MACH_MR900 is not set -# CONFIG_ATH79_MACH_MYNET_N600 is not set -# CONFIG_ATH79_MACH_MYNET_N750 is not set -# CONFIG_ATH79_MACH_MYNET_REXT is not set -# CONFIG_ATH79_MACH_MZK_W04NU is not set -# CONFIG_ATH79_MACH_MZK_W300NH is not set -# CONFIG_ATH79_MACH_N5Q is not set -# CONFIG_ATH79_MACH_NBG460N is not set -# CONFIG_ATH79_MACH_NBG6716 is not set -# CONFIG_ATH79_MACH_OM2P is not set -# CONFIG_ATH79_MACH_OM5P is not set -# CONFIG_ATH79_MACH_OM5P_AC is not set -# CONFIG_ATH79_MACH_OM5P_ACv2 is not set -# CONFIG_ATH79_MACH_OMY_G1 is not set -# CONFIG_ATH79_MACH_OMY_X1 is not set -# CONFIG_ATH79_MACH_ONION_OMEGA is not set -# CONFIG_ATH79_MACH_PB42 is not set -# CONFIG_ATH79_MACH_PB44 is not set -# CONFIG_ATH79_MACH_PQI_AIR_PEN is not set -# CONFIG_ATH79_MACH_QIHOO_C301 is not set -# CONFIG_ATH79_MACH_R36A is not set -# CONFIG_ATH79_MACH_R602N is not set -# CONFIG_ATH79_MACH_R6100 is not set -# CONFIG_ATH79_MACH_RAMBUTAN is not set -# CONFIG_ATH79_MACH_RB2011 is not set -# CONFIG_ATH79_MACH_RB4XX is not set -# CONFIG_ATH79_MACH_RB750 is not set -# CONFIG_ATH79_MACH_RB91X is not set -# CONFIG_ATH79_MACH_RB922 is not set -# CONFIG_ATH79_MACH_RB95X is not set -# CONFIG_ATH79_MACH_RBSPI is not set -# CONFIG_ATH79_MACH_RBSXTLITE is not set -# CONFIG_ATH79_MACH_RE355 is not set -# CONFIG_ATH79_MACH_RE450 is not set -# CONFIG_ATH79_MACH_RME_EG200 is not set -# CONFIG_ATH79_MACH_RUT9XX is not set -# CONFIG_ATH79_MACH_RW2458N is not set -# CONFIG_ATH79_MACH_SC1750 is not set -# CONFIG_ATH79_MACH_SC300M is not set -# CONFIG_ATH79_MACH_SC450 is not set -# CONFIG_ATH79_MACH_SMART_300 is not set -# CONFIG_ATH79_MACH_SOM9331 is not set -# CONFIG_ATH79_MACH_SR3200 is not set -# CONFIG_ATH79_MACH_T830 is not set -# CONFIG_ATH79_MACH_TELLSTICK_ZNET_LITE is not set -# CONFIG_ATH79_MACH_TEW_632BRP is not set -# CONFIG_ATH79_MACH_TEW_673GRU is not set -# CONFIG_ATH79_MACH_TEW_712BR is not set -# CONFIG_ATH79_MACH_TEW_732BR is not set -# CONFIG_ATH79_MACH_TEW_823DRU is not set -# CONFIG_ATH79_MACH_TL_MR11U is not set -# CONFIG_ATH79_MACH_TL_MR13U is not set -# CONFIG_ATH79_MACH_TL_MR3020 is not set -# CONFIG_ATH79_MACH_TL_MR3X20 is not set -# CONFIG_ATH79_MACH_TL_MR6400 is not set -# CONFIG_ATH79_MACH_TL_WA701ND_V2 is not set -# CONFIG_ATH79_MACH_TL_WA7210N_V2 is not set -# CONFIG_ATH79_MACH_TL_WA801ND_V3 is not set -# CONFIG_ATH79_MACH_TL_WA830RE_V2 is not set -# CONFIG_ATH79_MACH_TL_WA850RE_V2 is not set -# CONFIG_ATH79_MACH_TL_WA855RE_V1 is not set -# CONFIG_ATH79_MACH_TL_WA901ND is not set -# CONFIG_ATH79_MACH_TL_WA901ND_V2 is not set -# CONFIG_ATH79_MACH_TL_WA901ND_V4 is not set -# CONFIG_ATH79_MACH_TL_WAX50RE is not set -# CONFIG_ATH79_MACH_TL_WDR3320_V2 is not set -# CONFIG_ATH79_MACH_TL_WDR3500 is not set -# CONFIG_ATH79_MACH_TL_WDR4300 is not set -# CONFIG_ATH79_MACH_TL_WDR6500_V2 is not set -# CONFIG_ATH79_MACH_TL_WPA8630 is not set -# CONFIG_ATH79_MACH_TL_WR1041N_V2 is not set -# CONFIG_ATH79_MACH_TL_WR1043ND is not set -# CONFIG_ATH79_MACH_TL_WR1043ND_V2 is not set -# CONFIG_ATH79_MACH_TL_WR1043ND_V4 is not set -# CONFIG_ATH79_MACH_TL_WR1043N_V5 is not set -# CONFIG_ATH79_MACH_TL_WR2543N is not set -# CONFIG_ATH79_MACH_TL_WR703N is not set -# CONFIG_ATH79_MACH_TL_WR720N_V3 is not set -# CONFIG_ATH79_MACH_TL_WR741ND is not set -# CONFIG_ATH79_MACH_TL_WR741ND_V4 is not set -# CONFIG_ATH79_MACH_TL_WR802N_V1 is not set -# CONFIG_ATH79_MACH_TL_WR802N_V2 is not set -# CONFIG_ATH79_MACH_TL_WR810N is not set -# CONFIG_ATH79_MACH_TL_WR810N_V2 is not set -# CONFIG_ATH79_MACH_TL_WR840N_V2 is not set -# CONFIG_ATH79_MACH_TL_WR841N_V1 is not set -# CONFIG_ATH79_MACH_TL_WR841N_V8 is not set -# CONFIG_ATH79_MACH_TL_WR841N_V9 is not set -# CONFIG_ATH79_MACH_TL_WR902AC_V1 is not set -# CONFIG_ATH79_MACH_TL_WR940N_V4 is not set -# CONFIG_ATH79_MACH_TL_WR941ND is not set -# CONFIG_ATH79_MACH_TL_WR941ND_V6 is not set -# CONFIG_ATH79_MACH_TL_WR942N_V1 is not set -# CONFIG_ATH79_MACH_TS_D084 is not set -# CONFIG_ATH79_MACH_TUBE2H is not set -# CONFIG_ATH79_MACH_UBNT is not set -# CONFIG_ATH79_MACH_UBNT_UNIFIAC is not set -# CONFIG_ATH79_MACH_UBNT_XM is not set -# CONFIG_ATH79_MACH_WAM250 is not set -# CONFIG_ATH79_MACH_WEIO is not set -# CONFIG_ATH79_MACH_WHR_HP_G300N is not set -# CONFIG_ATH79_MACH_WI2A_AC200I is not set -# CONFIG_ATH79_MACH_WIFI_PINEAPPLE_NANO is not set -# CONFIG_ATH79_MACH_WLAE_AG300N is not set -# CONFIG_ATH79_MACH_WLR8100 is not set -# CONFIG_ATH79_MACH_WNDAP360 is not set -# CONFIG_ATH79_MACH_WNDR3700 is not set -# CONFIG_ATH79_MACH_WNDR4300 is not set -# CONFIG_ATH79_MACH_WNR2000 is not set -# CONFIG_ATH79_MACH_WNR2000_V3 is not set -# CONFIG_ATH79_MACH_WNR2000_V4 is not set -# CONFIG_ATH79_MACH_WNR2200 is not set -# CONFIG_ATH79_MACH_WP543 is not set -# CONFIG_ATH79_MACH_WPE72 is not set -# CONFIG_ATH79_MACH_WPJ342 is not set -# CONFIG_ATH79_MACH_WPJ344 is not set -# CONFIG_ATH79_MACH_WPJ531 is not set -# CONFIG_ATH79_MACH_WPJ558 is not set -# CONFIG_ATH79_MACH_WPJ563 is not set -# CONFIG_ATH79_MACH_WRT160NL is not set -# CONFIG_ATH79_MACH_WRT400N is not set -# CONFIG_ATH79_MACH_WRTNODE2Q is not set -# CONFIG_ATH79_MACH_WZR_450HP2 is not set -# CONFIG_ATH79_MACH_WZR_HP_AG300H is not set -# CONFIG_ATH79_MACH_WZR_HP_G300NH is not set -# CONFIG_ATH79_MACH_WZR_HP_G300NH2 is not set -# CONFIG_ATH79_MACH_WZR_HP_G450H is not set -# CONFIG_ATH79_MACH_XD3200 is not set -# CONFIG_ATH79_MACH_Z1 is not set -# CONFIG_ATH79_MACH_ZBT_WE1526 is not set -# CONFIG_ATH79_MACH_ZCN_1523H is not set -# CONFIG_ATH79_NVRAM is not set -# CONFIG_ATH79_PCI_ATH9K_FIXUP is not set -# CONFIG_ATH79_ROUTERBOOT is not set -CONFIG_ATH79_WDT=y -CONFIG_CEVT_R4K=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs noinitrd" -CONFIG_CMDLINE_BOOL=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_COMMON_CLK=y -CONFIG_CPU_BIG_ENDIAN=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_MIPS32=y -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_R4K_FPU=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_WORKQUEUE=y -CONFIG_CSRC_R4K=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_EARLY_PRINTK=y -CONFIG_ETHERNET_PACKET_MANGLE=y -CONFIG_FIXED_PHY=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_IO=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIOLIB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_74X164=y -CONFIG_GPIO_ATH79=y -CONFIG_GPIO_GENERIC=y -# CONFIG_GPIO_LATCH is not set -CONFIG_GPIO_NXP_74HC153=y -CONFIG_GPIO_PCF857X=y -CONFIG_GPIO_SYSFS=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set -# CONFIG_HAVE_ARCH_BITREVERSE is not set -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set -CONFIG_HAVE_CBPF_JIT=y -CONFIG_HAVE_CC_STACKPROTECTOR=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_CLK_PREPARE=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_HAVE_DEBUG_KMEMLEAK=y -CONFIG_HAVE_DEBUG_STACKOVERFLOW=y -CONFIG_HAVE_DMA_API_DEBUG=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_HAVE_IDE=y -CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_KVM=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_HAVE_MEMBLOCK=y -CONFIG_HAVE_MEMBLOCK_NODE_MAP=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_HAVE_NET_DSA=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_HZ_PERIODIC=y -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_GPIO=y -CONFIG_IMAGE_CMDLINE_HACK=y -CONFIG_INITRAMFS_ROOT_GID=0 -CONFIG_INITRAMFS_ROOT_UID=0 -CONFIG_INITRAMFS_SOURCE="../../root" -CONFIG_INTEL_XWAY_PHY=y -CONFIG_IP17XX_PHY=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -CONFIG_LEDS_GPIO=y -CONFIG_MARVELL_PHY=y -CONFIG_MDIO_BITBANG=y -CONFIG_MDIO_BOARDINFO=y -CONFIG_MDIO_GPIO=y -CONFIG_MICREL_PHY=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CLOCK_VSYSCALL=y -# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set -CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y -# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set -CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_MIPS_MACHINE=y -CONFIG_MIPS_SPRAM=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -# CONFIG_MTD_CFI_I2 is not set -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CYBERTAN_PARTS=y -CONFIG_MTD_M25P80=y -# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set -CONFIG_MTD_MYLOADER_PARTS=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-2 -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_EVA_FW=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_LZMA_FW=y -CONFIG_MTD_SPLIT_MINOR_FW=y -CONFIG_MTD_SPLIT_SEAMA_FW=y -CONFIG_MTD_SPLIT_TPLINK_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_MTD_SPLIT_WRGG_FW=y -CONFIG_MTD_TPLINK_PARTS=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MV88E6060=y -CONFIG_NET_DSA_MV88E6063=y -CONFIG_NET_DSA_TAG_TRAILER=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -# CONFIG_NO_IOPORT_MAP is not set -# CONFIG_OF is not set -# CONFIG_PCI_AR724X is not set -CONFIG_PCI_DRIVERS_LEGACY=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_RATIONAL=y -# CONFIG_RCU_STALL_COMMON is not set -CONFIG_RTL8306_PHY=y -CONFIG_RTL8366RB_PHY=y -CONFIG_RTL8366S_PHY=y -CONFIG_RTL8366_SMI=y -CONFIG_RTL8367_PHY=y -# CONFIG_SCHED_INFO is not set -# CONFIG_SCSI_DMA is not set -# CONFIG_SERIAL_8250_FSL is not set -CONFIG_SERIAL_8250_NR_UARTS=1 -CONFIG_SERIAL_8250_RUNTIME_UARTS=1 -# CONFIG_SOC_AR71XX is not set -# CONFIG_SOC_AR724X is not set -# CONFIG_SOC_AR913X is not set -# CONFIG_SOC_AR933X is not set -# CONFIG_SOC_AR934X is not set -# CONFIG_SOC_QCA953X is not set -# CONFIG_SOC_QCA955X is not set -# CONFIG_SOC_QCA956X is not set -CONFIG_SPI=y -CONFIG_SPI_ATH79=y -CONFIG_SPI_BITBANG=y -CONFIG_SPI_GPIO=y -CONFIG_SPI_MASTER=y -# CONFIG_SPI_RB4XX is not set -# CONFIG_SPI_VSC7385 is not set -CONFIG_SRCU=y -CONFIG_SWCONFIG=y -CONFIG_SWCONFIG_LEDS=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_SYS_SUPPORTS_ZBOOT=y -CONFIG_SYS_SUPPORTS_ZBOOT_UART_PROM=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_USB_SUPPORT=y diff --git a/target/linux/ar71xx/patches-4.9/001-spi-cs-gpio.patch b/target/linux/ar71xx/patches-4.9/001-spi-cs-gpio.patch deleted file mode 100644 index 7a0b669e43..0000000000 --- a/target/linux/ar71xx/patches-4.9/001-spi-cs-gpio.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h -+++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h -@@ -14,6 +14,7 @@ - struct ath79_spi_platform_data { - unsigned bus_num; - unsigned num_chipselect; -+ int *cs_gpios; - }; - - #endif /* _ATH79_SPI_PLATFORM_H */ ---- a/drivers/spi/spi-ath79.c -+++ b/drivers/spi/spi-ath79.c -@@ -231,6 +231,7 @@ static int ath79_spi_probe(struct platfo - if (pdata) { - master->bus_num = pdata->bus_num; - master->num_chipselect = pdata->num_chipselect; -+ master->cs_gpios = pdata->cs_gpios; - } - - sp->bitbang.master = master; diff --git a/target/linux/ar71xx/patches-4.9/002-add_back_gpio_function_select.patch b/target/linux/ar71xx/patches-4.9/002-add_back_gpio_function_select.patch deleted file mode 100644 index 5b26a640eb..0000000000 --- a/target/linux/ar71xx/patches-4.9/002-add_back_gpio_function_select.patch +++ /dev/null @@ -1,92 +0,0 @@ ---- /dev/null -+++ b/arch/mips/ath79/gpio.c -@@ -0,0 +1,59 @@ -+/* -+ * Atheros AR71XX/AR724X/AR913X GPIO API support -+ * -+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> -+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> -+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> -+ * -+ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+#include <linux/kernel.h> -+#include <linux/module.h> -+#include <linux/io.h> -+#include <linux/gpio.h> -+#include <asm/mach-ath79/ar71xx_regs.h> -+#include <asm/mach-ath79/ath79.h> -+#include "common.h" -+ -+void __iomem *ath79_gpio_base; -+EXPORT_SYMBOL_GPL(ath79_gpio_base); -+ -+static void __iomem *ath79_gpio_get_function_reg(void) -+{ -+ u32 reg = 0; -+ -+ if (soc_is_ar71xx() || -+ soc_is_ar724x() || -+ soc_is_ar913x() || -+ soc_is_ar933x()) -+ reg = AR71XX_GPIO_REG_FUNC; -+ else if (soc_is_ar934x()) -+ reg = AR934X_GPIO_REG_FUNC; -+ else -+ BUG(); -+ -+ return ath79_gpio_base + reg; -+} -+ -+void ath79_gpio_function_setup(u32 set, u32 clear) -+{ -+ void __iomem *reg = ath79_gpio_get_function_reg(); -+ -+ __raw_writel((__raw_readl(reg) & ~clear) | set, reg); -+ /* flush write */ -+ __raw_readl(reg); -+} -+ -+void ath79_gpio_function_enable(u32 mask) -+{ -+ ath79_gpio_function_setup(mask, 0); -+} -+ -+void ath79_gpio_function_disable(u32 mask) -+{ -+ ath79_gpio_function_setup(0, mask); -+} ---- a/arch/mips/include/asm/mach-ath79/ath79.h -+++ b/arch/mips/include/asm/mach-ath79/ath79.h -@@ -118,6 +118,7 @@ static inline int soc_is_qca955x(void) - void ath79_ddr_wb_flush(unsigned int reg); - void ath79_ddr_set_pci_windows(void); - -+extern void __iomem *ath79_gpio_base; - extern void __iomem *ath79_pll_base; - extern void __iomem *ath79_reset_base; - ---- a/arch/mips/ath79/dev-common.c -+++ b/arch/mips/ath79/dev-common.c -@@ -156,4 +156,5 @@ void __init ath79_gpio_init(void) - } - - platform_device_register(&ath79_gpio_device); -+ ath79_gpio_base = ioremap(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); - } ---- a/arch/mips/ath79/common.h -+++ b/arch/mips/ath79/common.h -@@ -24,6 +24,9 @@ unsigned long ath79_get_sys_clk_rate(con - - void ath79_ddr_ctrl_init(void); - -+void ath79_gpio_function_enable(u32 mask); -+void ath79_gpio_function_disable(u32 mask); -+void ath79_gpio_function_setup(u32 set, u32 clear); - void ath79_gpio_init(void); - - #endif /* __ATH79_COMMON_H */ diff --git a/target/linux/ar71xx/patches-4.9/004-register_gpio_driver_earlier.patch b/target/linux/ar71xx/patches-4.9/004-register_gpio_driver_earlier.patch deleted file mode 100644 index cc30e2d91e..0000000000 --- a/target/linux/ar71xx/patches-4.9/004-register_gpio_driver_earlier.patch +++ /dev/null @@ -1,18 +0,0 @@ -HACK: register the GPIO driver earlier to ensure that gpio_request calls -from mach files succeed. - ---- a/drivers/gpio/gpio-ath79.c -+++ b/drivers/gpio/gpio-ath79.c -@@ -322,7 +322,11 @@ static struct platform_driver ath79_gpio - .remove = ath79_gpio_remove, - }; - --module_platform_driver(ath79_gpio_driver); -+static int __init ath79_gpio_init(void) -+{ -+ return platform_driver_register(&ath79_gpio_driver); -+} -+postcore_initcall(ath79_gpio_init); - - MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X GPIO API support"); - MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ar71xx/patches-4.9/100-MIPS-ath79-Avoid-using-unitialized-reg-variable.patch b/target/linux/ar71xx/patches-4.9/100-MIPS-ath79-Avoid-using-unitialized-reg-variable.patch deleted file mode 100644 index 8d5b089986..0000000000 --- a/target/linux/ar71xx/patches-4.9/100-MIPS-ath79-Avoid-using-unitialized-reg-variable.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 8b7a76e72fc819753878cd5684e243f33f847c79 Mon Sep 17 00:00:00 2001 -From: Markos Chandras <markos.chandras@imgtec.com> -Date: Wed, 21 Aug 2013 11:47:22 +0100 -Subject: [PATCH] MIPS: ath79: Avoid using unitialized 'reg' variable - -Fixes the following build error: -arch/mips/include/asm/mach-ath79/ath79.h:139:20: error: 'reg' may be used -uninitialized in this function [-Werror=maybe-uninitialized] -arch/mips/ath79/common.c:62:6: note: 'reg' was declared here -In file included from arch/mips/ath79/common.c:20:0: -arch/mips/ath79/common.c: In function 'ath79_device_reset_clear': -arch/mips/include/asm/mach-ath79/ath79.h:139:20: -error: 'reg' may be used uninitialized in this function -[-Werror=maybe-uninitialized] -arch/mips/ath79/common.c:90:6: note: 'reg' was declared here - -Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> -Acked-by: Gabor Juhos <juhosg@openwrt.org> ---- - arch/mips/ath79/common.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/mips/ath79/common.c -+++ b/arch/mips/ath79/common.c -@@ -106,7 +106,7 @@ void ath79_device_reset_set(u32 mask) - else if (soc_is_qca955x()) - reg = QCA955X_RESET_REG_RESET_MODULE; - else -- BUG(); -+ panic("Reset register not defined for this SOC"); - - spin_lock_irqsave(&ath79_device_reset_lock, flags); - t = ath79_reset_rr(reg); -@@ -134,7 +134,7 @@ void ath79_device_reset_clear(u32 mask) - else if (soc_is_qca955x()) - reg = QCA955X_RESET_REG_RESET_MODULE; - else -- BUG(); -+ panic("Reset register not defined for this SOC"); - - spin_lock_irqsave(&ath79_device_reset_lock, flags); - t = ath79_reset_rr(reg); diff --git a/target/linux/ar71xx/patches-4.9/104-spi-spi-ath79-support-multiple-internal-chip-select-.patch b/target/linux/ar71xx/patches-4.9/104-spi-spi-ath79-support-multiple-internal-chip-select-.patch deleted file mode 100644 index 3c355cd21c..0000000000 --- a/target/linux/ar71xx/patches-4.9/104-spi-spi-ath79-support-multiple-internal-chip-select-.patch +++ /dev/null @@ -1,70 +0,0 @@ -From: Felix Fietkau <nbd@nbd.name> -Date: Fri, 9 Dec 2016 20:09:16 +0100 -Subject: [PATCH] spi: spi-ath79: support multiple internal chip select - lines - -Several devices with multiple flash chips use the internal chip select -lines. Don't assume that chip select 1 and above are GPIO lines. - -Signed-off-by: Felix Fietkau <nbd@nbd.name> ---- - ---- a/drivers/spi/spi-ath79.c -+++ b/drivers/spi/spi-ath79.c -@@ -78,14 +78,16 @@ static void ath79_spi_chipselect(struct - ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); - } - -- if (spi->chip_select) { -+ if (gpio_is_valid(spi->cs_gpio)) { - /* SPI is normally active-low */ - gpio_set_value(spi->cs_gpio, cs_high); - } else { -+ u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select); -+ - if (cs_high) -- sp->ioc_base |= AR71XX_SPI_IOC_CS0; -+ sp->ioc_base |= cs_bit; - else -- sp->ioc_base &= ~AR71XX_SPI_IOC_CS0; -+ sp->ioc_base &= ~cs_bit; - - ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); - } -@@ -118,11 +120,8 @@ static int ath79_spi_setup_cs(struct spi - struct ath79_spi *sp = ath79_spidev_to_sp(spi); - int status; - -- if (spi->chip_select && !gpio_is_valid(spi->cs_gpio)) -- return -EINVAL; -- - status = 0; -- if (spi->chip_select) { -+ if (gpio_is_valid(spi->cs_gpio)) { - unsigned long flags; - - flags = GPIOF_DIR_OUT; -@@ -134,10 +133,12 @@ static int ath79_spi_setup_cs(struct spi - status = gpio_request_one(spi->cs_gpio, flags, - dev_name(&spi->dev)); - } else { -+ u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select); -+ - if (spi->mode & SPI_CS_HIGH) -- sp->ioc_base &= ~AR71XX_SPI_IOC_CS0; -+ sp->ioc_base &= ~cs_bit; - else -- sp->ioc_base |= AR71XX_SPI_IOC_CS0; -+ sp->ioc_base |= cs_bit; - - ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); - } -@@ -147,7 +148,7 @@ static int ath79_spi_setup_cs(struct spi - - static void ath79_spi_cleanup_cs(struct spi_device *spi) - { -- if (spi->chip_select) { -+ if (gpio_is_valid(spi->cs_gpio)) { - gpio_free(spi->cs_gpio); - } - } diff --git a/target/linux/ar71xx/patches-4.9/105-spi-spi-ath79-use-gpio_set_value_cansleep-for-GPIO-c.patch b/target/linux/ar71xx/patches-4.9/105-spi-spi-ath79-use-gpio_set_value_cansleep-for-GPIO-c.patch deleted file mode 100644 index 11b6a83104..0000000000 --- a/target/linux/ar71xx/patches-4.9/105-spi-spi-ath79-use-gpio_set_value_cansleep-for-GPIO-c.patch +++ /dev/null @@ -1,19 +0,0 @@ -From: Felix Fietkau <nbd@nbd.name> -Date: Fri, 9 Dec 2016 20:11:35 +0100 -Subject: [PATCH] spi: spi-ath79: use gpio_set_value_cansleep for GPIO chip - select - -Signed-off-by: Felix Fietkau <nbd@nbd.name> ---- - ---- a/drivers/spi/spi-ath79.c -+++ b/drivers/spi/spi-ath79.c -@@ -80,7 +80,7 @@ static void ath79_spi_chipselect(struct - - if (gpio_is_valid(spi->cs_gpio)) { - /* SPI is normally active-low */ -- gpio_set_value(spi->cs_gpio, cs_high); -+ gpio_set_value_cansleep(spi->cs_gpio, cs_high); - } else { - u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select); - diff --git a/target/linux/ar71xx/patches-4.9/106-02-MIPS-ath79-do-AR724x-PCIe-root-complex-init.patch b/target/linux/ar71xx/patches-4.9/106-02-MIPS-ath79-do-AR724x-PCIe-root-complex-init.patch deleted file mode 100644 index 3af99bf3b5..0000000000 --- a/target/linux/ar71xx/patches-4.9/106-02-MIPS-ath79-do-AR724x-PCIe-root-complex-init.patch +++ /dev/null @@ -1,113 +0,0 @@ -From 460f382c278fe66059a773c41cbcd0db86d53983 Mon Sep 17 00:00:00 2001 -From: Mathias Kresin <dev@kresin.me> -Date: Thu, 13 Apr 2017 09:47:42 +0200 -Subject: [PATCH] MIPS: pci-ar724x: get PCIe controller out of reset - -The ar724x pci driver expects the PCIe controller to be brought out of -reset by the bootloader. - -At least the AVM Fritz 300E bootloader doesn't take care of releasing -the different PCIe controller related resets which causes an endless -hang as soon as either the PCIE Reset register (0x180f0018) or the PCI -Application Control register (0x180f0000) is read from. - -Do the full "PCIE Root Complex Initialization Sequence" if the PCIe -host controller is still in reset during probing. - -The QCA u-boot sleeps 10ms after the PCIE Application Control bit is -set to ready. It has been shown that 10ms might not be enough time if -PCIe should be used right after setting the bit. During my tests it -took up to 20ms till the link was up. Giving the link up to 100ms -should work for all cases. - -Signed-off-by: Mathias Kresin <dev@kresin.me> ---- - arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 3 ++ - arch/mips/pci/pci-ar724x.c | 42 ++++++++++++++++++++++++++ - 2 files changed, 45 insertions(+) - ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -169,6 +169,9 @@ - #define AR724X_PLL_REG_CPU_CONFIG 0x00 - #define AR724X_PLL_REG_PCIE_CONFIG 0x10 - -+#define AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS BIT(16) -+#define AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET BIT(25) -+ - #define AR724X_PLL_FB_SHIFT 0 - #define AR724X_PLL_FB_MASK 0x3ff - #define AR724X_PLL_REF_DIV_SHIFT 10 ---- a/arch/mips/pci/pci-ar724x.c -+++ b/arch/mips/pci/pci-ar724x.c -@@ -12,14 +12,18 @@ - #include <linux/irq.h> - #include <linux/pci.h> - #include <linux/init.h> -+#include <linux/delay.h> - #include <linux/platform_device.h> - #include <asm/mach-ath79/ath79.h> - #include <asm/mach-ath79/ar71xx_regs.h> - -+#define AR724X_PCI_REG_APP 0x0 - #define AR724X_PCI_REG_RESET 0x18 - #define AR724X_PCI_REG_INT_STATUS 0x4c - #define AR724X_PCI_REG_INT_MASK 0x50 - -+#define AR724X_PCI_APP_LTSSM_ENABLE BIT(0) -+ - #define AR724X_PCI_RESET_LINK_UP BIT(0) - - #define AR724X_PCI_INT_DEV0 BIT(14) -@@ -325,6 +329,37 @@ static void ar724x_pci_irq_init(struct a - apc); - } - -+static void ar724x_pci_hw_init(struct ar724x_pci_controller *apc) -+{ -+ u32 ppl, app; -+ int wait = 0; -+ -+ /* deassert PCIe host controller and PCIe PHY reset */ -+ ath79_device_reset_clear(AR724X_RESET_PCIE); -+ ath79_device_reset_clear(AR724X_RESET_PCIE_PHY); -+ -+ /* remove the reset of the PCIE PLL */ -+ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG); -+ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET; -+ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl); -+ -+ /* deassert bypass for the PCIE PLL */ -+ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG); -+ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS; -+ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl); -+ -+ /* set PCIE Application Control to ready */ -+ app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP); -+ app |= AR724X_PCI_APP_LTSSM_ENABLE; -+ __raw_writel(app, apc->ctrl_base + AR724X_PCI_REG_APP); -+ -+ /* wait up to 100ms for PHY link up */ -+ do { -+ mdelay(10); -+ wait++; -+ } while (wait < 10 && !ar724x_pci_check_link(apc)); -+} -+ - static int ar724x_pci_probe(struct platform_device *pdev) - { - struct ar724x_pci_controller *apc; -@@ -383,6 +418,13 @@ static int ar724x_pci_probe(struct platf - apc->pci_controller.io_resource = &apc->io_res; - apc->pci_controller.mem_resource = &apc->mem_res; - -+ /* -+ * Do the full PCIE Root Complex Initialization Sequence if the PCIe -+ * host controller is in reset. -+ */ -+ if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE) -+ ar724x_pci_hw_init(apc); -+ - apc->link_up = ar724x_pci_check_link(apc); - if (!apc->link_up) - dev_warn(&pdev->dev, "PCIe link is down\n"); diff --git a/target/linux/ar71xx/patches-4.9/200-MIPS-ath79-fix-ar933x-wmac-reset.patch b/target/linux/ar71xx/patches-4.9/200-MIPS-ath79-fix-ar933x-wmac-reset.patch deleted file mode 100644 index b7ae0ce649..0000000000 --- a/target/linux/ar71xx/patches-4.9/200-MIPS-ath79-fix-ar933x-wmac-reset.patch +++ /dev/null @@ -1,30 +0,0 @@ ---- a/arch/mips/ath79/dev-wmac.c -+++ b/arch/mips/ath79/dev-wmac.c -@@ -62,10 +62,26 @@ static void __init ar913x_wmac_setup(voi - - static int ar933x_wmac_reset(void) - { -+ int retries = 20; -+ - ath79_device_reset_set(AR933X_RESET_WMAC); - ath79_device_reset_clear(AR933X_RESET_WMAC); - -- return 0; -+ while (1) { -+ u32 bootstrap; -+ -+ bootstrap = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); -+ if ((bootstrap & AR933X_BOOTSTRAP_EEPBUSY) == 0) -+ return 0; -+ -+ if (retries-- == 0) -+ break; -+ -+ udelay(10000); -+ } -+ -+ pr_err("ar933x: WMAC reset timed out"); -+ return -ETIMEDOUT; - } - - static int ar933x_r1_get_wmac_revision(void) diff --git a/target/linux/ar71xx/patches-4.9/201-ar913x_wmac_external_reset.patch b/target/linux/ar71xx/patches-4.9/201-ar913x_wmac_external_reset.patch deleted file mode 100644 index 9b704a3c47..0000000000 --- a/target/linux/ar71xx/patches-4.9/201-ar913x_wmac_external_reset.patch +++ /dev/null @@ -1,31 +0,0 @@ ---- a/arch/mips/ath79/dev-wmac.c -+++ b/arch/mips/ath79/dev-wmac.c -@@ -44,7 +44,7 @@ static struct platform_device ath79_wmac - }, - }; - --static void __init ar913x_wmac_setup(void) -+static int ar913x_wmac_reset(void) - { - /* reset the WMAC */ - ath79_device_reset_set(AR913X_RESET_AMBA2WMAC); -@@ -53,10 +53,19 @@ static void __init ar913x_wmac_setup(voi - ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC); - mdelay(10); - -+ return 0; -+} -+ -+static void __init ar913x_wmac_setup(void) -+{ -+ ar913x_wmac_reset(); -+ - ath79_wmac_resources[0].start = AR913X_WMAC_BASE; - ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1; - ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2); - ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2); -+ -+ ath79_wmac_data.external_reset = ar913x_wmac_reset; - } - - diff --git a/target/linux/ar71xx/patches-4.9/202-MIPS-ath79-ar934x-wmac-revision.patch b/target/linux/ar71xx/patches-4.9/202-MIPS-ath79-ar934x-wmac-revision.patch deleted file mode 100644 index 0f8016f847..0000000000 --- a/target/linux/ar71xx/patches-4.9/202-MIPS-ath79-ar934x-wmac-revision.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/mips/ath79/dev-wmac.c -+++ b/arch/mips/ath79/dev-wmac.c -@@ -139,6 +139,8 @@ static void ar934x_wmac_setup(void) - ath79_wmac_data.is_clk_25mhz = false; - else - ath79_wmac_data.is_clk_25mhz = true; -+ -+ ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision; - } - - static void qca955x_wmac_setup(void) diff --git a/target/linux/ar71xx/patches-4.9/220-add_cpu_feature_overrides.patch b/target/linux/ar71xx/patches-4.9/220-add_cpu_feature_overrides.patch deleted file mode 100644 index d925f92624..0000000000 --- a/target/linux/ar71xx/patches-4.9/220-add_cpu_feature_overrides.patch +++ /dev/null @@ -1,28 +0,0 @@ ---- a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h -+++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h -@@ -36,6 +36,7 @@ - #define cpu_has_mdmx 0 - #define cpu_has_mips3d 0 - #define cpu_has_smartmips 0 -+#define cpu_has_rixi 0 - - #define cpu_has_mips32r1 1 - #define cpu_has_mips32r2 1 -@@ -43,6 +44,7 @@ - #define cpu_has_mips64r2 0 - - #define cpu_has_mipsmt 0 -+#define cpu_has_userlocal 0 - - #define cpu_has_64bits 0 - #define cpu_has_64bit_zero_reg 0 -@@ -51,5 +53,9 @@ - - #define cpu_dcache_line_size() 32 - #define cpu_icache_line_size() 32 -+#define cpu_has_vtag_icache 0 -+#define cpu_has_dc_aliases 1 -+#define cpu_has_ic_fills_f_dc 0 -+#define cpu_has_pindexed_dcache 0 - - #endif /* __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H */ diff --git a/target/linux/ar71xx/patches-4.9/300-MIPS-add-MIPS_MACHINE_NONAME-macro.patch b/target/linux/ar71xx/patches-4.9/300-MIPS-add-MIPS_MACHINE_NONAME-macro.patch deleted file mode 100644 index 0bc64b7a17..0000000000 --- a/target/linux/ar71xx/patches-4.9/300-MIPS-add-MIPS_MACHINE_NONAME-macro.patch +++ /dev/null @@ -1,21 +0,0 @@ ---- a/arch/mips/include/asm/mips_machine.h -+++ b/arch/mips/include/asm/mips_machine.h -@@ -36,6 +36,18 @@ static struct mips_machine machine_##_ty - .mach_setup = _setup, \ - }; - -+#define MIPS_MACHINE_NONAME(_type, _id, _setup) \ -+static const char machine_id_##_type[] __initconst \ -+ __aligned(1) = _id; \ -+static struct mips_machine machine_##_type \ -+ __used __section(.mips.machines.init) = \ -+{ \ -+ .mach_type = _type, \ -+ .mach_id = machine_id_##_type, \ -+ .mach_name = NULL, \ -+ .mach_setup = _setup, \ -+}; -+ - extern long __mips_machines_start; - extern long __mips_machines_end; - diff --git a/target/linux/ar71xx/patches-4.9/310-lib-add-rle-decompression.patch b/target/linux/ar71xx/patches-4.9/310-lib-add-rle-decompression.patch deleted file mode 100644 index d8480125a9..0000000000 --- a/target/linux/ar71xx/patches-4.9/310-lib-add-rle-decompression.patch +++ /dev/null @@ -1,124 +0,0 @@ ---- a/lib/Kconfig -+++ b/lib/Kconfig -@@ -247,6 +247,9 @@ config LZMA_COMPRESS - config LZMA_DECOMPRESS - tristate - -+config RLE_DECOMPRESS -+ tristate -+ - # - # These all provide a common interface (hence the apparent duplication with - # ZLIB_INFLATE; DECOMPRESS_GZIP is just a wrapper.) ---- a/lib/Makefile -+++ b/lib/Makefile -@@ -120,6 +120,7 @@ obj-$(CONFIG_XZ_DEC) += xz/ - obj-$(CONFIG_RAID6_PQ) += raid6/ - obj-$(CONFIG_LZMA_COMPRESS) += lzma/ - obj-$(CONFIG_LZMA_DECOMPRESS) += lzma/ -+obj-$(CONFIG_RLE_DECOMPRESS) += rle.o - - lib-$(CONFIG_DECOMPRESS_GZIP) += decompress_inflate.o - lib-$(CONFIG_DECOMPRESS_BZIP2) += decompress_bunzip2.o ---- /dev/null -+++ b/include/linux/rle.h -@@ -0,0 +1,18 @@ -+#ifndef _RLE_H_ -+#define _RLE_H_ -+ -+#ifdef CONFIG_RLE_DECOMPRESS -+int rle_decode(const unsigned char *src, size_t srclen, -+ unsigned char *dst, size_t dstlen, -+ size_t *src_done, size_t *dst_done); -+#else -+static inline int -+rle_decode(const unsigned char *src, size_t srclen, -+ unsigned char *dst, size_t dstlen, -+ size_t *src_done, size_t *dst_done) -+{ -+ return -ENOTSUPP; -+} -+#endif /* CONFIG_RLE_DECOMPRESS */ -+ -+#endif /* _RLE_H_ */ ---- /dev/null -+++ b/lib/rle.c -@@ -0,0 +1,78 @@ -+/* -+ * RLE decoding routine -+ * -+ * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org> -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include <linux/kernel.h> -+#include <linux/module.h> -+#include <linux/rle.h> -+ -+int rle_decode(const unsigned char *src, size_t srclen, -+ unsigned char *dst, size_t dstlen, -+ size_t *src_done, size_t *dst_done) -+{ -+ size_t srcpos, dstpos; -+ int ret; -+ -+ srcpos = 0; -+ dstpos = 0; -+ ret = -EINVAL; -+ -+ /* sanity checks */ -+ if (!src || !srclen || !dst || !dstlen) -+ goto out; -+ -+ while (1) { -+ char count; -+ -+ if (srcpos >= srclen) -+ break; -+ -+ count = (char) src[srcpos++]; -+ if (count == 0) { -+ ret = 0; -+ break; -+ } -+ -+ if (count > 0) { -+ unsigned char c; -+ -+ if (srcpos >= srclen) -+ break; -+ -+ c = src[srcpos++]; -+ -+ while (count--) { -+ if (dstpos >= dstlen) -+ break; -+ -+ dst[dstpos++] = c; -+ } -+ } else { -+ count *= -1; -+ -+ while (count--) { -+ if (srcpos >= srclen) -+ break; -+ if (dstpos >= dstlen) -+ break; -+ dst[dstpos++] = src[srcpos++]; -+ } -+ } -+ } -+ -+out: -+ if (src_done) -+ *src_done = srcpos; -+ if (dst_done) -+ *dst_done = dstpos; -+ -+ return ret; -+} -+ -+EXPORT_SYMBOL_GPL(rle_decode); diff --git a/target/linux/ar71xx/patches-4.9/401-mtd-physmap-add-lock-unlock.patch b/target/linux/ar71xx/patches-4.9/401-mtd-physmap-add-lock-unlock.patch deleted file mode 100644 index db7b3ca83d..0000000000 --- a/target/linux/ar71xx/patches-4.9/401-mtd-physmap-add-lock-unlock.patch +++ /dev/null @@ -1,94 +0,0 @@ ---- a/drivers/mtd/maps/physmap.c -+++ b/drivers/mtd/maps/physmap.c -@@ -31,6 +31,66 @@ struct physmap_flash_info { - int vpp_refcnt; - }; - -+static struct platform_device *physmap_map2pdev(struct map_info *map) -+{ -+ return (struct platform_device *) map->map_priv_1; -+} -+ -+static void physmap_lock(struct map_info *map) -+{ -+ struct platform_device *pdev; -+ struct physmap_flash_data *physmap_data; -+ -+ pdev = physmap_map2pdev(map); -+ physmap_data = pdev->dev.platform_data; -+ physmap_data->lock(pdev); -+} -+ -+static void physmap_unlock(struct map_info *map) -+{ -+ struct platform_device *pdev; -+ struct physmap_flash_data *physmap_data; -+ -+ pdev = physmap_map2pdev(map); -+ physmap_data = pdev->dev.platform_data; -+ physmap_data->unlock(pdev); -+} -+ -+static map_word physmap_flash_read_lock(struct map_info *map, unsigned long ofs) -+{ -+ map_word ret; -+ -+ physmap_lock(map); -+ ret = inline_map_read(map, ofs); -+ physmap_unlock(map); -+ -+ return ret; -+} -+ -+static void physmap_flash_write_lock(struct map_info *map, map_word d, -+ unsigned long ofs) -+{ -+ physmap_lock(map); -+ inline_map_write(map, d, ofs); -+ physmap_unlock(map); -+} -+ -+static void physmap_flash_copy_from_lock(struct map_info *map, void *to, -+ unsigned long from, ssize_t len) -+{ -+ physmap_lock(map); -+ inline_map_copy_from(map, to, from, len); -+ physmap_unlock(map); -+} -+ -+static void physmap_flash_copy_to_lock(struct map_info *map, unsigned long to, -+ const void *from, ssize_t len) -+{ -+ physmap_lock(map); -+ inline_map_copy_to(map, to, from, len); -+ physmap_unlock(map); -+} -+ - static int physmap_flash_remove(struct platform_device *dev) - { - struct physmap_flash_info *info; -@@ -153,6 +213,13 @@ static int physmap_flash_probe(struct pl - - simple_map_init(&info->map[i]); - -+ if (physmap_data->lock && physmap_data->unlock) { -+ info->map[i].read = physmap_flash_read_lock; -+ info->map[i].write = physmap_flash_write_lock; -+ info->map[i].copy_from = physmap_flash_copy_from_lock; -+ info->map[i].copy_to = physmap_flash_copy_to_lock; -+ } -+ - probe_type = rom_probe_types; - if (physmap_data->probe_type == NULL) { - for (; info->mtd[i] == NULL && *probe_type != NULL; probe_type++) ---- a/include/linux/mtd/physmap.h -+++ b/include/linux/mtd/physmap.h -@@ -25,6 +25,8 @@ struct physmap_flash_data { - unsigned int width; - int (*init)(struct platform_device *); - void (*exit)(struct platform_device *); -+ void (*lock)(struct platform_device *); -+ void (*unlock)(struct platform_device *); - void (*set_vpp)(struct platform_device *, int); - unsigned int nr_parts; - unsigned int pfow_base; diff --git a/target/linux/ar71xx/patches-4.9/402-mtd-SST39VF6401B-support.patch b/target/linux/ar71xx/patches-4.9/402-mtd-SST39VF6401B-support.patch deleted file mode 100644 index 0d483ab1a4..0000000000 --- a/target/linux/ar71xx/patches-4.9/402-mtd-SST39VF6401B-support.patch +++ /dev/null @@ -1,29 +0,0 @@ ---- a/drivers/mtd/chips/jedec_probe.c -+++ b/drivers/mtd/chips/jedec_probe.c -@@ -148,6 +148,7 @@ - #define SST39LF160 0x2782 - #define SST39VF1601 0x234b - #define SST39VF3201 0x235b -+#define SST39VF6401B 0x236d - #define SST39WF1601 0x274b - #define SST39WF1602 0x274a - #define SST39LF512 0x00D4 -@@ -1569,6 +1570,18 @@ static const struct amd_flash_info jedec - ERASEINFO(0x10000,64), - } - }, { -+ .mfr_id = CFI_MFR_SST, -+ .dev_id = SST39VF6401B, -+ .name = "SST 39VF6401B", -+ .devtypes = CFI_DEVICETYPE_X16, -+ .uaddr = MTD_UADDR_0xAAAA_0x5555, -+ .dev_size = SIZE_8MiB, -+ .cmd_set = P_ID_AMD_STD, -+ .nr_regions = 1, -+ .regions = { -+ ERASEINFO(0x10000,128) -+ } -+ }, { - .mfr_id = CFI_MFR_ST, - .dev_id = M29F800AB, - .name = "ST M29F800AB", diff --git a/target/linux/ar71xx/patches-4.9/404-mtd-cybertan-trx-parser.patch b/target/linux/ar71xx/patches-4.9/404-mtd-cybertan-trx-parser.patch deleted file mode 100644 index 6c2322e07f..0000000000 --- a/target/linux/ar71xx/patches-4.9/404-mtd-cybertan-trx-parser.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/drivers/mtd/Kconfig -+++ b/drivers/mtd/Kconfig -@@ -178,6 +178,12 @@ menu "Partition parsers" - source "drivers/mtd/parsers/Kconfig" - endmenu - -+config MTD_CYBERTAN_PARTS -+ tristate "Cybertan partitioning support" -+ depends on ATH79 -+ ---help--- -+ Cybertan partitioning support -+ - config MTD_MYLOADER_PARTS - tristate "MyLoader partition parsing" - depends on ADM5120 || ATH25 || ATH79 ---- a/drivers/mtd/Makefile -+++ b/drivers/mtd/Makefile -@@ -17,6 +17,7 @@ obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63 - obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm47xxpart.o - obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o - obj-y += parsers/ -+obj-$(CONFIG_MTD_CYBERTAN_PARTS) += cybertan_part.o - - # 'Users' - code which presents functionality to userspace. - obj-$(CONFIG_MTD_BLKDEVS) += mtd_blkdevs.o diff --git a/target/linux/ar71xx/patches-4.9/405-mtd-tp-link-partition-parser.patch b/target/linux/ar71xx/patches-4.9/405-mtd-tp-link-partition-parser.patch deleted file mode 100644 index a53d9501ec..0000000000 --- a/target/linux/ar71xx/patches-4.9/405-mtd-tp-link-partition-parser.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/drivers/mtd/Kconfig -+++ b/drivers/mtd/Kconfig -@@ -200,6 +200,12 @@ config MTD_MYLOADER_PARTS - You will still need the parsing functions to be called by the driver - for your particular device. It won't happen automatically. - -+config MTD_TPLINK_PARTS -+ tristate "TP-Link AR7XXX/AR9XXX partitioning support" -+ depends on ATH79 -+ ---help--- -+ TBD. -+ - comment "User Modules And Translation Layers" - - # ---- a/drivers/mtd/Makefile -+++ b/drivers/mtd/Makefile -@@ -17,6 +17,7 @@ obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63 - obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm47xxpart.o - obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o - obj-y += parsers/ -+obj-$(CONFIG_MTD_TPLINK_PARTS) += tplinkpart.o - obj-$(CONFIG_MTD_CYBERTAN_PARTS) += cybertan_part.o - - # 'Users' - code which presents functionality to userspace. diff --git a/target/linux/ar71xx/patches-4.9/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch b/target/linux/ar71xx/patches-4.9/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch deleted file mode 100644 index cfc84c4afa..0000000000 --- a/target/linux/ar71xx/patches-4.9/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch +++ /dev/null @@ -1,34 +0,0 @@ ---- a/drivers/mtd/devices/m25p80.c -+++ b/drivers/mtd/devices/m25p80.c -@@ -195,6 +195,7 @@ static ssize_t m25p80_read(struct spi_no - */ - static int m25p_probe(struct spi_device *spi) - { -+ struct mtd_part_parser_data ppdata = {0,}; - struct flash_platform_data *data; - struct m25p *flash; - struct spi_nor *nor; -@@ -247,8 +248,11 @@ static int m25p_probe(struct spi_device - if (ret) - return ret; - -- return mtd_device_register(&nor->mtd, data ? data->parts : NULL, -- data ? data->nr_parts : 0); -+ return mtd_device_parse_register(&nor->mtd, -+ data ? data->part_probes : NULL, -+ &ppdata, -+ data ? data->parts : NULL, -+ data ? data->nr_parts : 0); - } - - ---- a/include/linux/spi/flash.h -+++ b/include/linux/spi/flash.h -@@ -24,6 +24,7 @@ struct flash_platform_data { - unsigned int nr_parts; - - char *type; -+ const char **part_probes; - - /* we'll likely add more ... use JEDEC IDs, etc */ - }; diff --git a/target/linux/ar71xx/patches-4.9/408-mtd-redboot_partition_scan.patch b/target/linux/ar71xx/patches-4.9/408-mtd-redboot_partition_scan.patch deleted file mode 100644 index 18ff52aca3..0000000000 --- a/target/linux/ar71xx/patches-4.9/408-mtd-redboot_partition_scan.patch +++ /dev/null @@ -1,44 +0,0 @@ ---- a/drivers/mtd/redboot.c -+++ b/drivers/mtd/redboot.c -@@ -77,12 +77,18 @@ static int parse_redboot_partitions(stru - static char nullstring[] = "unallocated"; - #endif - -+ buf = vmalloc(master->erasesize); -+ if (!buf) -+ return -ENOMEM; -+ -+ restart: - if ( directory < 0 ) { - offset = master->size + directory * master->erasesize; - while (mtd_block_isbad(master, offset)) { - if (!offset) { - nogood: - printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n"); -+ vfree(buf); - return -EIO; - } - offset -= master->erasesize; -@@ -95,10 +101,6 @@ static int parse_redboot_partitions(stru - goto nogood; - } - } -- buf = vmalloc(master->erasesize); -- -- if (!buf) -- return -ENOMEM; - - printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n", - master->name, offset); -@@ -171,6 +173,11 @@ static int parse_redboot_partitions(stru - } - if (i == numslots) { - /* Didn't find it */ -+ if (offset + master->erasesize < master->size) { -+ /* not at the end of the flash yet, maybe next block :) */ -+ directory++; -+ goto restart; -+ } - printk(KERN_NOTICE "No RedBoot partition table detected in %s\n", - master->name); - ret = 0; diff --git a/target/linux/ar71xx/patches-4.9/409-mtd-rb4xx_nand_driver.patch b/target/linux/ar71xx/patches-4.9/409-mtd-rb4xx_nand_driver.patch deleted file mode 100644 index 93d34b8826..0000000000 --- a/target/linux/ar71xx/patches-4.9/409-mtd-rb4xx_nand_driver.patch +++ /dev/null @@ -1,21 +0,0 @@ ---- a/drivers/mtd/nand/Kconfig -+++ b/drivers/mtd/nand/Kconfig -@@ -569,4 +569,8 @@ config MTD_NAND_MTK - Enables support for NAND controller on MTK SoCs. - This controller is found on mt27xx, mt81xx, mt65xx SoCs. - -+config MTD_NAND_RB4XX -+ tristate "NAND flash driver for RouterBoard 4xx series" -+ depends on MTD_NAND && ATH79_MACH_RB4XX -+ - endif # MTD_NAND ---- a/drivers/mtd/nand/Makefile -+++ b/drivers/mtd/nand/Makefile -@@ -33,6 +33,7 @@ obj-$(CONFIG_MTD_NAND_CM_X270) += cmx27 - obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o - obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o - obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o -+obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o - obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o - obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o - obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o diff --git a/target/linux/ar71xx/patches-4.9/410-mtd-rb750-nand-driver.patch b/target/linux/ar71xx/patches-4.9/410-mtd-rb750-nand-driver.patch deleted file mode 100644 index 9ea879c8e4..0000000000 --- a/target/linux/ar71xx/patches-4.9/410-mtd-rb750-nand-driver.patch +++ /dev/null @@ -1,21 +0,0 @@ ---- a/drivers/mtd/nand/Kconfig -+++ b/drivers/mtd/nand/Kconfig -@@ -573,4 +573,8 @@ config MTD_NAND_RB4XX - tristate "NAND flash driver for RouterBoard 4xx series" - depends on MTD_NAND && ATH79_MACH_RB4XX - -+config MTD_NAND_RB750 -+ tristate "NAND flash driver for the RouterBoard 750" -+ depends on MTD_NAND && ATH79_MACH_RB750 -+ - endif # MTD_NAND ---- a/drivers/mtd/nand/Makefile -+++ b/drivers/mtd/nand/Makefile -@@ -34,6 +34,7 @@ obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx - obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o - obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o - obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o -+obj-$(CONFIG_MTD_NAND_RB750) += rb750_nand.o - obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o - obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o - obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o diff --git a/target/linux/ar71xx/patches-4.9/411-mtd-cfi_cmdset_0002-force-word-write.patch b/target/linux/ar71xx/patches-4.9/411-mtd-cfi_cmdset_0002-force-word-write.patch deleted file mode 100644 index ddd69f17e1..0000000000 --- a/target/linux/ar71xx/patches-4.9/411-mtd-cfi_cmdset_0002-force-word-write.patch +++ /dev/null @@ -1,61 +0,0 @@ ---- a/drivers/mtd/chips/cfi_cmdset_0002.c -+++ b/drivers/mtd/chips/cfi_cmdset_0002.c -@@ -40,7 +40,7 @@ - #include <linux/mtd/xip.h> - - #define AMD_BOOTLOC_BUG --#define FORCE_WORD_WRITE 0 -+#define FORCE_WORD_WRITE 1 - - #define MAX_RETRIES 3 - -@@ -51,7 +51,9 @@ - - static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *); - static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); -+#if !FORCE_WORD_WRITE - static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); -+#endif - static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *); - static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *); - static void cfi_amdstd_sync (struct mtd_info *); -@@ -202,6 +204,7 @@ static void fixup_amd_bootblock(struct m - } - #endif - -+#if !FORCE_WORD_WRITE - static void fixup_use_write_buffers(struct mtd_info *mtd) - { - struct map_info *map = mtd->priv; -@@ -211,6 +214,7 @@ static void fixup_use_write_buffers(stru - mtd->_write = cfi_amdstd_write_buffers; - } - } -+#endif /* !FORCE_WORD_WRITE */ - - /* Atmel chips don't use the same PRI format as AMD chips */ - static void fixup_convert_atmel_pri(struct mtd_info *mtd) -@@ -1788,6 +1792,7 @@ static int cfi_amdstd_write_words(struct - /* - * FIXME: interleaved mode not tested, and probably not supported! - */ -+#if !FORCE_WORD_WRITE - static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip, - unsigned long adr, const u_char *buf, - int len) -@@ -1916,7 +1921,6 @@ static int __xipram do_write_buffer(stru - return ret; - } - -- - static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len, - size_t *retlen, const u_char *buf) - { -@@ -1991,6 +1995,7 @@ static int cfi_amdstd_write_buffers(stru - - return 0; - } -+#endif /* !FORCE_WORD_WRITE */ - - /* - * Wait for the flash chip to become ready to write data diff --git a/target/linux/ar71xx/patches-4.9/413-mtd-ar934x-nand-driver.patch b/target/linux/ar71xx/patches-4.9/413-mtd-ar934x-nand-driver.patch deleted file mode 100644 index 9f9c339e6b..0000000000 --- a/target/linux/ar71xx/patches-4.9/413-mtd-ar934x-nand-driver.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/drivers/mtd/nand/Kconfig -+++ b/drivers/mtd/nand/Kconfig -@@ -577,4 +577,12 @@ config MTD_NAND_RB750 - tristate "NAND flash driver for the RouterBoard 750" - depends on MTD_NAND && ATH79_MACH_RB750 - -+config MTD_NAND_AR934X -+ tristate "NAND flash driver for the Qualcomm Atheros AR934x/QCA955x SoCs" -+ depends on (SOC_AR934X || SOC_QCA955X) -+ -+config MTD_NAND_AR934X_HW_ECC -+ bool "Hardware ECC support for the AR934X NAND Controller (EXPERIMENTAL)" -+ depends on MTD_NAND_AR934X -+ - endif # MTD_NAND ---- a/drivers/mtd/nand/Makefile -+++ b/drivers/mtd/nand/Makefile -@@ -13,6 +13,7 @@ obj-$(CONFIG_MTD_NAND_AMS_DELTA) += ams- - obj-$(CONFIG_MTD_NAND_DENALI) += denali.o - obj-$(CONFIG_MTD_NAND_DENALI_PCI) += denali_pci.o - obj-$(CONFIG_MTD_NAND_DENALI_DT) += denali_dt.o -+obj-$(CONFIG_MTD_NAND_AR934X) += ar934x_nfc.o - obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o - obj-$(CONFIG_MTD_NAND_BF5XX) += bf5xx_nand.o - obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o diff --git a/target/linux/ar71xx/patches-4.9/414-mtd-rb91x-nand-driver.patch b/target/linux/ar71xx/patches-4.9/414-mtd-rb91x-nand-driver.patch deleted file mode 100644 index d1b61f096d..0000000000 --- a/target/linux/ar71xx/patches-4.9/414-mtd-rb91x-nand-driver.patch +++ /dev/null @@ -1,23 +0,0 @@ ---- a/drivers/mtd/nand/Kconfig -+++ b/drivers/mtd/nand/Kconfig -@@ -577,6 +577,10 @@ config MTD_NAND_RB750 - tristate "NAND flash driver for the RouterBoard 750" - depends on MTD_NAND && ATH79_MACH_RB750 - -+config MTD_NAND_RB91X -+ tristate "NAND flash driver for the RouterBOARD 91x series" -+ depends on MTD_NAND && ATH79_MACH_RB91X -+ - config MTD_NAND_AR934X - tristate "NAND flash driver for the Qualcomm Atheros AR934x/QCA955x SoCs" - depends on (SOC_AR934X || SOC_QCA955X) ---- a/drivers/mtd/nand/Makefile -+++ b/drivers/mtd/nand/Makefile -@@ -36,6 +36,7 @@ obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nan - obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o - obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o - obj-$(CONFIG_MTD_NAND_RB750) += rb750_nand.o -+obj-$(CONFIG_MTD_NAND_RB91X) += rb91x_nand.o - obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o - obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o - obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o diff --git a/target/linux/ar71xx/patches-4.9/420-net-ar71xx_mac_driver.patch b/target/linux/ar71xx/patches-4.9/420-net-ar71xx_mac_driver.patch deleted file mode 100644 index feb2e6a393..0000000000 --- a/target/linux/ar71xx/patches-4.9/420-net-ar71xx_mac_driver.patch +++ /dev/null @@ -1,28 +0,0 @@ ---- a/drivers/net/ethernet/atheros/Kconfig -+++ b/drivers/net/ethernet/atheros/Kconfig -@@ -5,7 +5,7 @@ - config NET_VENDOR_ATHEROS - bool "Atheros devices" - default y -- depends on PCI -+ depends on (PCI || ATH79) - ---help--- - If you have a network (Ethernet) card belonging to this class, say Y. - -@@ -78,4 +78,6 @@ config ALX - To compile this driver as a module, choose M here. The module - will be called alx. - -+source drivers/net/ethernet/atheros/ag71xx/Kconfig -+ - endif # NET_VENDOR_ATHEROS ---- a/drivers/net/ethernet/atheros/Makefile -+++ b/drivers/net/ethernet/atheros/Makefile -@@ -2,6 +2,7 @@ - # Makefile for the Atheros network device drivers. - # - -+obj-$(CONFIG_AG71XX) += ag71xx/ - obj-$(CONFIG_ATL1) += atlx/ - obj-$(CONFIG_ATL2) += atlx/ - obj-$(CONFIG_ATL1E) += atl1e/ diff --git a/target/linux/ar71xx/patches-4.9/423-dsa-add-88e6063-driver.patch b/target/linux/ar71xx/patches-4.9/423-dsa-add-88e6063-driver.patch deleted file mode 100644 index dbf892b434..0000000000 --- a/target/linux/ar71xx/patches-4.9/423-dsa-add-88e6063-driver.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/drivers/net/dsa/Kconfig -+++ b/drivers/net/dsa/Kconfig -@@ -9,6 +9,14 @@ config NET_DSA_MV88E6060 - This enables support for the Marvell 88E6060 ethernet switch - chip. - -+config NET_DSA_MV88E6063 -+ bool "Marvell 88E6063 ethernet switch chip support" -+ depends on NET_DSA -+ select NET_DSA_TAG_TRAILER -+ ---help--- -+ This enables support for the Marvell 88E6063 ethernet switch -+ chip -+ - config NET_DSA_BCM_SF2 - tristate "Broadcom Starfighter 2 Ethernet switch support" - depends on HAS_IOMEM && NET_DSA ---- a/drivers/net/dsa/Makefile -+++ b/drivers/net/dsa/Makefile -@@ -1,4 +1,5 @@ - obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o -+obj-$(CONFIG_NET_DSA_MV88E6063) += mv88e6063.o - obj-$(CONFIG_NET_DSA_BCM_SF2) += bcm_sf2.o - obj-$(CONFIG_NET_DSA_QCA8K) += qca8k.o - diff --git a/target/linux/ar71xx/patches-4.9/430-drivers-link-spi-before-mtd.patch b/target/linux/ar71xx/patches-4.9/430-drivers-link-spi-before-mtd.patch deleted file mode 100644 index a862454597..0000000000 --- a/target/linux/ar71xx/patches-4.9/430-drivers-link-spi-before-mtd.patch +++ /dev/null @@ -1,12 +0,0 @@ ---- a/drivers/Makefile -+++ b/drivers/Makefile -@@ -77,8 +77,8 @@ obj-$(CONFIG_SCSI) += scsi/ - obj-y += nvme/ - obj-$(CONFIG_ATA) += ata/ - obj-$(CONFIG_TARGET_CORE) += target/ --obj-$(CONFIG_MTD) += mtd/ - obj-$(CONFIG_SPI) += spi/ -+obj-$(CONFIG_MTD) += mtd/ - obj-$(CONFIG_SPMI) += spmi/ - obj-$(CONFIG_HSI) += hsi/ - obj-y += net/ diff --git a/target/linux/ar71xx/patches-4.9/432-spi-rb4xx-spi-driver.patch b/target/linux/ar71xx/patches-4.9/432-spi-rb4xx-spi-driver.patch deleted file mode 100644 index e896d0bdf4..0000000000 --- a/target/linux/ar71xx/patches-4.9/432-spi-rb4xx-spi-driver.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/drivers/spi/Kconfig -+++ b/drivers/spi/Kconfig -@@ -533,6 +533,12 @@ config SPI_QUP - This driver can also be built as a module. If so, the module - will be called spi_qup. - -+config SPI_RB4XX -+ tristate "Mikrotik RB4XX SPI master" -+ depends on SPI_MASTER && ATH79_MACH_RB4XX -+ help -+ SPI controller driver for the Mikrotik RB4xx series boards. -+ - config SPI_S3C24XX - tristate "Samsung S3C24XX series SPI" - depends on ARCH_S3C24XX ---- a/drivers/spi/Makefile -+++ b/drivers/spi/Makefile -@@ -72,6 +72,7 @@ obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx. - spi-pxa2xx-platform-objs := spi-pxa2xx.o spi-pxa2xx-dma.o - obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o - obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o -+obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o - obj-$(CONFIG_SPI_QUP) += spi-qup.o - obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o - obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o diff --git a/target/linux/ar71xx/patches-4.9/433-spi-rb4xx-cpld-driver.patch b/target/linux/ar71xx/patches-4.9/433-spi-rb4xx-cpld-driver.patch deleted file mode 100644 index c44acab32e..0000000000 --- a/target/linux/ar71xx/patches-4.9/433-spi-rb4xx-cpld-driver.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/spi/Kconfig -+++ b/drivers/spi/Kconfig -@@ -761,6 +761,13 @@ config SPI_TLE62X0 - sysfs interface, with each line presented as a kind of GPIO - exposing both switch control and diagnostic feedback. - -+config SPI_RB4XX_CPLD -+ tristate "MikroTik RB4XX CPLD driver" -+ depends on ATH79_MACH_RB4XX -+ help -+ SPI driver for the Xilinx CPLD chip present on the -+ MikroTik RB4xx boards. -+ - # - # Add new SPI protocol masters in alphabetical order above this line - # ---- a/drivers/spi/Makefile -+++ b/drivers/spi/Makefile -@@ -73,6 +73,7 @@ spi-pxa2xx-platform-objs := spi-pxa2xx. - obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o - obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o - obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o -+obj-$(CONFIG_SPI_RB4XX_CPLD) += spi-rb4xx-cpld.o - obj-$(CONFIG_SPI_QUP) += spi-qup.o - obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o - obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o diff --git a/target/linux/ar71xx/patches-4.9/435-spi-vsc7385_driver.patch b/target/linux/ar71xx/patches-4.9/435-spi-vsc7385_driver.patch deleted file mode 100644 index f9f1f7a1e5..0000000000 --- a/target/linux/ar71xx/patches-4.9/435-spi-vsc7385_driver.patch +++ /dev/null @@ -1,24 +0,0 @@ ---- a/drivers/spi/Kconfig -+++ b/drivers/spi/Kconfig -@@ -768,6 +768,11 @@ config SPI_RB4XX_CPLD - SPI driver for the Xilinx CPLD chip present on the - MikroTik RB4xx boards. - -+config SPI_VSC7385 -+ tristate "Vitesse VSC7385 ethernet switch driver" -+ help -+ SPI driver for the Vitesse VSC7385 ethernet switch. -+ - # - # Add new SPI protocol masters in alphabetical order above this line - # ---- a/drivers/spi/Makefile -+++ b/drivers/spi/Makefile -@@ -99,6 +99,7 @@ spi-thunderx-objs := spi-cavium.o spi- - obj-$(CONFIG_SPI_THUNDERX) += spi-thunderx.o - obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o - obj-$(CONFIG_SPI_TXX9) += spi-txx9.o -+obj-$(CONFIG_SPI_VSC7385) += spi-vsc7385.o - obj-$(CONFIG_SPI_XCOMM) += spi-xcomm.o - obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o - obj-$(CONFIG_SPI_XLP) += spi-xlp.o diff --git a/target/linux/ar71xx/patches-4.9/440-leds-wndr3700-usb-led-driver.patch b/target/linux/ar71xx/patches-4.9/440-leds-wndr3700-usb-led-driver.patch deleted file mode 100644 index 0bf5b1a7d9..0000000000 --- a/target/linux/ar71xx/patches-4.9/440-leds-wndr3700-usb-led-driver.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/leds/Kconfig -+++ b/drivers/leds/Kconfig -@@ -659,6 +659,13 @@ config LEDS_MLXCPLD - This option enabled support for the LEDs on the Mellanox - boards. Say Y to enabled these. - -+config LEDS_WNDR3700_USB -+ tristate "NETGEAR WNDR3700 USB LED driver" -+ depends on LEDS_CLASS && ATH79_MACH_WNDR3700 -+ help -+ This option enables support for the USB LED found on the -+ NETGEAR WNDR3700 board. -+ - comment "LED Triggers" - source "drivers/leds/trigger/Kconfig" - ---- a/drivers/leds/Makefile -+++ b/drivers/leds/Makefile -@@ -48,6 +48,7 @@ obj-$(CONFIG_LEDS_DA9052) += leds-da905 - obj-$(CONFIG_LEDS_WM831X_STATUS) += leds-wm831x-status.o - obj-$(CONFIG_LEDS_WM8350) += leds-wm8350.o - obj-$(CONFIG_LEDS_PWM) += leds-pwm.o -+obj-${CONFIG_LEDS_WNDR3700_USB} += leds-wndr3700-usb.o - obj-$(CONFIG_LEDS_REGULATOR) += leds-regulator.o - obj-$(CONFIG_LEDS_INTEL_SS4200) += leds-ss4200.o - obj-$(CONFIG_LEDS_LT3593) += leds-lt3593.o diff --git a/target/linux/ar71xx/patches-4.9/441-leds-rb750-led-driver.patch b/target/linux/ar71xx/patches-4.9/441-leds-rb750-led-driver.patch deleted file mode 100644 index 777a0df917..0000000000 --- a/target/linux/ar71xx/patches-4.9/441-leds-rb750-led-driver.patch +++ /dev/null @@ -1,23 +0,0 @@ ---- a/drivers/leds/Kconfig -+++ b/drivers/leds/Kconfig -@@ -666,6 +666,10 @@ config LEDS_WNDR3700_USB - This option enables support for the USB LED found on the - NETGEAR WNDR3700 board. - -+config LEDS_RB750 -+ tristate "LED driver for the Mikrotik RouterBOARD 750" -+ depends on LEDS_CLASS && ATH79_MACH_RB750 -+ - comment "LED Triggers" - source "drivers/leds/trigger/Kconfig" - ---- a/drivers/leds/Makefile -+++ b/drivers/leds/Makefile -@@ -55,6 +55,7 @@ obj-$(CONFIG_LEDS_LT3593) += leds-lt359 - obj-$(CONFIG_LEDS_ADP5520) += leds-adp5520.o - obj-$(CONFIG_LEDS_DELL_NETBOOKS) += dell-led.o - obj-$(CONFIG_LEDS_MC13783) += leds-mc13783.o -+obj-$(CONFIG_LEDS_RB750) += leds-rb750.o - obj-$(CONFIG_LEDS_NS2) += leds-ns2.o - obj-$(CONFIG_LEDS_NETXBIG) += leds-netxbig.o - obj-$(CONFIG_LEDS_ASIC3) += leds-asic3.o diff --git a/target/linux/ar71xx/patches-4.9/442-leds-gpio-allow-to-use-OPEN_-DRAIN-SOURCE-flags-with.patch b/target/linux/ar71xx/patches-4.9/442-leds-gpio-allow-to-use-OPEN_-DRAIN-SOURCE-flags-with.patch deleted file mode 100644 index 26c8cb5dfc..0000000000 --- a/target/linux/ar71xx/patches-4.9/442-leds-gpio-allow-to-use-OPEN_-DRAIN-SOURCE-flags-with.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 183148e0789bee1cd5c46ba49afcb211f636f8a2 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos <juhosg@freemail.hu> -Date: Mon, 15 Jan 2018 15:01:14 +0100 -Subject: [PATCH] leds: gpio: allow to use OPEN_{DRAIN,SOURCE} flags with - legacy GPIOs - -LEDs which are connected to open-source or open-drain type of GPIO lines -can be used only, if those are defined via devicetree. -Add two new fields to 'struct gpio_led' in order to make it possible to -specify this type of GPIO lines to the leds-gpio driver via platform data. -Also update the create_gpio_led() function to set the GPIOF_OPEN_DRAIN and -GPIOF_OPEN_SOURCE flags for the given GPIO line. - -Signed-off-by: Gabor Juhos <juhosg@freemail.hu> ---- - drivers/leds/leds-gpio.c | 6 ++++++ - include/linux/leds.h | 2 ++ - 2 files changed, 8 insertions(+) - ---- a/drivers/leds/leds-gpio.c -+++ b/drivers/leds/leds-gpio.c -@@ -100,6 +100,12 @@ static int create_gpio_led(const struct - if (template->active_low) - flags |= GPIOF_ACTIVE_LOW; - -+ if (template->open_drain) -+ flags |= GPIOF_OPEN_DRAIN; -+ -+ if (template->open_source) -+ flags |= GPIOF_OPEN_SOURCE; -+ - ret = devm_gpio_request_one(parent, template->gpio, flags, - template->name); - if (ret < 0) ---- a/include/linux/leds.h -+++ b/include/linux/leds.h -@@ -380,6 +380,8 @@ struct gpio_led { - unsigned panic_indicator : 1; - unsigned default_state : 2; - /* default_state should be one of LEDS_GPIO_DEFSTATE_(ON|OFF|KEEP) */ -+ unsigned open_drain : 1; -+ unsigned open_source : 1; - struct gpio_desc *gpiod; - }; - #define LEDS_GPIO_DEFSTATE_OFF 0 diff --git a/target/linux/ar71xx/patches-4.9/450-gpio-nxp-74hc153-gpio-chip-driver.patch b/target/linux/ar71xx/patches-4.9/450-gpio-nxp-74hc153-gpio-chip-driver.patch deleted file mode 100644 index 7ffdc769e3..0000000000 --- a/target/linux/ar71xx/patches-4.9/450-gpio-nxp-74hc153-gpio-chip-driver.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/drivers/gpio/Kconfig -+++ b/drivers/gpio/Kconfig -@@ -1213,4 +1213,12 @@ config GPIO_VIPERBOARD - - endmenu - -+comment "Other GPIO expanders" -+ -+config GPIO_NXP_74HC153 -+ tristate "NXP 74HC153 Dual 4-input multiplexer" -+ help -+ Platform driver for NXP 74HC153 Dual 4-input Multiplexer. This -+ provides a GPIO interface supporting input mode only. -+ - endif ---- a/drivers/gpio/Makefile -+++ b/drivers/gpio/Makefile -@@ -83,6 +83,7 @@ obj-$(CONFIG_GPIO_MSIC) += gpio-msic.o - obj-$(CONFIG_GPIO_MVEBU) += gpio-mvebu.o - obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o - obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o -+obj-$(CONFIG_GPIO_NXP_74HC153) += gpio-nxp-74hc153.o - obj-$(CONFIG_GPIO_OCTEON) += gpio-octeon.o - obj-$(CONFIG_GPIO_OMAP) += gpio-omap.o - obj-$(CONFIG_GPIO_PCA953X) += gpio-pca953x.o diff --git a/target/linux/ar71xx/patches-4.9/451-gpio-74x164-improve-platform-device-support.patch b/target/linux/ar71xx/patches-4.9/451-gpio-74x164-improve-platform-device-support.patch deleted file mode 100644 index a3d752e9a4..0000000000 --- a/target/linux/ar71xx/patches-4.9/451-gpio-74x164-improve-platform-device-support.patch +++ /dev/null @@ -1,119 +0,0 @@ ---- a/drivers/gpio/gpio-74x164.c -+++ b/drivers/gpio/gpio-74x164.c -@@ -12,6 +12,7 @@ - #include <linux/init.h> - #include <linux/mutex.h> - #include <linux/spi/spi.h> -+#include <linux/spi/74x164.h> - #include <linux/gpio.h> - #include <linux/of_gpio.h> - #include <linux/slab.h> -@@ -103,9 +104,16 @@ static int gen_74x164_direction_output(s - static int gen_74x164_probe(struct spi_device *spi) - { - struct gen_74x164_chip *chip; -+ struct gen_74x164_chip_platform_data *pdata = spi->dev.platform_data; -+ struct device_node *np = spi->dev.of_node; - u32 nregs; - int ret; - -+ if (!np && !pdata) { -+ dev_err(&spi->dev, "No configuration data available.\n"); -+ return -EINVAL; -+ } -+ - /* - * bits_per_word cannot be configured in platform data - */ -@@ -115,12 +123,15 @@ static int gen_74x164_probe(struct spi_d - if (ret < 0) - return ret; - -- if (of_property_read_u32(spi->dev.of_node, "registers-number", -- &nregs)) { -- dev_err(&spi->dev, -- "Missing registers-number property in the DT.\n"); -- return -EINVAL; -- } -+ if (np) { -+ if (of_property_read_u32(np, "registers-number", &nregs)) { -+ dev_err(&spi->dev, -+ "Missing registers-number property in the DT.\n"); -+ return -EINVAL; -+ } -+ } else if (pdata) { -+ nregs = pdata->num_registers; -+ } - - chip = devm_kzalloc(&spi->dev, sizeof(*chip) + nregs, GFP_KERNEL); - if (!chip) -@@ -133,7 +144,11 @@ static int gen_74x164_probe(struct spi_d - chip->gpio_chip.get = gen_74x164_get_value; - chip->gpio_chip.set = gen_74x164_set_value; - chip->gpio_chip.set_multiple = gen_74x164_set_multiple; -- chip->gpio_chip.base = -1; -+ if (np) -+ chip->gpio_chip.base = -1; -+ else if (pdata) -+ chip->gpio_chip.base = pdata->base; -+ - - chip->registers = nregs; - chip->gpio_chip.ngpio = GEN_74X164_NUMBER_GPIOS * chip->registers; -@@ -142,6 +157,9 @@ static int gen_74x164_probe(struct spi_d - chip->gpio_chip.parent = &spi->dev; - chip->gpio_chip.owner = THIS_MODULE; - -+ if (pdata && pdata->init_data) -+ memcpy(chip->buffer, pdata->init_data, chip->registers); -+ - mutex_init(&chip->lock); - - ret = __gen_74x164_write_config(chip); -@@ -170,17 +188,19 @@ static int gen_74x164_remove(struct spi_ - return 0; - } - -+#ifdef CONFIG_OF - static const struct of_device_id gen_74x164_dt_ids[] = { - { .compatible = "fairchild,74hc595" }, - { .compatible = "nxp,74lvc594" }, - {}, - }; - MODULE_DEVICE_TABLE(of, gen_74x164_dt_ids); -+#endif - - static struct spi_driver gen_74x164_driver = { - .driver = { - .name = "74x164", -- .of_match_table = gen_74x164_dt_ids, -+ .of_match_table = of_match_ptr(gen_74x164_dt_ids), - }, - .probe = gen_74x164_probe, - .remove = gen_74x164_remove, ---- /dev/null -+++ b/include/linux/spi/74x164.h -@@ -0,0 +1,13 @@ -+#ifndef LINUX_SPI_74X164_H -+#define LINUX_SPI_74X164_H -+ -+struct gen_74x164_chip_platform_data { -+ /* number assigned to the first GPIO */ -+ unsigned base; -+ /* number of chained registers */ -+ unsigned num_registers; -+ /* address of a buffer containing initial data */ -+ u8 *init_data; -+}; -+ -+#endif ---- a/drivers/gpio/Kconfig -+++ b/drivers/gpio/Kconfig -@@ -1154,7 +1154,6 @@ menu "SPI GPIO expanders" - - config GPIO_74X164 - tristate "74x164 serial-in/parallel-out 8-bits shift register" -- depends on OF_GPIO - help - Driver for 74x164 compatible serial-in/parallel-out 8-outputs - shift registers. This driver can be used to provide access diff --git a/target/linux/ar71xx/patches-4.9/452-gpio-add-gpio-latch-driver.patch b/target/linux/ar71xx/patches-4.9/452-gpio-add-gpio-latch-driver.patch deleted file mode 100644 index a56226f095..0000000000 --- a/target/linux/ar71xx/patches-4.9/452-gpio-add-gpio-latch-driver.patch +++ /dev/null @@ -1,22 +0,0 @@ ---- a/drivers/gpio/Kconfig -+++ b/drivers/gpio/Kconfig -@@ -1220,4 +1220,9 @@ config GPIO_NXP_74HC153 - Platform driver for NXP 74HC153 Dual 4-input Multiplexer. This - provides a GPIO interface supporting input mode only. - -+config GPIO_LATCH -+ tristate "GPIO latch driver" -+ help -+ Say yes here to enable a GPIO latch driver. -+ - endif ---- a/drivers/gpio/Makefile -+++ b/drivers/gpio/Makefile -@@ -56,6 +56,7 @@ obj-$(CONFIG_GPIO_JANZ_TTL) += gpio-janz - obj-$(CONFIG_GPIO_KEMPLD) += gpio-kempld.o - obj-$(CONFIG_ARCH_KS8695) += gpio-ks8695.o - obj-$(CONFIG_GPIO_INTEL_MID) += gpio-intel-mid.o -+obj-$(CONFIG_GPIO_LATCH) += gpio-latch.o - obj-$(CONFIG_GPIO_LOONGSON) += gpio-loongson.o - obj-$(CONFIG_GPIO_LP3943) += gpio-lp3943.o - obj-$(CONFIG_GPIO_LPC18XX) += gpio-lpc18xx.o diff --git a/target/linux/ar71xx/patches-4.9/461-spi-ath79-add-fast-flash-read.patch b/target/linux/ar71xx/patches-4.9/461-spi-ath79-add-fast-flash-read.patch deleted file mode 100644 index 5c3583f758..0000000000 --- a/target/linux/ar71xx/patches-4.9/461-spi-ath79-add-fast-flash-read.patch +++ /dev/null @@ -1,60 +0,0 @@ ---- a/drivers/spi/spi-ath79.c -+++ b/drivers/spi/spi-ath79.c -@@ -102,9 +102,6 @@ static void ath79_spi_enable(struct ath7 - /* save CTRL register */ - sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL); - sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC); -- -- /* TODO: setup speed? */ -- ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43); - } - - static void ath79_spi_disable(struct ath79_spi *sp) -@@ -205,6 +202,38 @@ static u32 ath79_spi_txrx_mode0(struct s - return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS); - } - -+static bool ath79_spi_flash_read_supported(struct spi_device *spi) -+{ -+ if (spi->chip_select || gpio_is_valid(spi->cs_gpio)) -+ return false; -+ -+ return true; -+} -+ -+static int ath79_spi_read_flash_data(struct spi_device *spi, -+ struct spi_flash_read_message *msg) -+{ -+ struct ath79_spi *sp = ath79_spidev_to_sp(spi); -+ -+ if (msg->addr_width > 3) -+ return -EOPNOTSUPP; -+ -+ /* disable GPIO mode */ -+ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0); -+ -+ memcpy_fromio(msg->buf, sp->base + msg->from, msg->len); -+ -+ /* enable GPIO mode */ -+ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); -+ -+ /* restore IOC register */ -+ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); -+ -+ msg->retlen = msg->len; -+ -+ return 0; -+} -+ - static int ath79_spi_probe(struct platform_device *pdev) - { - struct spi_master *master; -@@ -234,6 +263,8 @@ static int ath79_spi_probe(struct platfo - master->num_chipselect = pdata->num_chipselect; - master->cs_gpios = pdata->cs_gpios; - } -+ master->spi_flash_read = ath79_spi_read_flash_data; -+ master->flash_read_supported = ath79_spi_flash_read_supported; - - sp->bitbang.master = master; - sp->bitbang.chipselect = ath79_spi_chipselect; diff --git a/target/linux/ar71xx/patches-4.9/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch b/target/linux/ar71xx/patches-4.9/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch deleted file mode 100644 index 520c652059..0000000000 --- a/target/linux/ar71xx/patches-4.9/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch +++ /dev/null @@ -1,111 +0,0 @@ ---- /dev/null -+++ b/arch/mips/include/asm/mach-ath79/mangle-port.h -@@ -0,0 +1,37 @@ -+/* -+ * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org> -+ * -+ * This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h -+ * Copyright (C) 2003, 2004 Ralf Baechle -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __ASM_MACH_ATH79_MANGLE_PORT_H -+#define __ASM_MACH_ATH79_MANGLE_PORT_H -+ -+#ifdef CONFIG_PCI -+extern unsigned long (ath79_pci_swizzle_b)(unsigned long port); -+extern unsigned long (ath79_pci_swizzle_w)(unsigned long port); -+#else -+#define ath79_pci_swizzle_b(port) (port) -+#define ath79_pci_swizzle_w(port) (port) -+#endif -+ -+#define __swizzle_addr_b(port) ath79_pci_swizzle_b(port) -+#define __swizzle_addr_w(port) ath79_pci_swizzle_w(port) -+#define __swizzle_addr_l(port) (port) -+#define __swizzle_addr_q(port) (port) -+ -+# define ioswabb(a, x) (x) -+# define __mem_ioswabb(a, x) (x) -+# define ioswabw(a, x) (x) -+# define __mem_ioswabw(a, x) cpu_to_le16(x) -+# define ioswabl(a, x) (x) -+# define __mem_ioswabl(a, x) cpu_to_le32(x) -+# define ioswabq(a, x) (x) -+# define __mem_ioswabq(a, x) cpu_to_le64(x) -+ -+#endif /* __ASM_MACH_ATH79_MANGLE_PORT_H */ ---- a/arch/mips/ath79/pci.c -+++ b/arch/mips/ath79/pci.c -@@ -13,6 +13,7 @@ - */ - - #include <linux/init.h> -+#include <linux/export.h> - #include <linux/pci.h> - #include <linux/resource.h> - #include <linux/platform_device.h> -@@ -25,6 +26,9 @@ static int (*ath79_pci_plat_dev_init)(st - static const struct ath79_pci_irq *ath79_pci_irq_map __initdata; - static unsigned ath79_pci_nr_irqs __initdata; - -+static unsigned long (*__ath79_pci_swizzle_b)(unsigned long port); -+static unsigned long (*__ath79_pci_swizzle_w)(unsigned long port); -+ - static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = { - { - .slot = 17, -@@ -212,12 +216,50 @@ ath79_register_pci_ar724x(int id, - return pdev; - } - -+static inline bool ar71xx_is_pci_addr(unsigned long port) -+{ -+ unsigned long phys = CPHYSADDR(port); -+ -+ return (phys >= AR71XX_PCI_MEM_BASE && -+ phys < AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE); -+} -+ -+static unsigned long ar71xx_pci_swizzle_b(unsigned long port) -+{ -+ return ar71xx_is_pci_addr(port) ? port ^ 3 : port; -+} -+ -+static unsigned long ar71xx_pci_swizzle_w(unsigned long port) -+{ -+ return ar71xx_is_pci_addr(port) ? port ^ 2 : port; -+} -+ -+unsigned long ath79_pci_swizzle_b(unsigned long port) -+{ -+ if (__ath79_pci_swizzle_b) -+ return __ath79_pci_swizzle_b(port); -+ -+ return port; -+} -+EXPORT_SYMBOL(ath79_pci_swizzle_b); -+ -+unsigned long ath79_pci_swizzle_w(unsigned long port) -+{ -+ if (__ath79_pci_swizzle_w) -+ return __ath79_pci_swizzle_w(port); -+ -+ return port; -+} -+EXPORT_SYMBOL(ath79_pci_swizzle_w); -+ - int __init ath79_register_pci(void) - { - struct platform_device *pdev = NULL; - - if (soc_is_ar71xx()) { - pdev = ath79_register_pci_ar71xx(); -+ __ath79_pci_swizzle_b = ar71xx_pci_swizzle_b; -+ __ath79_pci_swizzle_w = ar71xx_pci_swizzle_w; - } else if (soc_is_ar724x()) { - pdev = ath79_register_pci_ar724x(-1, - AR724X_PCI_CFG_BASE, diff --git a/target/linux/ar71xx/patches-4.9/490-usb-ehci-add-quirks-for-qca-socs.patch b/target/linux/ar71xx/patches-4.9/490-usb-ehci-add-quirks-for-qca-socs.patch deleted file mode 100644 index 8a05adb050..0000000000 --- a/target/linux/ar71xx/patches-4.9/490-usb-ehci-add-quirks-for-qca-socs.patch +++ /dev/null @@ -1,103 +0,0 @@ ---- a/drivers/usb/host/ehci-hcd.c -+++ b/drivers/usb/host/ehci-hcd.c -@@ -252,6 +252,37 @@ int ehci_reset(struct ehci_hcd *ehci) - command |= CMD_RESET; - dbg_cmd (ehci, "reset", command); - ehci_writel(ehci, command, &ehci->regs->command); -+ -+ if (ehci->qca_force_host_mode) { -+ u32 usbmode; -+ -+ udelay(1000); -+ -+ usbmode = ehci_readl(ehci, &ehci->regs->usbmode); -+ usbmode |= USBMODE_CM_HC | (1 << 4); -+ ehci_writel(ehci, usbmode, &ehci->regs->usbmode); -+ -+ ehci_dbg(ehci, "forced host mode, usbmode: %08x\n", -+ ehci_readl(ehci, &ehci->regs->usbmode)); -+ } -+ -+ if (ehci->qca_force_16bit_ptw) { -+ u32 port_status; -+ -+ udelay(1000); -+ -+ /* enable 16-bit UTMI interface */ -+ port_status = ehci_readl(ehci, &ehci->regs->port_status[0]); -+ port_status |= BIT(28); -+ ehci_writel(ehci, port_status, &ehci->regs->port_status[0]); -+ -+ ehci_dbg(ehci, "16-bit UTMI interface enabled, status: %08x\n", -+ ehci_readl(ehci, &ehci->regs->port_status[0])); -+ } -+ -+ if (ehci->reset_notifier) -+ ehci->reset_notifier(ehci_to_hcd(ehci)); -+ - ehci->rh_state = EHCI_RH_HALTED; - ehci->next_statechange = jiffies; - retval = ehci_handshake(ehci, &ehci->regs->command, ---- a/drivers/usb/host/ehci.h -+++ b/drivers/usb/host/ehci.h -@@ -231,6 +231,10 @@ struct ehci_hcd { /* one per controlle - unsigned need_oc_pp_cycle:1; /* MPC834X port power */ - unsigned imx28_write_fix:1; /* For Freescale i.MX28 */ - unsigned ignore_oc:1; -+ unsigned qca_force_host_mode:1; -+ unsigned qca_force_16bit_ptw:1; /* force 16 bit UTMI */ -+ -+ void (*reset_notifier)(struct usb_hcd *hcd); - - /* required for usb32 quirk */ - #define OHCI_CTRL_HCFS (3 << 6) ---- a/include/linux/usb/ehci_pdriver.h -+++ b/include/linux/usb/ehci_pdriver.h -@@ -50,6 +50,8 @@ struct usb_ehci_pdata { - unsigned reset_on_resume:1; - unsigned dma_mask_64:1; - unsigned ignore_oc:1; -+ unsigned qca_force_host_mode:1; -+ unsigned qca_force_16bit_ptw:1; - - /* Turn on all power and clocks */ - int (*power_on)(struct platform_device *pdev); -@@ -59,6 +61,7 @@ struct usb_ehci_pdata { - * turn off everything else */ - void (*power_suspend)(struct platform_device *pdev); - int (*pre_setup)(struct usb_hcd *hcd); -+ void (*reset_notifier)(struct platform_device *pdev); - }; - - #endif /* __USB_CORE_EHCI_PDRIVER_H */ ---- a/drivers/usb/host/ehci-platform.c -+++ b/drivers/usb/host/ehci-platform.c -@@ -52,6 +52,14 @@ struct ehci_platform_priv { - - static const char hcd_name[] = "ehci-platform"; - -+static void ehci_platform_reset_notifier(struct usb_hcd *hcd) -+{ -+ struct platform_device *pdev = to_platform_device(hcd->self.controller); -+ struct usb_ehci_pdata *pdata = pdev->dev.platform_data; -+ -+ pdata->reset_notifier(pdev); -+} -+ - static int ehci_platform_reset(struct usb_hcd *hcd) - { - struct platform_device *pdev = to_platform_device(hcd->self.controller); -@@ -261,6 +269,13 @@ static int ehci_platform_probe(struct pl - priv->reset_on_resume = true; - if (pdata->ignore_oc) - ehci->ignore_oc = 1; -+ if (pdata->qca_force_host_mode) -+ ehci->qca_force_host_mode = 1; -+ if (pdata->qca_force_16bit_ptw) -+ ehci->qca_force_16bit_ptw = 1; -+ -+ if (pdata->reset_notifier) -+ ehci->reset_notifier = ehci_platform_reset_notifier; - - #ifndef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO - if (ehci->big_endian_mmio) { diff --git a/target/linux/ar71xx/patches-4.9/500-MIPS-fw-myloader.patch b/target/linux/ar71xx/patches-4.9/500-MIPS-fw-myloader.patch deleted file mode 100644 index 304fd69b22..0000000000 --- a/target/linux/ar71xx/patches-4.9/500-MIPS-fw-myloader.patch +++ /dev/null @@ -1,22 +0,0 @@ ---- a/arch/mips/Makefile -+++ b/arch/mips/Makefile -@@ -218,6 +218,7 @@ cflags-$(toolchain-virt) += -DTOOLCHAIN - # - libs-$(CONFIG_FW_ARC) += arch/mips/fw/arc/ - libs-$(CONFIG_FW_CFE) += arch/mips/fw/cfe/ -+libs-$(CONFIG_MYLOADER) += arch/mips/fw/myloader/ - libs-$(CONFIG_FW_SNIPROM) += arch/mips/fw/sni/ - libs-y += arch/mips/fw/lib/ - ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -1150,6 +1150,9 @@ config MIPS_MSC - config MIPS_NILE4 - bool - -+config MYLOADER -+ bool -+ - config SYNC_R4K - bool - diff --git a/target/linux/ar71xx/patches-4.9/501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch b/target/linux/ar71xx/patches-4.9/501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch deleted file mode 100644 index 12ab3b50d6..0000000000 --- a/target/linux/ar71xx/patches-4.9/501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch +++ /dev/null @@ -1,70 +0,0 @@ ---- a/arch/mips/ath79/dev-wmac.c -+++ b/arch/mips/ath79/dev-wmac.c -@@ -15,6 +15,7 @@ - #include <linux/init.h> - #include <linux/delay.h> - #include <linux/irq.h> -+#include <linux/etherdevice.h> - #include <linux/platform_device.h> - #include <linux/ath9k_platform.h> - -@@ -22,6 +23,7 @@ - #include <asm/mach-ath79/ar71xx_regs.h> - #include "dev-wmac.h" - -+static u8 ath79_wmac_mac[ETH_ALEN]; - static struct ath9k_platform_data ath79_wmac_data; - - static struct resource ath79_wmac_resources[] = { -@@ -161,7 +163,7 @@ static void qca955x_wmac_setup(void) - ath79_wmac_data.is_clk_25mhz = true; - } - --void __init ath79_register_wmac(u8 *cal_data) -+void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr) - { - if (soc_is_ar913x()) - ar913x_wmac_setup(); -@@ -178,5 +180,10 @@ void __init ath79_register_wmac(u8 *cal_ - memcpy(ath79_wmac_data.eeprom_data, cal_data, - sizeof(ath79_wmac_data.eeprom_data)); - -+ if (mac_addr) { -+ memcpy(ath79_wmac_mac, mac_addr, sizeof(ath79_wmac_mac)); -+ ath79_wmac_data.macaddr = ath79_wmac_mac; -+ } -+ - platform_device_register(&ath79_wmac_device); - } ---- a/arch/mips/ath79/dev-wmac.h -+++ b/arch/mips/ath79/dev-wmac.h -@@ -12,6 +12,6 @@ - #ifndef _ATH79_DEV_WMAC_H - #define _ATH79_DEV_WMAC_H - --void ath79_register_wmac(u8 *cal_data); -+void ath79_register_wmac(u8 *cal_data, u8 *mac_addr); - - #endif /* _ATH79_DEV_WMAC_H */ ---- a/arch/mips/ath79/mach-db120.c -+++ b/arch/mips/ath79/mach-db120.c -@@ -128,7 +128,7 @@ static void __init db120_setup(void) - ath79_register_spi(&db120_spi_data, db120_spi_info, - ARRAY_SIZE(db120_spi_info)); - ath79_register_usb(); -- ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET); -+ ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL); - db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET); - } - ---- a/arch/mips/ath79/mach-ap121.c -+++ b/arch/mips/ath79/mach-ap121.c -@@ -85,7 +85,7 @@ static void __init ap121_setup(void) - ath79_register_spi(&ap121_spi_data, ap121_spi_info, - ARRAY_SIZE(ap121_spi_info)); - ath79_register_usb(); -- ath79_register_wmac(cal_data); -+ ath79_register_wmac(cal_data, NULL); - } - - MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board", diff --git a/target/linux/ar71xx/patches-4.9/504-MIPS-ath79-add-ath79_device_reset_get.patch b/target/linux/ar71xx/patches-4.9/504-MIPS-ath79-add-ath79_device_reset_get.patch deleted file mode 100644 index c0e96b2729..0000000000 --- a/target/linux/ar71xx/patches-4.9/504-MIPS-ath79-add-ath79_device_reset_get.patch +++ /dev/null @@ -1,42 +0,0 @@ ---- a/arch/mips/include/asm/mach-ath79/ath79.h -+++ b/arch/mips/include/asm/mach-ath79/ath79.h -@@ -145,6 +145,7 @@ static inline u32 ath79_reset_rr(unsigne - - void ath79_device_reset_set(u32 mask); - void ath79_device_reset_clear(u32 mask); -+u32 ath79_device_reset_get(u32 mask); - - void ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3); - void ath79_misc_irq_init(void __iomem *regs, int irq, ---- a/arch/mips/ath79/common.c -+++ b/arch/mips/ath79/common.c -@@ -142,3 +142,29 @@ void ath79_device_reset_clear(u32 mask) - spin_unlock_irqrestore(&ath79_device_reset_lock, flags); - } - EXPORT_SYMBOL_GPL(ath79_device_reset_clear); -+ -+u32 ath79_device_reset_get(u32 mask) -+{ -+ unsigned long flags; -+ u32 reg; -+ u32 ret; -+ -+ if (soc_is_ar71xx()) -+ reg = AR71XX_RESET_REG_RESET_MODULE; -+ else if (soc_is_ar724x()) -+ reg = AR724X_RESET_REG_RESET_MODULE; -+ else if (soc_is_ar913x()) -+ reg = AR913X_RESET_REG_RESET_MODULE; -+ else if (soc_is_ar933x()) -+ reg = AR933X_RESET_REG_RESET_MODULE; -+ else if (soc_is_ar934x()) -+ reg = AR934X_RESET_REG_RESET_MODULE; -+ else -+ BUG(); -+ -+ spin_lock_irqsave(&ath79_device_reset_lock, flags); -+ ret = ath79_reset_rr(reg); -+ spin_unlock_irqrestore(&ath79_device_reset_lock, flags); -+ return ret; -+} -+EXPORT_SYMBOL_GPL(ath79_device_reset_get); diff --git a/target/linux/ar71xx/patches-4.9/505-MIPS-ath79-add-ath79_gpio_function_select.patch b/target/linux/ar71xx/patches-4.9/505-MIPS-ath79-add-ath79_gpio_function_select.patch deleted file mode 100644 index 278e781539..0000000000 --- a/target/linux/ar71xx/patches-4.9/505-MIPS-ath79-add-ath79_gpio_function_select.patch +++ /dev/null @@ -1,39 +0,0 @@ ---- a/arch/mips/ath79/common.h -+++ b/arch/mips/ath79/common.h -@@ -27,6 +27,7 @@ void ath79_ddr_ctrl_init(void); - void ath79_gpio_function_enable(u32 mask); - void ath79_gpio_function_disable(u32 mask); - void ath79_gpio_function_setup(u32 set, u32 clear); -+void ath79_gpio_output_select(unsigned gpio, u8 val); - void ath79_gpio_init(void); - - #endif /* __ATH79_COMMON_H */ ---- a/arch/mips/ath79/gpio.c -+++ b/arch/mips/ath79/gpio.c -@@ -57,3 +57,26 @@ void ath79_gpio_function_disable(u32 mas - { - ath79_gpio_function_setup(0, mask); - } -+ -+void __init ath79_gpio_output_select(unsigned gpio, u8 val) -+{ -+ void __iomem *base = ath79_gpio_base; -+ unsigned int reg; -+ u32 t, s; -+ -+ BUG_ON(!soc_is_ar934x()); -+ -+ if (gpio >= AR934X_GPIO_COUNT) -+ return; -+ -+ reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4); -+ s = 8 * (gpio % 4); -+ -+ t = __raw_readl(base + reg); -+ t &= ~(0xff << s); -+ t |= val << s; -+ __raw_writel(t, base + reg); -+ -+ /* flush write */ -+ (void) __raw_readl(base + reg); -+} diff --git a/target/linux/ar71xx/patches-4.9/506-MIPS-ath79-prom-parse-redboot-args.patch b/target/linux/ar71xx/patches-4.9/506-MIPS-ath79-prom-parse-redboot-args.patch deleted file mode 100644 index 46beeffeea..0000000000 --- a/target/linux/ar71xx/patches-4.9/506-MIPS-ath79-prom-parse-redboot-args.patch +++ /dev/null @@ -1,42 +0,0 @@ ---- a/arch/mips/ath79/prom.c -+++ b/arch/mips/ath79/prom.c -@@ -22,10 +22,39 @@ - - #include "common.h" - -+static char ath79_cmdline_buf[COMMAND_LINE_SIZE] __initdata; -+ -+static void __init ath79_prom_append_cmdline(const char *name, -+ const char *value) -+{ -+ snprintf(ath79_cmdline_buf, sizeof(ath79_cmdline_buf), -+ " %s=%s", name, value); -+ strlcat(arcs_cmdline, ath79_cmdline_buf, sizeof(arcs_cmdline)); -+} -+ - void __init prom_init(void) - { -+ const char *env; -+ - fw_init_cmdline(); - -+ env = fw_getenv("ethaddr"); -+ if (env) -+ ath79_prom_append_cmdline("ethaddr", env); -+ -+ env = fw_getenv("board"); -+ if (env) { -+ /* Workaround for buggy bootloaders */ -+ if (strcmp(env, "RouterStation") == 0 || -+ strcmp(env, "Ubiquiti AR71xx-based board") == 0) -+ env = "UBNT-RS"; -+ -+ if (strcmp(env, "RouterStation PRO") == 0) -+ env = "UBNT-RSPRO"; -+ -+ ath79_prom_append_cmdline("board", env); -+ } -+ - #ifdef CONFIG_BLK_DEV_INITRD - /* Read the initrd address from the firmware environment */ - initrd_start = fw_getenvl("initrd_start"); diff --git a/target/linux/ar71xx/patches-4.9/507-MIPS-ath79-prom-add-myloader-support.patch b/target/linux/ar71xx/patches-4.9/507-MIPS-ath79-prom-add-myloader-support.patch deleted file mode 100644 index 17a97335d2..0000000000 --- a/target/linux/ar71xx/patches-4.9/507-MIPS-ath79-prom-add-myloader-support.patch +++ /dev/null @@ -1,55 +0,0 @@ ---- a/arch/mips/ath79/prom.c -+++ b/arch/mips/ath79/prom.c -@@ -19,6 +19,7 @@ - #include <asm/bootinfo.h> - #include <asm/addrspace.h> - #include <asm/fw/fw.h> -+#include <asm/fw/myloader/myloader.h> - - #include "common.h" - -@@ -32,10 +33,44 @@ static void __init ath79_prom_append_cmd - strlcat(arcs_cmdline, ath79_cmdline_buf, sizeof(arcs_cmdline)); - } - -+static int __init ath79_prom_init_myloader(void) -+{ -+ struct myloader_info *mylo; -+ char mac_buf[32]; -+ unsigned char *mac; -+ -+ mylo = myloader_get_info(); -+ if (!mylo) -+ return 0; -+ -+ switch (mylo->did) { -+ case DEVID_COMPEX_WP543: -+ ath79_prom_append_cmdline("board", "WP543"); -+ break; -+ case DEVID_COMPEX_WPE72: -+ ath79_prom_append_cmdline("board", "WPE72"); -+ break; -+ default: -+ pr_warn("prom: unknown device id: %x\n", mylo->did); -+ return 0; -+ } -+ -+ mac = mylo->macs[0]; -+ snprintf(mac_buf, sizeof(mac_buf), "%02x:%02x:%02x:%02x:%02x:%02x", -+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); -+ -+ ath79_prom_append_cmdline("ethaddr", mac_buf); -+ -+ return 1; -+} -+ - void __init prom_init(void) - { - const char *env; - -+ if (ath79_prom_init_myloader()) -+ return; -+ - fw_init_cmdline(); - - env = fw_getenv("ethaddr"); diff --git a/target/linux/ar71xx/patches-4.9/508-MIPS-ath79-prom-image-command-line-hack.patch b/target/linux/ar71xx/patches-4.9/508-MIPS-ath79-prom-image-command-line-hack.patch deleted file mode 100644 index cfa5e72eec..0000000000 --- a/target/linux/ar71xx/patches-4.9/508-MIPS-ath79-prom-image-command-line-hack.patch +++ /dev/null @@ -1,73 +0,0 @@ ---- a/arch/mips/ath79/prom.c -+++ b/arch/mips/ath79/prom.c -@@ -33,6 +33,41 @@ static void __init ath79_prom_append_cmd - strlcat(arcs_cmdline, ath79_cmdline_buf, sizeof(arcs_cmdline)); - } - -+#ifdef CONFIG_IMAGE_CMDLINE_HACK -+extern char __image_cmdline[]; -+ -+static int __init ath79_use_image_cmdline(void) -+{ -+ char *p = __image_cmdline; -+ int replace = 0; -+ -+ if (*p == '-') { -+ replace = 1; -+ p++; -+ } -+ -+ if (*p == '\0') -+ return 0; -+ -+ if (replace) { -+ strlcpy(arcs_cmdline, p, sizeof(arcs_cmdline)); -+ } else { -+ strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); -+ strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); -+ } -+ -+ /* Validate and setup environment pointer */ -+ if (fw_arg2 < CKSEG0) -+ _fw_envp = NULL; -+ else -+ _fw_envp = (int *)fw_arg2; -+ -+ return 1; -+} -+#else -+static inline int ath79_use_image_cmdline(void) { return 0; } -+#endif -+ - static int __init ath79_prom_init_myloader(void) - { - struct myloader_info *mylo; -@@ -61,6 +96,8 @@ static int __init ath79_prom_init_myload - - ath79_prom_append_cmdline("ethaddr", mac_buf); - -+ ath79_use_image_cmdline(); -+ - return 1; - } - -@@ -71,7 +108,8 @@ void __init prom_init(void) - if (ath79_prom_init_myloader()) - return; - -- fw_init_cmdline(); -+ if (!ath79_use_image_cmdline()) -+ fw_init_cmdline(); - - env = fw_getenv("ethaddr"); - if (env) ---- a/arch/mips/fw/lib/cmdline.c -+++ b/arch/mips/fw/lib/cmdline.c -@@ -35,6 +35,7 @@ void __init fw_init_cmdline(void) - else - _fw_envp = (int *)fw_arg2; - -+ arcs_cmdline[0] = '\0'; - for (i = 1; i < fw_argc; i++) { - strlcat(arcs_cmdline, fw_argv(i), COMMAND_LINE_SIZE); - if (i < (fw_argc - 1)) diff --git a/target/linux/ar71xx/patches-4.9/509-MIPS-ath79-process-board-kernel-option.patch b/target/linux/ar71xx/patches-4.9/509-MIPS-ath79-process-board-kernel-option.patch deleted file mode 100644 index 3091ab69b6..0000000000 --- a/target/linux/ar71xx/patches-4.9/509-MIPS-ath79-process-board-kernel-option.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/mips/ath79/setup.c -+++ b/arch/mips/ath79/setup.c -@@ -283,6 +283,8 @@ void __init plat_time_init(void) - mips_hpt_frequency = cpu_clk_rate / 2; - } - -+__setup("board=", mips_machtype_setup); -+ - static int __init ath79_setup(void) - { - if (mips_machtype == ATH79_MACH_GENERIC_OF) diff --git a/target/linux/ar71xx/patches-4.9/510-MIPS-ath79-init-gpio-pin-of-wmac-device.patch b/target/linux/ar71xx/patches-4.9/510-MIPS-ath79-init-gpio-pin-of-wmac-device.patch deleted file mode 100644 index 2d2235e292..0000000000 --- a/target/linux/ar71xx/patches-4.9/510-MIPS-ath79-init-gpio-pin-of-wmac-device.patch +++ /dev/null @@ -1,14 +0,0 @@ ---- a/arch/mips/ath79/dev-wmac.c -+++ b/arch/mips/ath79/dev-wmac.c -@@ -24,7 +24,10 @@ - #include "dev-wmac.h" - - static u8 ath79_wmac_mac[ETH_ALEN]; --static struct ath9k_platform_data ath79_wmac_data; -+ -+static struct ath9k_platform_data ath79_wmac_data = { -+ .led_pin = -1, -+}; - - static struct resource ath79_wmac_resources[] = { - { diff --git a/target/linux/ar71xx/patches-4.9/520-MIPS-ath79-enable-UART-function.patch b/target/linux/ar71xx/patches-4.9/520-MIPS-ath79-enable-UART-function.patch deleted file mode 100644 index c8649b7494..0000000000 --- a/target/linux/ar71xx/patches-4.9/520-MIPS-ath79-enable-UART-function.patch +++ /dev/null @@ -1,18 +0,0 @@ ---- a/arch/mips/ath79/dev-common.c -+++ b/arch/mips/ath79/dev-common.c -@@ -81,6 +81,15 @@ void __init ath79_register_uart(void) - - uart_clk_rate = ath79_get_sys_clk_rate("uart"); - -+ if (soc_is_ar71xx()) -+ ath79_gpio_function_enable(AR71XX_GPIO_FUNC_UART_EN); -+ else if (soc_is_ar724x()) -+ ath79_gpio_function_enable(AR724X_GPIO_FUNC_UART_EN); -+ else if (soc_is_ar913x()) -+ ath79_gpio_function_enable(AR913X_GPIO_FUNC_UART_EN); -+ else if (soc_is_ar933x()) -+ ath79_gpio_function_enable(AR933X_GPIO_FUNC_UART_EN); -+ - if (soc_is_ar71xx() || - soc_is_ar724x() || - soc_is_ar913x() || diff --git a/target/linux/ar71xx/patches-4.9/521-MIPS-ath79-enable-UART-for-early_serial.patch b/target/linux/ar71xx/patches-4.9/521-MIPS-ath79-enable-UART-for-early_serial.patch deleted file mode 100644 index e546ff26fe..0000000000 --- a/target/linux/ar71xx/patches-4.9/521-MIPS-ath79-enable-UART-for-early_serial.patch +++ /dev/null @@ -1,61 +0,0 @@ ---- a/arch/mips/ath79/early_printk.c -+++ b/arch/mips/ath79/early_printk.c -@@ -58,6 +58,46 @@ static void prom_putchar_dummy(unsigned - /* nothing to do */ - } - -+static void prom_enable_uart(u32 id) -+{ -+ void __iomem *gpio_base; -+ u32 uart_en; -+ u32 t; -+ -+ switch (id) { -+ case REV_ID_MAJOR_AR71XX: -+ uart_en = AR71XX_GPIO_FUNC_UART_EN; -+ break; -+ -+ case REV_ID_MAJOR_AR7240: -+ case REV_ID_MAJOR_AR7241: -+ case REV_ID_MAJOR_AR7242: -+ uart_en = AR724X_GPIO_FUNC_UART_EN; -+ break; -+ -+ case REV_ID_MAJOR_AR913X: -+ uart_en = AR913X_GPIO_FUNC_UART_EN; -+ break; -+ -+ case REV_ID_MAJOR_AR9330: -+ case REV_ID_MAJOR_AR9331: -+ uart_en = AR933X_GPIO_FUNC_UART_EN; -+ break; -+ -+ case REV_ID_MAJOR_AR9341: -+ case REV_ID_MAJOR_AR9342: -+ case REV_ID_MAJOR_AR9344: -+ /* TODO */ -+ default: -+ return; -+ } -+ -+ gpio_base = (void __iomem *)(KSEG1ADDR(AR71XX_GPIO_BASE)); -+ t = __raw_readl(gpio_base + AR71XX_GPIO_REG_FUNC); -+ t |= uart_en; -+ __raw_writel(t, gpio_base + AR71XX_GPIO_REG_FUNC); -+} -+ - static void prom_putchar_init(void) - { - void __iomem *base; -@@ -88,8 +128,10 @@ static void prom_putchar_init(void) - - default: - _prom_putchar = prom_putchar_dummy; -- break; -+ return; - } -+ -+ prom_enable_uart(id); - } - - void prom_putchar(unsigned char ch) diff --git a/target/linux/ar71xx/patches-4.9/522-MIPS-ath79-add-ath79_wmac_register_simple-helper.patch b/target/linux/ar71xx/patches-4.9/522-MIPS-ath79-add-ath79_wmac_register_simple-helper.patch deleted file mode 100644 index 2d5559cb9d..0000000000 --- a/target/linux/ar71xx/patches-4.9/522-MIPS-ath79-add-ath79_wmac_register_simple-helper.patch +++ /dev/null @@ -1,21 +0,0 @@ ---- a/arch/mips/ath79/dev-wmac.c -+++ b/arch/mips/ath79/dev-wmac.c -@@ -190,3 +190,9 @@ void __init ath79_register_wmac(u8 *cal_ - - platform_device_register(&ath79_wmac_device); - } -+ -+void __init ath79_register_wmac_simple(void) -+{ -+ ath79_register_wmac(NULL, NULL); -+ ath79_wmac_data.eeprom_name = "soc_wmac.eeprom"; -+} ---- a/arch/mips/ath79/dev-wmac.h -+++ b/arch/mips/ath79/dev-wmac.h -@@ -13,5 +13,6 @@ - #define _ATH79_DEV_WMAC_H - - void ath79_register_wmac(u8 *cal_data, u8 *mac_addr); -+void ath79_register_wmac_simple(void); - - #endif /* _ATH79_DEV_WMAC_H */ diff --git a/target/linux/ar71xx/patches-4.9/523-MIPS-ath79-OTP-support.patch b/target/linux/ar71xx/patches-4.9/523-MIPS-ath79-OTP-support.patch deleted file mode 100644 index d11d418f17..0000000000 --- a/target/linux/ar71xx/patches-4.9/523-MIPS-ath79-OTP-support.patch +++ /dev/null @@ -1,192 +0,0 @@ ---- a/arch/mips/ath79/dev-wmac.c -+++ b/arch/mips/ath79/dev-wmac.c -@@ -166,6 +166,149 @@ static void qca955x_wmac_setup(void) - ath79_wmac_data.is_clk_25mhz = true; - } - -+#define AR93XX_WMAC_SIZE \ -+ (soc_is_ar934x() ? AR934X_WMAC_SIZE : AR933X_WMAC_SIZE) -+#define AR93XX_WMAC_BASE \ -+ (soc_is_ar934x() ? AR934X_WMAC_BASE : AR933X_WMAC_BASE) -+ -+#define AR93XX_OTP_BASE \ -+ (soc_is_ar934x() ? AR934X_OTP_BASE : AR9300_OTP_BASE) -+#define AR93XX_OTP_STATUS \ -+ (soc_is_ar934x() ? AR934X_OTP_STATUS : AR9300_OTP_STATUS) -+#define AR93XX_OTP_READ_DATA \ -+ (soc_is_ar934x() ? AR934X_OTP_READ_DATA : AR9300_OTP_READ_DATA) -+ -+static bool __init -+ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data) -+{ -+ int timeout = 1000; -+ u32 val; -+ -+ __raw_readl(base + AR93XX_OTP_BASE + (4 * addr)); -+ while (timeout--) { -+ val = __raw_readl(base + AR93XX_OTP_STATUS); -+ if ((val & AR9300_OTP_STATUS_TYPE) == AR9300_OTP_STATUS_VALID) -+ break; -+ -+ udelay(10); -+ } -+ -+ if (!timeout) -+ return false; -+ -+ *data = __raw_readl(base + AR93XX_OTP_READ_DATA); -+ return true; -+} -+ -+static bool __init -+ar93xx_wmac_otp_read(void __iomem *base, int addr, u8 *dest, int len) -+{ -+ u32 data; -+ int i; -+ -+ for (i = 0; i < len; i++) { -+ int offset = 8 * ((addr - i) % 4); -+ -+ if (!ar93xx_wmac_otp_read_word(base, (addr - i) / 4, &data)) -+ return false; -+ -+ dest[i] = (data >> offset) & 0xff; -+ } -+ -+ return true; -+} -+ -+static bool __init -+ar93xx_wmac_otp_uncompress(void __iomem *base, int addr, int len, u8 *dest, -+ int dest_start, int dest_len) -+{ -+ int dest_bytes = 0; -+ int offset = 0; -+ int end = addr - len; -+ u8 hdr[2]; -+ -+ while (addr > end) { -+ if (!ar93xx_wmac_otp_read(base, addr, hdr, 2)) -+ return false; -+ -+ addr -= 2; -+ offset += hdr[0]; -+ -+ if (offset <= dest_start + dest_len && -+ offset + len >= dest_start) { -+ int data_offset = 0; -+ int dest_offset = 0; -+ int copy_len; -+ -+ if (offset < dest_start) -+ data_offset = dest_start - offset; -+ else -+ dest_offset = offset - dest_start; -+ -+ copy_len = len - data_offset; -+ if (copy_len > dest_len - dest_offset) -+ copy_len = dest_len - dest_offset; -+ -+ ar93xx_wmac_otp_read(base, addr - data_offset, -+ dest + dest_offset, -+ copy_len); -+ -+ dest_bytes += copy_len; -+ } -+ addr -= hdr[1]; -+ } -+ return !!dest_bytes; -+} -+ -+bool __init ar93xx_wmac_read_mac_address(u8 *dest) -+{ -+ void __iomem *base; -+ bool ret = false; -+ int addr = 0x1ff; -+ unsigned int len; -+ u32 hdr_u32; -+ u8 *hdr = (u8 *) &hdr_u32; -+ u8 mac[6] = { 0x00, 0x02, 0x03, 0x04, 0x05, 0x06 }; -+ int mac_start = 2, mac_end = 8; -+ -+ BUG_ON(!soc_is_ar933x() && !soc_is_ar934x()); -+ base = ioremap_nocache(AR93XX_WMAC_BASE, AR93XX_WMAC_SIZE); -+ while (addr > sizeof(hdr_u32)) { -+ if (!ar93xx_wmac_otp_read(base, addr, hdr, sizeof(hdr_u32))) -+ break; -+ -+ if (hdr_u32 == 0 || hdr_u32 == ~0) -+ break; -+ -+ len = (hdr[1] << 4) | (hdr[2] >> 4); -+ addr -= 4; -+ -+ switch (hdr[0] >> 5) { -+ case 0: -+ if (len < mac_end) -+ break; -+ -+ ar93xx_wmac_otp_read(base, addr - mac_start, mac, 6); -+ ret = true; -+ break; -+ case 3: -+ ret |= ar93xx_wmac_otp_uncompress(base, addr, len, mac, -+ mac_start, 6); -+ break; -+ default: -+ break; -+ } -+ -+ addr -= len + 2; -+ } -+ -+ iounmap(base); -+ if (ret) -+ memcpy(dest, mac, 6); -+ -+ return ret; -+} -+ - void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr) - { - if (soc_is_ar913x()) ---- a/arch/mips/ath79/dev-wmac.h -+++ b/arch/mips/ath79/dev-wmac.h -@@ -14,5 +14,6 @@ - - void ath79_register_wmac(u8 *cal_data, u8 *mac_addr); - void ath79_register_wmac_simple(void); -+bool ar93xx_wmac_read_mac_address(u8 *dest); - - #endif /* _ATH79_DEV_WMAC_H */ ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -112,6 +112,14 @@ - #define QCA955X_EHCI1_BASE 0x1b400000 - #define QCA955X_EHCI_SIZE 0x1000 - -+#define AR9300_OTP_BASE 0x14000 -+#define AR9300_OTP_STATUS 0x15f18 -+#define AR9300_OTP_STATUS_TYPE 0x7 -+#define AR9300_OTP_STATUS_VALID 0x4 -+#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2 -+#define AR9300_OTP_STATUS_SM_BUSY 0x1 -+#define AR9300_OTP_READ_DATA 0x15f1c -+ - /* - * DDR_CTRL block - */ -@@ -149,6 +157,13 @@ - #define AR934X_DDR_REG_FLUSH_PCIE 0xa8 - #define AR934X_DDR_REG_FLUSH_WMAC 0xac - -+#define AR934X_OTP_BASE 0x30000 -+#define AR934X_OTP_STATUS 0x31018 -+#define AR934X_OTP_READ_DATA 0x3101c -+#define AR934X_OTP_INTF2_ADDRESS 0x31008 -+#define AR934X_OTP_INTF3_ADDRESS 0x3100c -+#define AR934X_OTP_PGENB_SETUP_HOLD_TIME_ADDRESS 0x31034 -+ - /* - * PLL block - */ diff --git a/target/linux/ar71xx/patches-4.9/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch b/target/linux/ar71xx/patches-4.9/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch deleted file mode 100644 index 91e037e247..0000000000 --- a/target/linux/ar71xx/patches-4.9/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch +++ /dev/null @@ -1,31 +0,0 @@ ---- a/arch/mips/ath79/dev-wmac.c -+++ b/arch/mips/ath79/dev-wmac.c -@@ -309,6 +309,16 @@ bool __init ar93xx_wmac_read_mac_address - return ret; - } - -+void __init ath79_wmac_disable_2ghz(void) -+{ -+ ath79_wmac_data.disable_2ghz = true; -+} -+ -+void __init ath79_wmac_disable_5ghz(void) -+{ -+ ath79_wmac_data.disable_5ghz = true; -+} -+ - void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr) - { - if (soc_is_ar913x()) ---- a/arch/mips/ath79/dev-wmac.h -+++ b/arch/mips/ath79/dev-wmac.h -@@ -14,6 +14,9 @@ - - void ath79_register_wmac(u8 *cal_data, u8 *mac_addr); - void ath79_register_wmac_simple(void); -+void ath79_wmac_disable_2ghz(void); -+void ath79_wmac_disable_5ghz(void); -+ - bool ar93xx_wmac_read_mac_address(u8 *dest); - - #endif /* _ATH79_DEV_WMAC_H */ diff --git a/target/linux/ar71xx/patches-4.9/525-MIPS-ath79-enable-qca-usb-quirks.patch b/target/linux/ar71xx/patches-4.9/525-MIPS-ath79-enable-qca-usb-quirks.patch deleted file mode 100644 index 0e33674adf..0000000000 --- a/target/linux/ar71xx/patches-4.9/525-MIPS-ath79-enable-qca-usb-quirks.patch +++ /dev/null @@ -1,101 +0,0 @@ ---- a/arch/mips/ath79/dev-usb.c -+++ b/arch/mips/ath79/dev-usb.c -@@ -37,6 +37,8 @@ static struct usb_ehci_pdata ath79_ehci_ - static struct usb_ehci_pdata ath79_ehci_pdata_v2 = { - .caps_offset = 0x100, - .has_tt = 1, -+ .qca_force_host_mode = 1, -+ .qca_force_16bit_ptw = 1, - }; - - static void __init ath79_usb_register(const char *name, int id, -@@ -159,6 +161,9 @@ static void __init ar913x_usb_setup(void - ath79_device_reset_clear(AR913X_RESET_USB_PHY); - mdelay(10); - -+ ath79_ehci_pdata_v2.qca_force_host_mode = 0; -+ ath79_ehci_pdata_v2.qca_force_16bit_ptw = 0; -+ - ath79_usb_register("ehci-platform", -1, - AR913X_EHCI_BASE, AR913X_EHCI_SIZE, - ATH79_CPU_IRQ(3), -@@ -182,14 +187,34 @@ static void __init ar933x_usb_setup(void - &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); - } - --static void __init ar934x_usb_setup(void) -+static void enable_tx_tx_idp_violation_fix(unsigned base) - { -- u32 bootstrap; -+ void __iomem *phy_reg; -+ u32 t; -+ -+ phy_reg = ioremap(base, 4); -+ if (!phy_reg) -+ return; -+ -+ t = ioread32(phy_reg); -+ t &= ~0xff; -+ t |= 0x58; -+ iowrite32(t, phy_reg); -+ -+ iounmap(phy_reg); -+} - -- bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); -- if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE) -+static void ar934x_usb_reset_notifier(struct platform_device *pdev) -+{ -+ if (pdev->id != -1) - return; - -+ enable_tx_tx_idp_violation_fix(0x18116c94); -+ dev_info(&pdev->dev, "TX-TX IDP fix enabled\n"); -+} -+ -+static void __init ar934x_usb_setup(void) -+{ - ath79_device_reset_set(AR934X_RESET_USBSUS_OVERRIDE); - udelay(1000); - -@@ -202,14 +227,40 @@ static void __init ar934x_usb_setup(void - ath79_device_reset_clear(AR934X_RESET_USB_HOST); - udelay(1000); - -+ if (ath79_soc_rev >= 3) -+ ath79_ehci_pdata_v2.reset_notifier = ar934x_usb_reset_notifier; -+ - ath79_usb_register("ehci-platform", -1, - AR934X_EHCI_BASE, AR934X_EHCI_SIZE, - ATH79_CPU_IRQ(3), - &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); - } - -+static void qca955x_usb_reset_notifier(struct platform_device *pdev) -+{ -+ u32 base; -+ -+ switch (pdev->id) { -+ case 0: -+ base = 0x18116c94; -+ break; -+ -+ case 1: -+ base = 0x18116e54; -+ break; -+ -+ default: -+ return; -+ } -+ -+ enable_tx_tx_idp_violation_fix(base); -+ dev_info(&pdev->dev, "TX-TX IDP fix enabled\n"); -+} -+ - static void __init qca955x_usb_setup(void) - { -+ ath79_ehci_pdata_v2.reset_notifier = qca955x_usb_reset_notifier; -+ - ath79_usb_register("ehci-platform", 0, - QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE, - ATH79_IP3_IRQ(0), diff --git a/target/linux/ar71xx/patches-4.9/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-4.9/601-MIPS-ath79-add-more-register-defines.patch deleted file mode 100644 index d0f5b78901..0000000000 --- a/target/linux/ar71xx/patches-4.9/601-MIPS-ath79-add-more-register-defines.patch +++ /dev/null @@ -1,455 +0,0 @@ ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -20,6 +20,10 @@ - #include <linux/bitops.h> - - #define AR71XX_APB_BASE 0x18000000 -+#define AR71XX_GE0_BASE 0x19000000 -+#define AR71XX_GE0_SIZE 0x10000 -+#define AR71XX_GE1_BASE 0x1a000000 -+#define AR71XX_GE1_SIZE 0x10000 - #define AR71XX_EHCI_BASE 0x1b000000 - #define AR71XX_EHCI_SIZE 0x1000 - #define AR71XX_OHCI_BASE 0x1c000000 -@@ -39,6 +43,8 @@ - #define AR71XX_PLL_SIZE 0x100 - #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) - #define AR71XX_RESET_SIZE 0x100 -+#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000) -+#define AR71XX_MII_SIZE 0x100 - - #define AR71XX_PCI_MEM_BASE 0x10000000 - #define AR71XX_PCI_MEM_SIZE 0x07000000 -@@ -81,15 +87,21 @@ - - #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) - #define AR933X_UART_SIZE 0x14 -+#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) -+#define AR933X_GMAC_SIZE 0x04 - #define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) - #define AR933X_WMAC_SIZE 0x20000 - #define AR933X_EHCI_BASE 0x1b000000 - #define AR933X_EHCI_SIZE 0x1000 - -+#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) -+#define AR934X_GMAC_SIZE 0x14 - #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) - #define AR934X_WMAC_SIZE 0x20000 - #define AR934X_EHCI_BASE 0x1b000000 - #define AR934X_EHCI_SIZE 0x200 -+#define AR934X_NFC_BASE 0x1b000200 -+#define AR934X_NFC_SIZE 0xb8 - #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) - #define AR934X_SRIF_SIZE 0x1000 - -@@ -106,11 +118,15 @@ - #define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) - #define QCA955X_PCI_CTRL_SIZE 0x100 - -+#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) -+#define QCA955X_GMAC_SIZE 0x40 - #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) - #define QCA955X_WMAC_SIZE 0x20000 - #define QCA955X_EHCI0_BASE 0x1b000000 - #define QCA955X_EHCI1_BASE 0x1b400000 - #define QCA955X_EHCI_SIZE 0x1000 -+#define QCA955X_NFC_BASE 0x1b800200 -+#define QCA955X_NFC_SIZE 0xb8 - - #define AR9300_OTP_BASE 0x14000 - #define AR9300_OTP_STATUS 0x15f18 -@@ -181,6 +197,9 @@ - #define AR71XX_AHB_DIV_SHIFT 20 - #define AR71XX_AHB_DIV_MASK 0x7 - -+#define AR71XX_ETH0_PLL_SHIFT 17 -+#define AR71XX_ETH1_PLL_SHIFT 19 -+ - #define AR724X_PLL_REG_CPU_CONFIG 0x00 - #define AR724X_PLL_REG_PCIE_CONFIG 0x10 - -@@ -196,6 +215,8 @@ - #define AR724X_DDR_DIV_SHIFT 22 - #define AR724X_DDR_DIV_MASK 0x3 - -+#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c -+ - #define AR913X_PLL_REG_CPU_CONFIG 0x00 - #define AR913X_PLL_REG_ETH_CONFIG 0x04 - #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 -@@ -208,6 +229,9 @@ - #define AR913X_AHB_DIV_SHIFT 19 - #define AR913X_AHB_DIV_MASK 0x1 - -+#define AR913X_ETH0_PLL_SHIFT 20 -+#define AR913X_ETH1_PLL_SHIFT 22 -+ - #define AR933X_PLL_CPU_CONFIG_REG 0x00 - #define AR933X_PLL_CLOCK_CTRL_REG 0x08 - -@@ -229,6 +253,8 @@ - #define AR934X_PLL_CPU_CONFIG_REG 0x00 - #define AR934X_PLL_DDR_CONFIG_REG 0x04 - #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 -+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 -+#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c - - #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 - #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f -@@ -261,9 +287,13 @@ - #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) - #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) - -+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6) -+ - #define QCA955X_PLL_CPU_CONFIG_REG 0x00 - #define QCA955X_PLL_DDR_CONFIG_REG 0x04 - #define QCA955X_PLL_CLK_CTRL_REG 0x08 -+#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28 -+#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48 - - #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 - #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f -@@ -388,16 +418,83 @@ - #define AR913X_RESET_USB_HOST BIT(5) - #define AR913X_RESET_USB_PHY BIT(4) - -+#define AR933X_RESET_GE1_MDIO BIT(23) -+#define AR933X_RESET_GE0_MDIO BIT(22) -+#define AR933X_RESET_GE1_MAC BIT(13) - #define AR933X_RESET_WMAC BIT(11) -+#define AR933X_RESET_GE0_MAC BIT(9) - #define AR933X_RESET_USB_HOST BIT(5) - #define AR933X_RESET_USB_PHY BIT(4) - #define AR933X_RESET_USBSUS_OVERRIDE BIT(3) - -+#define AR934X_RESET_HOST BIT(31) -+#define AR934X_RESET_SLIC BIT(30) -+#define AR934X_RESET_HDMA BIT(29) -+#define AR934X_RESET_EXTERNAL BIT(28) -+#define AR934X_RESET_RTC BIT(27) -+#define AR934X_RESET_PCIE_EP_INT BIT(26) -+#define AR934X_RESET_CHKSUM_ACC BIT(25) -+#define AR934X_RESET_FULL_CHIP BIT(24) -+#define AR934X_RESET_GE1_MDIO BIT(23) -+#define AR934X_RESET_GE0_MDIO BIT(22) -+#define AR934X_RESET_CPU_NMI BIT(21) -+#define AR934X_RESET_CPU_COLD BIT(20) -+#define AR934X_RESET_HOST_RESET_INT BIT(19) -+#define AR934X_RESET_PCIE_EP BIT(18) -+#define AR934X_RESET_UART1 BIT(17) -+#define AR934X_RESET_DDR BIT(16) -+#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) -+#define AR934X_RESET_NANDF BIT(14) -+#define AR934X_RESET_GE1_MAC BIT(13) -+#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12) - #define AR934X_RESET_USB_PHY_ANALOG BIT(11) -+#define AR934X_RESET_HOST_DMA_INT BIT(10) -+#define AR934X_RESET_GE0_MAC BIT(9) -+#define AR934X_RESET_ETH_SWITCH BIT(8) -+#define AR934X_RESET_PCIE_PHY BIT(7) -+#define AR934X_RESET_PCIE BIT(6) - #define AR934X_RESET_USB_HOST BIT(5) - #define AR934X_RESET_USB_PHY BIT(4) - #define AR934X_RESET_USBSUS_OVERRIDE BIT(3) -+#define AR934X_RESET_LUT BIT(2) -+#define AR934X_RESET_MBOX BIT(1) -+#define AR934X_RESET_I2S BIT(0) -+ -+#define QCA955X_RESET_HOST BIT(31) -+#define QCA955X_RESET_SLIC BIT(30) -+#define QCA955X_RESET_HDMA BIT(29) -+#define QCA955X_RESET_EXTERNAL BIT(28) -+#define QCA955X_RESET_RTC BIT(27) -+#define QCA955X_RESET_PCIE_EP_INT BIT(26) -+#define QCA955X_RESET_CHKSUM_ACC BIT(25) -+#define QCA955X_RESET_FULL_CHIP BIT(24) -+#define QCA955X_RESET_GE1_MDIO BIT(23) -+#define QCA955X_RESET_GE0_MDIO BIT(22) -+#define QCA955X_RESET_CPU_NMI BIT(21) -+#define QCA955X_RESET_CPU_COLD BIT(20) -+#define QCA955X_RESET_HOST_RESET_INT BIT(19) -+#define QCA955X_RESET_PCIE_EP BIT(18) -+#define QCA955X_RESET_UART1 BIT(17) -+#define QCA955X_RESET_DDR BIT(16) -+#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) -+#define QCA955X_RESET_NANDF BIT(14) -+#define QCA955X_RESET_GE1_MAC BIT(13) -+#define QCA955X_RESET_SGMII_ANALOG BIT(12) -+#define QCA955X_RESET_USB_PHY_ANALOG BIT(11) -+#define QCA955X_RESET_HOST_DMA_INT BIT(10) -+#define QCA955X_RESET_GE0_MAC BIT(9) -+#define QCA955X_RESET_SGMII BIT(8) -+#define QCA955X_RESET_PCIE_PHY BIT(7) -+#define QCA955X_RESET_PCIE BIT(6) -+#define QCA955X_RESET_USB_HOST BIT(5) -+#define QCA955X_RESET_USB_PHY BIT(4) -+#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3) -+#define QCA955X_RESET_LUT BIT(2) -+#define QCA955X_RESET_MBOX BIT(1) -+#define QCA955X_RESET_I2S BIT(0) - -+#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) -+#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) - #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) - - #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) -@@ -539,8 +636,22 @@ - #define AR71XX_GPIO_REG_INT_ENABLE 0x24 - #define AR71XX_GPIO_REG_FUNC 0x28 - -+#define AR934X_GPIO_REG_OUT_FUNC0 0x2c -+#define AR934X_GPIO_REG_OUT_FUNC1 0x30 -+#define AR934X_GPIO_REG_OUT_FUNC2 0x34 -+#define AR934X_GPIO_REG_OUT_FUNC3 0x38 -+#define AR934X_GPIO_REG_OUT_FUNC4 0x3c -+#define AR934X_GPIO_REG_OUT_FUNC5 0x40 - #define AR934X_GPIO_REG_FUNC 0x6c - -+#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c -+#define QCA955X_GPIO_REG_OUT_FUNC1 0x30 -+#define QCA955X_GPIO_REG_OUT_FUNC2 0x34 -+#define QCA955X_GPIO_REG_OUT_FUNC3 0x38 -+#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c -+#define QCA955X_GPIO_REG_OUT_FUNC5 0x40 -+#define QCA955X_GPIO_REG_FUNC 0x6c -+ - #define AR71XX_GPIO_COUNT 16 - #define AR7240_GPIO_COUNT 18 - #define AR7241_GPIO_COUNT 20 -@@ -570,4 +681,235 @@ - #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 - #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 - -+#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) -+#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) -+#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) -+#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) -+#define AR71XX_GPIO_FUNC_UART_EN BIT(8) -+#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) -+#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) -+ -+#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) -+#define AR724X_GPIO_FUNC_SPI_EN BIT(18) -+#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) -+#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) -+#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) -+#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) -+#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) -+#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) -+#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) -+#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) -+#define AR724X_GPIO_FUNC_UART_EN BIT(1) -+#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) -+ -+#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22) -+#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) -+#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20) -+#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19) -+#define AR913X_GPIO_FUNC_I2S1_EN BIT(18) -+#define AR913X_GPIO_FUNC_I2S0_EN BIT(17) -+#define AR913X_GPIO_FUNC_SLIC_EN BIT(16) -+#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9) -+#define AR913X_GPIO_FUNC_UART_EN BIT(8) -+#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4) -+ -+#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31) -+#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30) -+#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29) -+#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27) -+#define AR933X_GPIO_FUNC_I2SO_EN BIT(26) -+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25) -+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24) -+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23) -+#define AR933X_GPIO_FUNC_SPI_EN BIT(18) -+#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14) -+#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13) -+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) -+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) -+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) -+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) -+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) -+#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) -+#define AR933X_GPIO_FUNC_UART_EN BIT(1) -+#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0) -+ -+#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9) -+#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8) -+#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7) -+#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6) -+#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5) -+#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4) -+#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3) -+#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2) -+#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1) -+ -+#define AR934X_GPIO_OUT_GPIO 0 -+#define AR934X_GPIO_OUT_SPI_CS1 7 -+#define AR934X_GPIO_OUT_LED_LINK0 41 -+#define AR934X_GPIO_OUT_LED_LINK1 42 -+#define AR934X_GPIO_OUT_LED_LINK2 43 -+#define AR934X_GPIO_OUT_LED_LINK3 44 -+#define AR934X_GPIO_OUT_LED_LINK4 45 -+#define AR934X_GPIO_OUT_EXT_LNA0 46 -+#define AR934X_GPIO_OUT_EXT_LNA1 47 -+ -+#define QCA955X_GPIO_FUNC_CLK_OBS7_EN BIT(9) -+#define QCA955X_GPIO_FUNC_CLK_OBS6_EN BIT(8) -+#define QCA955X_GPIO_FUNC_CLK_OBS5_EN BIT(7) -+#define QCA955X_GPIO_FUNC_CLK_OBS4_EN BIT(6) -+#define QCA955X_GPIO_FUNC_CLK_OBS3_EN BIT(5) -+#define QCA955X_GPIO_FUNC_CLK_OBS2_EN BIT(4) -+#define QCA955X_GPIO_FUNC_CLK_OBS1_EN BIT(3) -+#define QCA955X_GPIO_FUNC_JTAG_DISABLE BIT(1) -+ -+#define QCA955X_GPIO_OUT_GPIO 0 -+#define QCA955X_MII_EXT_MDI 1 -+#define QCA955X_SLIC_DATA_OUT 3 -+#define QCA955X_SLIC_PCM_FS 4 -+#define QCA955X_SLIC_PCM_CLK 5 -+#define QCA955X_SPI_CLK 8 -+#define QCA955X_SPI_CS_0 9 -+#define QCA955X_SPI_CS_1 10 -+#define QCA955X_SPI_CS_2 11 -+#define QCA955X_SPI_MISO 12 -+#define QCA955X_I2S_CLK 13 -+#define QCA955X_I2S_WS 14 -+#define QCA955X_I2S_SD 15 -+#define QCA955X_I2S_MCK 16 -+#define QCA955X_SPDIF_OUT 17 -+#define QCA955X_UART1_TD 18 -+#define QCA955X_UART1_RTS 19 -+#define QCA955X_UART1_RD 20 -+#define QCA955X_UART1_CTS 21 -+#define QCA955X_UART0_SOUT 22 -+#define QCA955X_SPDIF2_OUT 23 -+#define QCA955X_LED_SGMII_SPEED0 24 -+#define QCA955X_LED_SGMII_SPEED1 25 -+#define QCA955X_LED_SGMII_DUPLEX 26 -+#define QCA955X_LED_SGMII_LINK_UP 27 -+#define QCA955X_SGMII_SPEED0_INVERT 28 -+#define QCA955X_SGMII_SPEED1_INVERT 29 -+#define QCA955X_SGMII_DUPLEX_INVERT 30 -+#define QCA955X_SGMII_LINK_UP_INVERT 31 -+#define QCA955X_GE1_MII_MDO 32 -+#define QCA955X_GE1_MII_MDC 33 -+#define QCA955X_SWCOM2 38 -+#define QCA955X_SWCOM3 39 -+#define QCA955X_MAC2_GPIO 40 -+#define QCA955X_MAC3_GPIO 41 -+#define QCA955X_ATT_LED 42 -+#define QCA955X_PWR_LED 43 -+#define QCA955X_TX_FRAME 44 -+#define QCA955X_RX_CLEAR_EXTERNAL 45 -+#define QCA955X_LED_NETWORK_EN 46 -+#define QCA955X_LED_POWER_EN 47 -+#define QCA955X_WMAC_GLUE_WOW 68 -+#define QCA955X_RX_CLEAR_EXTENSION 70 -+#define QCA955X_CP_NAND_CS1 73 -+#define QCA955X_USB_SUSPEND 74 -+#define QCA955X_ETH_TX_ERR 75 -+#define QCA955X_DDR_DQ_OE 76 -+#define QCA955X_CLKREQ_N_EP 77 -+#define QCA955X_CLKREQ_N_RC 78 -+#define QCA955X_CLK_OBS0 79 -+#define QCA955X_CLK_OBS1 80 -+#define QCA955X_CLK_OBS2 81 -+#define QCA955X_CLK_OBS3 82 -+#define QCA955X_CLK_OBS4 83 -+#define QCA955X_CLK_OBS5 84 -+ -+/* -+ * MII_CTRL block -+ */ -+#define AR71XX_MII_REG_MII0_CTRL 0x00 -+#define AR71XX_MII_REG_MII1_CTRL 0x04 -+ -+#define AR71XX_MII_CTRL_IF_MASK 3 -+#define AR71XX_MII_CTRL_SPEED_SHIFT 4 -+#define AR71XX_MII_CTRL_SPEED_MASK 3 -+#define AR71XX_MII_CTRL_SPEED_10 0 -+#define AR71XX_MII_CTRL_SPEED_100 1 -+#define AR71XX_MII_CTRL_SPEED_1000 2 -+ -+#define AR71XX_MII0_CTRL_IF_GMII 0 -+#define AR71XX_MII0_CTRL_IF_MII 1 -+#define AR71XX_MII0_CTRL_IF_RGMII 2 -+#define AR71XX_MII0_CTRL_IF_RMII 3 -+ -+#define AR71XX_MII1_CTRL_IF_RGMII 0 -+#define AR71XX_MII1_CTRL_IF_RMII 1 -+ -+/* -+ * AR933X GMAC interface -+ */ -+#define AR933X_GMAC_REG_ETH_CFG 0x00 -+ -+#define AR933X_ETH_CFG_RGMII_GE0 BIT(0) -+#define AR933X_ETH_CFG_MII_GE0 BIT(1) -+#define AR933X_ETH_CFG_GMII_GE0 BIT(2) -+#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3) -+#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4) -+#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5) -+#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7) -+#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) -+#define AR933X_ETH_CFG_RMII_GE0 BIT(9) -+#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 -+#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10) -+ -+/* -+ * AR934X GMAC Interface -+ */ -+#define AR934X_GMAC_REG_ETH_CFG 0x00 -+ -+#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0) -+#define AR934X_ETH_CFG_MII_GMAC0 BIT(1) -+#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2) -+#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3) -+#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4) -+#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5) -+#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6) -+#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7) -+#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9) -+#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10) -+#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11) -+#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12) -+#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) -+#define AR934X_ETH_CFG_RXD_DELAY BIT(14) -+#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3 -+#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14 -+#define AR934X_ETH_CFG_RDV_DELAY BIT(16) -+#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3 -+#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16 -+ -+/* -+ * QCA955X GMAC Interface -+ */ -+ -+#define QCA955X_GMAC_REG_ETH_CFG 0x00 -+ -+#define QCA955X_ETH_CFG_RGMII_EN BIT(0) -+#define QCA955X_ETH_CFG_MII_GE0 BIT(1) -+#define QCA955X_ETH_CFG_GMII_GE0 BIT(2) -+#define QCA955X_ETH_CFG_MII_GE0_MASTER BIT(3) -+#define QCA955X_ETH_CFG_MII_GE0_SLAVE BIT(4) -+#define QCA955X_ETH_CFG_GE0_ERR_EN BIT(5) -+#define QCA955X_ETH_CFG_GE0_SGMII BIT(6) -+#define QCA955X_ETH_CFG_RMII_GE0 BIT(10) -+#define QCA955X_ETH_CFG_MII_CNTL_SPEED BIT(11) -+#define QCA955X_ETH_CFG_RMII_GE0_MASTER BIT(12) -+#define QCA955X_ETH_CFG_RXD_DELAY_MASK 0x3 -+#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT 14 -+#define QCA955X_ETH_CFG_RDV_DELAY BIT(16) -+#define QCA955X_ETH_CFG_RDV_DELAY_MASK 0x3 -+#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT 16 -+#define QCA955X_ETH_CFG_TXD_DELAY_MASK 0x3 -+#define QCA955X_ETH_CFG_TXD_DELAY_SHIFT 18 -+#define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3 -+#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20 -+ - #endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/target/linux/ar71xx/patches-4.9/602-MIPS-ath79-add-openwrt-stuff.patch b/target/linux/ar71xx/patches-4.9/602-MIPS-ath79-add-openwrt-stuff.patch deleted file mode 100644 index cbd69e337b..0000000000 --- a/target/linux/ar71xx/patches-4.9/602-MIPS-ath79-add-openwrt-stuff.patch +++ /dev/null @@ -1,49 +0,0 @@ ---- a/arch/mips/ath79/Kconfig -+++ b/arch/mips/ath79/Kconfig -@@ -98,6 +98,20 @@ config SOC_QCA955X - select PCI_AR724X if PCI - def_bool n - -+config ATH79_DEV_M25P80 -+ select ATH79_DEV_SPI -+ def_bool n -+ -+config ATH79_DEV_AP9X_PCI -+ select ATH79_PCI_ATH9K_FIXUP -+ def_bool n -+ -+config ATH79_DEV_DSA -+ def_bool n -+ -+config ATH79_DEV_ETH -+ def_bool n -+ - config PCI_AR724X - def_bool n - -@@ -107,6 +121,10 @@ config ATH79_DEV_GPIO_BUTTONS - config ATH79_DEV_LEDS_GPIO - def_bool n - -+config ATH79_DEV_NFC -+ depends on (SOC_AR934X || SOC_QCA955X) -+ def_bool n -+ - config ATH79_DEV_SPI - def_bool n - -@@ -117,4 +135,14 @@ config ATH79_DEV_WMAC - depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X) - def_bool n - -+config ATH79_NVRAM -+ def_bool n -+ -+config ATH79_PCI_ATH9K_FIXUP -+ def_bool n -+ -+config ATH79_ROUTERBOOT -+ select LZO_DECOMPRESS -+ def_bool n -+ - endif diff --git a/target/linux/ar71xx/patches-4.9/603-MIPS-ath79-ap121-fixes.patch b/target/linux/ar71xx/patches-4.9/603-MIPS-ath79-ap121-fixes.patch deleted file mode 100644 index 773a858ae1..0000000000 --- a/target/linux/ar71xx/patches-4.9/603-MIPS-ath79-ap121-fixes.patch +++ /dev/null @@ -1,149 +0,0 @@ ---- a/arch/mips/ath79/mach-ap121.c -+++ b/arch/mips/ath79/mach-ap121.c -@@ -1,19 +1,21 @@ - /* - * Atheros AP121 board support - * -- * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> -+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - --#include "machtypes.h" -+#include "dev-eth.h" - #include "dev-gpio-buttons.h" - #include "dev-leds-gpio.h" -+#include "dev-m25p80.h" - #include "dev-spi.h" - #include "dev-usb.h" - #include "dev-wmac.h" -+#include "machtypes.h" - - #define AP121_GPIO_LED_WLAN 0 - #define AP121_GPIO_LED_USB 1 -@@ -24,7 +26,14 @@ - #define AP121_KEYS_POLL_INTERVAL 20 /* msecs */ - #define AP121_KEYS_DEBOUNCE_INTERVAL (3 * AP121_KEYS_POLL_INTERVAL) - --#define AP121_CAL_DATA_ADDR 0x1fff1000 -+#define AP121_MAC0_OFFSET 0x0000 -+#define AP121_MAC1_OFFSET 0x0006 -+#define AP121_CALDATA_OFFSET 0x1000 -+#define AP121_WMAC_MAC_OFFSET 0x1002 -+ -+#define AP121_MINI_GPIO_LED_WLAN 0 -+#define AP121_MINI_GPIO_BTN_JUMPSTART 12 -+#define AP121_MINI_GPIO_BTN_RESET 11 - - static struct gpio_led ap121_leds_gpio[] __initdata = { - { -@@ -58,35 +67,78 @@ static struct gpio_keys_button ap121_gpi - } - }; - --static struct spi_board_info ap121_spi_info[] = { -+static struct gpio_led ap121_mini_leds_gpio[] __initdata = { - { -- .bus_num = 0, -- .chip_select = 0, -- .max_speed_hz = 25000000, -- .modalias = "mx25l1606e", -- } -+ .name = "ap121:green:wlan", -+ .gpio = AP121_MINI_GPIO_LED_WLAN, -+ .active_low = 0, -+ }, - }; - --static struct ath79_spi_platform_data ap121_spi_data = { -- .bus_num = 0, -- .num_chipselect = 1, -+static struct gpio_keys_button ap121_mini_gpio_keys[] __initdata = { -+ { -+ .desc = "jumpstart button", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = AP121_MINI_GPIO_BTN_JUMPSTART, -+ .active_low = 1, -+ }, -+ { -+ .desc = "reset button", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = AP121_MINI_GPIO_BTN_RESET, -+ .active_low = 1, -+ } - }; - -+static void __init ap121_common_setup(void) -+{ -+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); -+ -+ ath79_register_m25p80(NULL); -+ ath79_register_wmac(art + AP121_CALDATA_OFFSET, -+ art + AP121_WMAC_MAC_OFFSET); -+ -+ ath79_init_mac(ath79_eth0_data.mac_addr, art + AP121_MAC0_OFFSET, 0); -+ ath79_init_mac(ath79_eth1_data.mac_addr, art + AP121_MAC1_OFFSET, 0); -+ -+ ath79_register_mdio(0, 0x0); -+ -+ /* LAN ports */ -+ ath79_register_eth(1); -+ -+ /* WAN port */ -+ ath79_register_eth(0); -+} -+ - static void __init ap121_setup(void) - { -- u8 *cal_data = (u8 *) KSEG1ADDR(AP121_CAL_DATA_ADDR); -+ ap121_common_setup(); - - ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio), - ap121_leds_gpio); - ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL, - ARRAY_SIZE(ap121_gpio_keys), - ap121_gpio_keys); -- -- ath79_register_spi(&ap121_spi_data, ap121_spi_info, -- ARRAY_SIZE(ap121_spi_info)); - ath79_register_usb(); -- ath79_register_wmac(cal_data, NULL); - } - - MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board", - ap121_setup); -+ -+static void __init ap121_mini_setup(void) -+{ -+ ap121_common_setup(); -+ -+ ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_mini_leds_gpio), -+ ap121_mini_leds_gpio); -+ ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(ap121_mini_gpio_keys), -+ ap121_mini_gpio_keys); -+} -+ -+MIPS_MACHINE(ATH79_MACH_AP121_MINI, "AP121-MINI", "Atheros AP121-MINI", -+ ap121_mini_setup); ---- a/arch/mips/ath79/Kconfig -+++ b/arch/mips/ath79/Kconfig -@@ -5,9 +5,10 @@ menu "Atheros AR71XX/AR724X/AR913X machi - config ATH79_MACH_AP121 - bool "Atheros AP121 reference board" - select SOC_AR933X -+ select ATH79_DEV_ETH - select ATH79_DEV_GPIO_BUTTONS - select ATH79_DEV_LEDS_GPIO -- select ATH79_DEV_SPI -+ select ATH79_DEV_M25P80 - select ATH79_DEV_USB - select ATH79_DEV_WMAC - help diff --git a/target/linux/ar71xx/patches-4.9/604-MIPS-ath79-no-of.patch b/target/linux/ar71xx/patches-4.9/604-MIPS-ath79-no-of.patch deleted file mode 100644 index 89dd32a7c1..0000000000 --- a/target/linux/ar71xx/patches-4.9/604-MIPS-ath79-no-of.patch +++ /dev/null @@ -1,70 +0,0 @@ ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -196,7 +196,6 @@ config ATH79 - select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_MIPS16 - select SYS_SUPPORTS_ZBOOT_UART_PROM -- select USE_OF - help - Support for the Atheros AR71XX/AR724X/AR913X SoCs. - ---- a/arch/mips/ath79/setup.c -+++ b/arch/mips/ath79/setup.c -@@ -196,16 +196,20 @@ unsigned int get_c0_compare_int(void) - - void __init plat_mem_setup(void) - { -+#ifdef CONFIG_OF - unsigned long fdt_start; -+#endif - - set_io_port_base(KSEG1); - -+#ifdef CONFIG_OF - /* Get the position of the FDT passed by the bootloader */ - fdt_start = fw_getenvl("fdt_start"); - if (fdt_start) - __dt_setup_arch((void *)KSEG0ADDR(fdt_start)); - else if (fw_passed_dtb) - __dt_setup_arch((void *)KSEG0ADDR(fw_passed_dtb)); -+#endif - - if (mips_machtype != ATH79_MACH_GENERIC_OF) { - ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE, -@@ -301,17 +305,21 @@ static int __init ath79_setup(void) - - arch_initcall(ath79_setup); - -+#ifdef CONFIG_OF - void __init device_tree_init(void) - { - unflatten_and_copy_device_tree(); - } -+#endif - - MIPS_MACHINE(ATH79_MACH_GENERIC, - "Generic", - "Generic AR71XX/AR724X/AR913X based board", - NULL); - -+#ifdef CONFIG_OF - MIPS_MACHINE(ATH79_MACH_GENERIC_OF, - "DTB", - "Generic AR71XX/AR724X/AR913X based board (DT)", - NULL); -+#endif ---- a/arch/mips/ath79/clock.c -+++ b/arch/mips/ath79/clock.c -@@ -33,10 +33,12 @@ - #define AR724X_BASE_FREQ 40000000 - - static struct clk *clks[ATH79_CLK_END]; -+#ifdef CONFIG_OF - static struct clk_onecell_data clk_data = { - .clks = clks, - .clk_num = ARRAY_SIZE(clks), - }; -+#endif - - static struct clk *__init ath79_add_sys_clkdev( - const char *id, unsigned long rate) diff --git a/target/linux/ar71xx/patches-4.9/605-MIPS-ath79-db120-fixes.patch b/target/linux/ar71xx/patches-4.9/605-MIPS-ath79-db120-fixes.patch deleted file mode 100644 index 1029d43669..0000000000 --- a/target/linux/ar71xx/patches-4.9/605-MIPS-ath79-db120-fixes.patch +++ /dev/null @@ -1,204 +0,0 @@ ---- a/arch/mips/ath79/mach-db120.c -+++ b/arch/mips/ath79/mach-db120.c -@@ -2,7 +2,7 @@ - * Atheros DB120 reference board support - * - * Copyright (c) 2011 Qualcomm Atheros -- * Copyright (c) 2011 Gabor Juhos <juhosg@openwrt.org> -+ * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org> - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above -@@ -19,16 +19,26 @@ - */ - - #include <linux/pci.h> -+#include <linux/phy.h> -+#include <linux/platform_device.h> - #include <linux/ath9k_platform.h> -+#include <linux/ar8216_platform.h> - --#include "machtypes.h" -+#include <asm/mach-ath79/ar71xx_regs.h> -+ -+#include "common.h" -+#include "dev-ap9x-pci.h" -+#include "dev-eth.h" - #include "dev-gpio-buttons.h" - #include "dev-leds-gpio.h" -+#include "dev-m25p80.h" -+#include "dev-nfc.h" - #include "dev-spi.h" - #include "dev-usb.h" - #include "dev-wmac.h" --#include "pci.h" -+#include "machtypes.h" - -+#define DB120_GPIO_LED_USB 11 - #define DB120_GPIO_LED_WLAN_5G 12 - #define DB120_GPIO_LED_WLAN_2G 13 - #define DB120_GPIO_LED_STATUS 14 -@@ -39,8 +49,10 @@ - #define DB120_KEYS_POLL_INTERVAL 20 /* msecs */ - #define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL) - --#define DB120_WMAC_CALDATA_OFFSET 0x1000 --#define DB120_PCIE_CALDATA_OFFSET 0x5000 -+#define DB120_MAC0_OFFSET 0 -+#define DB120_MAC1_OFFSET 6 -+#define DB120_WMAC_CALDATA_OFFSET 0x1000 -+#define DB120_PCIE_CALDATA_OFFSET 0x5000 - - static struct gpio_led db120_leds_gpio[] __initdata = { - { -@@ -63,6 +75,11 @@ static struct gpio_led db120_leds_gpio[] - .gpio = DB120_GPIO_LED_WLAN_2G, - .active_low = 1, - }, -+ { -+ .name = "db120:green:usb", -+ .gpio = DB120_GPIO_LED_USB, -+ .active_low = 1, -+ } - }; - - static struct gpio_keys_button db120_gpio_keys[] __initdata = { -@@ -76,60 +93,85 @@ static struct gpio_keys_button db120_gpi - }, - }; - --static struct spi_board_info db120_spi_info[] = { -- { -- .bus_num = 0, -- .chip_select = 0, -- .max_speed_hz = 25000000, -- .modalias = "s25sl064a", -- } -+static struct ar8327_pad_cfg db120_ar8327_pad0_cfg = { -+ .mode = AR8327_PAD_MAC_RGMII, -+ .txclk_delay_en = true, -+ .rxclk_delay_en = true, -+ .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, -+ .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, - }; - --static struct ath79_spi_platform_data db120_spi_data = { -- .bus_num = 0, -- .num_chipselect = 1, -+static struct ar8327_led_cfg db120_ar8327_led_cfg = { -+ .led_ctrl0 = 0x00000000, -+ .led_ctrl1 = 0xc737c737, -+ .led_ctrl2 = 0x00000000, -+ .led_ctrl3 = 0x00c30c00, -+ .open_drain = true, - }; - --#ifdef CONFIG_PCI --static struct ath9k_platform_data db120_ath9k_data; -- --static int db120_pci_plat_dev_init(struct pci_dev *dev) --{ -- switch (PCI_SLOT(dev->devfn)) { -- case 0: -- dev->dev.platform_data = &db120_ath9k_data; -- break; -- } -- -- return 0; --} -- --static void __init db120_pci_init(u8 *eeprom) --{ -- memcpy(db120_ath9k_data.eeprom_data, eeprom, -- sizeof(db120_ath9k_data.eeprom_data)); -+static struct ar8327_platform_data db120_ar8327_data = { -+ .pad0_cfg = &db120_ar8327_pad0_cfg, -+ .port0_cfg = { -+ .force_link = 1, -+ .speed = AR8327_PORT_SPEED_1000, -+ .duplex = 1, -+ .txpause = 1, -+ .rxpause = 1, -+ }, -+ .led_cfg = &db120_ar8327_led_cfg, -+}; - -- ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init); -- ath79_register_pci(); --} --#else --static inline void db120_pci_init(u8 *eeprom) {} --#endif /* CONFIG_PCI */ -+static struct mdio_board_info db120_mdio0_info[] = { -+ { -+ .bus_id = "ag71xx-mdio.0", -+ .phy_addr = 0, -+ .platform_data = &db120_ar8327_data, -+ }, -+}; - - static void __init db120_setup(void) - { - u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); - -+ ath79_gpio_output_select(DB120_GPIO_LED_USB, AR934X_GPIO_OUT_GPIO); -+ ath79_register_m25p80(NULL); -+ - ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio), - db120_leds_gpio); - ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL, - ARRAY_SIZE(db120_gpio_keys), - db120_gpio_keys); -- ath79_register_spi(&db120_spi_data, db120_spi_info, -- ARRAY_SIZE(db120_spi_info)); - ath79_register_usb(); - ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL); -- db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET); -+ ap91_pci_init(art + DB120_PCIE_CALDATA_OFFSET, NULL); -+ -+ ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | -+ AR934X_ETH_CFG_SW_ONLY_MODE); -+ -+ ath79_register_mdio(1, 0x0); -+ ath79_register_mdio(0, 0x0); -+ -+ ath79_init_mac(ath79_eth0_data.mac_addr, art + DB120_MAC0_OFFSET, 0); -+ -+ mdiobus_register_board_info(db120_mdio0_info, -+ ARRAY_SIZE(db120_mdio0_info)); -+ -+ /* GMAC0 is connected to an AR8327 switch */ -+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ath79_eth0_data.phy_mask = BIT(0); -+ ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; -+ ath79_eth0_pll_data.pll_1000 = 0x06000000; -+ ath79_register_eth(0); -+ -+ /* GMAC1 is connected to the internal switch */ -+ ath79_init_mac(ath79_eth1_data.mac_addr, art + DB120_MAC1_OFFSET, 0); -+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; -+ ath79_eth1_data.speed = SPEED_1000; -+ ath79_eth1_data.duplex = DUPLEX_FULL; -+ -+ ath79_register_eth(1); -+ -+ ath79_register_nfc(); - } - - MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board", ---- a/arch/mips/ath79/Kconfig -+++ b/arch/mips/ath79/Kconfig -@@ -42,9 +42,12 @@ config ATH79_MACH_AP81 - config ATH79_MACH_DB120 - bool "Atheros DB120 reference board" - select SOC_AR934X -+ select ATH79_DEV_AP9X_PCI if PCI -+ select ATH79_DEV_ETH - select ATH79_DEV_GPIO_BUTTONS - select ATH79_DEV_LEDS_GPIO -- select ATH79_DEV_SPI -+ select ATH79_DEV_M25P80 -+ select ATH79_DEV_NFC - select ATH79_DEV_USB - select ATH79_DEV_WMAC - help diff --git a/target/linux/ar71xx/patches-4.9/606-MIPS-ath79-pb44-fixes.patch b/target/linux/ar71xx/patches-4.9/606-MIPS-ath79-pb44-fixes.patch deleted file mode 100644 index f2943d0836..0000000000 --- a/target/linux/ar71xx/patches-4.9/606-MIPS-ath79-pb44-fixes.patch +++ /dev/null @@ -1,146 +0,0 @@ ---- a/arch/mips/ath79/mach-pb44.c -+++ b/arch/mips/ath79/mach-pb44.c -@@ -8,23 +8,48 @@ - * by the Free Software Foundation. - */ - -+#include <linux/delay.h> - #include <linux/init.h> - #include <linux/platform_device.h> - #include <linux/i2c.h> - #include <linux/i2c-gpio.h> - #include <linux/i2c/pcf857x.h> -+#include <linux/i2c/pcf857x.h> -+#include <linux/spi/flash.h> -+#include <linux/spi/vsc7385.h> - --#include "machtypes.h" -+#include <asm/mach-ath79/ar71xx_regs.h> -+#include <asm/mach-ath79/ath79.h> -+ -+#include "dev-eth.h" - #include "dev-gpio-buttons.h" - #include "dev-leds-gpio.h" - #include "dev-spi.h" - #include "dev-usb.h" -+#include "machtypes.h" - #include "pci.h" - - #define PB44_GPIO_I2C_SCL 0 - #define PB44_GPIO_I2C_SDA 1 - -+#define PB44_PCF8757_VSC7395_CS 0 -+#define PB44_PCF8757_STEREO_CS 1 -+#define PB44_PCF8757_SLIC_CS0 2 -+#define PB44_PCF8757_SLIC_TEST 3 -+#define PB44_PCF8757_SLIC_INT0 4 -+#define PB44_PCF8757_SLIC_INT1 5 -+#define PB44_PCF8757_SW_RESET 6 -+#define PB44_PCF8757_SW_JUMP 8 -+#define PB44_PCF8757_LED_JUMP1 9 -+#define PB44_PCF8757_LED_JUMP2 10 -+#define PB44_PCF8757_TP24 11 -+#define PB44_PCF8757_TP25 12 -+#define PB44_PCF8757_TP26 13 -+#define PB44_PCF8757_TP27 14 -+#define PB44_PCF8757_TP28 15 -+ - #define PB44_GPIO_EXP_BASE 16 -+#define PB44_GPIO_VSC7395_CS (PB44_GPIO_EXP_BASE + PB44_PCF8757_VSC7395_CS) - #define PB44_GPIO_SW_RESET (PB44_GPIO_EXP_BASE + 6) - #define PB44_GPIO_SW_JUMP (PB44_GPIO_EXP_BASE + 8) - #define PB44_GPIO_LED_JUMP1 (PB44_GPIO_EXP_BASE + 9) -@@ -87,20 +112,59 @@ static struct gpio_keys_button pb44_gpio - } - }; - -+static void pb44_vsc7395_reset(void) -+{ -+ ath79_device_reset_set(AR71XX_RESET_GE1_PHY); -+ udelay(10); -+ ath79_device_reset_clear(AR71XX_RESET_GE1_PHY); -+ mdelay(50); -+} -+ -+static struct vsc7385_platform_data pb44_vsc7395_data = { -+ .reset = pb44_vsc7395_reset, -+ .ucode_name = "vsc7395_ucode_pb44.bin", -+ .mac_cfg = { -+ .tx_ipg = 6, -+ .bit2 = 1, -+ .clk_sel = 0, -+ }, -+}; -+ -+static const char *pb44_part_probes[] = { -+ "RedBoot", -+ NULL, -+}; -+ -+static struct flash_platform_data pb44_flash_data = { -+ .part_probes = pb44_part_probes, -+}; -+ - static struct spi_board_info pb44_spi_info[] = { - { - .bus_num = 0, - .chip_select = 0, - .max_speed_hz = 25000000, - .modalias = "m25p64", -+ .platform_data = &pb44_flash_data, - }, -+ { -+ .bus_num = 0, -+ .chip_select = 1, -+ .max_speed_hz = 25000000, -+ .modalias = "spi-vsc7385", -+ .platform_data = &pb44_vsc7395_data, -+ } - }; - - static struct ath79_spi_platform_data pb44_spi_data = { - .bus_num = 0, -- .num_chipselect = 1, -+ .num_chipselect = 2, - }; - -+#define PB44_WAN_PHYMASK BIT(0) -+#define PB44_LAN_PHYMASK 0 -+#define PB44_MDIO_PHYMASK (PB44_LAN_PHYMASK | PB44_WAN_PHYMASK) -+ - static void __init pb44_init(void) - { - i2c_register_board_info(0, pb44_i2c_board_info, -@@ -116,6 +180,22 @@ static void __init pb44_init(void) - ARRAY_SIZE(pb44_spi_info)); - ath79_register_usb(); - ath79_register_pci(); -+ -+ ath79_register_mdio(0, ~PB44_MDIO_PHYMASK); -+ -+ ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); -+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ath79_eth0_data.phy_mask = PB44_WAN_PHYMASK; -+ -+ ath79_register_eth(0); -+ -+ ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); -+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ath79_eth1_data.speed = SPEED_1000; -+ ath79_eth1_data.duplex = DUPLEX_FULL; -+ ath79_eth1_pll_data.pll_1000 = 0x110000; -+ -+ ath79_register_eth(1); - } - - MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board", ---- a/arch/mips/ath79/Kconfig -+++ b/arch/mips/ath79/Kconfig -@@ -57,6 +57,7 @@ config ATH79_MACH_DB120 - config ATH79_MACH_PB44 - bool "Atheros PB44 reference board" - select SOC_AR71XX -+ select ATH79_DEV_ETH - select ATH79_DEV_GPIO_BUTTONS - select ATH79_DEV_LEDS_GPIO - select ATH79_DEV_SPI diff --git a/target/linux/ar71xx/patches-4.9/607-MIPS-ath79-ubnt-xm-fixes.patch b/target/linux/ar71xx/patches-4.9/607-MIPS-ath79-ubnt-xm-fixes.patch deleted file mode 100644 index d667215a15..0000000000 --- a/target/linux/ar71xx/patches-4.9/607-MIPS-ath79-ubnt-xm-fixes.patch +++ /dev/null @@ -1,14 +0,0 @@ ---- a/arch/mips/ath79/Kconfig -+++ b/arch/mips/ath79/Kconfig -@@ -69,9 +69,10 @@ config ATH79_MACH_PB44 - config ATH79_MACH_UBNT_XM - bool "Ubiquiti Networks XM (rev 1.0) board" - select SOC_AR724X -+ select ATH79_DEV_AP9X_PCI if PCI - select ATH79_DEV_GPIO_BUTTONS - select ATH79_DEV_LEDS_GPIO -- select ATH79_DEV_SPI -+ select ATH79_DEV_M25P80 - help - Say 'Y' here if you want your kernel to support the - Ubiquiti Networks XM (rev 1.0) board. diff --git a/target/linux/ar71xx/patches-4.9/608-MIPS-ath79-ubnt-xm-add-more-boards.patch b/target/linux/ar71xx/patches-4.9/608-MIPS-ath79-ubnt-xm-add-more-boards.patch deleted file mode 100644 index 536c28d1ca..0000000000 --- a/target/linux/ar71xx/patches-4.9/608-MIPS-ath79-ubnt-xm-add-more-boards.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- a/arch/mips/ath79/Kconfig -+++ b/arch/mips/ath79/Kconfig -@@ -67,12 +67,16 @@ config ATH79_MACH_PB44 - Atheros PB44 reference board. - - config ATH79_MACH_UBNT_XM -- bool "Ubiquiti Networks XM (rev 1.0) board" -+ bool "Ubiquiti Networks XM/UniFi boards" - select SOC_AR724X -+ select SOC_AR934X - select ATH79_DEV_AP9X_PCI if PCI -+ select ATH79_DEV_ETH - select ATH79_DEV_GPIO_BUTTONS - select ATH79_DEV_LEDS_GPIO - select ATH79_DEV_M25P80 -+ select ATH79_DEV_USB -+ select ATH79_DEV_WMAC - help - Say 'Y' here if you want your kernel to support the - Ubiquiti Networks XM (rev 1.0) board. diff --git a/target/linux/ar71xx/patches-4.9/609-MIPS-ath79-ap136-fixes.patch b/target/linux/ar71xx/patches-4.9/609-MIPS-ath79-ap136-fixes.patch deleted file mode 100644 index 4d7902e166..0000000000 --- a/target/linux/ar71xx/patches-4.9/609-MIPS-ath79-ap136-fixes.patch +++ /dev/null @@ -1,300 +0,0 @@ ---- a/arch/mips/ath79/mach-ap136.c -+++ b/arch/mips/ath79/mach-ap136.c -@@ -18,23 +18,29 @@ - * - */ - --#include <linux/pci.h> --#include <linux/ath9k_platform.h> -+#include <linux/platform_device.h> -+#include <linux/ar8216_platform.h> - --#include "machtypes.h" -+#include <asm/mach-ath79/ar71xx_regs.h> -+ -+#include "common.h" -+#include "pci.h" -+#include "dev-ap9x-pci.h" - #include "dev-gpio-buttons.h" -+#include "dev-eth.h" - #include "dev-leds-gpio.h" --#include "dev-spi.h" -+#include "dev-m25p80.h" -+#include "dev-nfc.h" - #include "dev-usb.h" - #include "dev-wmac.h" --#include "pci.h" -+#include "machtypes.h" - --#define AP136_GPIO_LED_STATUS_RED 14 --#define AP136_GPIO_LED_STATUS_GREEN 19 - #define AP136_GPIO_LED_USB 4 --#define AP136_GPIO_LED_WLAN_2G 13 - #define AP136_GPIO_LED_WLAN_5G 12 -+#define AP136_GPIO_LED_WLAN_2G 13 -+#define AP136_GPIO_LED_STATUS_RED 14 - #define AP136_GPIO_LED_WPS_RED 15 -+#define AP136_GPIO_LED_STATUS_GREEN 19 - #define AP136_GPIO_LED_WPS_GREEN 20 - - #define AP136_GPIO_BTN_WPS 16 -@@ -43,37 +49,39 @@ - #define AP136_KEYS_POLL_INTERVAL 20 /* msecs */ - #define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL) - --#define AP136_WMAC_CALDATA_OFFSET 0x1000 --#define AP136_PCIE_CALDATA_OFFSET 0x5000 -+#define AP136_MAC0_OFFSET 0 -+#define AP136_MAC1_OFFSET 6 -+#define AP136_WMAC_CALDATA_OFFSET 0x1000 -+#define AP136_PCIE_CALDATA_OFFSET 0x5000 - - static struct gpio_led ap136_leds_gpio[] __initdata = { - { -- .name = "qca:green:status", -+ .name = "ap136:green:status", - .gpio = AP136_GPIO_LED_STATUS_GREEN, - .active_low = 1, - }, - { -- .name = "qca:red:status", -+ .name = "ap136:red:status", - .gpio = AP136_GPIO_LED_STATUS_RED, - .active_low = 1, - }, - { -- .name = "qca:green:wps", -+ .name = "ap136:green:wps", - .gpio = AP136_GPIO_LED_WPS_GREEN, - .active_low = 1, - }, - { -- .name = "qca:red:wps", -+ .name = "ap136:red:wps", - .gpio = AP136_GPIO_LED_WPS_RED, - .active_low = 1, - }, - { -- .name = "qca:red:wlan-2g", -+ .name = "ap136:red:wlan-2g", - .gpio = AP136_GPIO_LED_WLAN_2G, - .active_low = 1, - }, - { -- .name = "qca:red:usb", -+ .name = "ap136:red:usb", - .gpio = AP136_GPIO_LED_USB, - .active_low = 1, - } -@@ -98,59 +106,151 @@ static struct gpio_keys_button ap136_gpi - }, - }; - --static struct spi_board_info ap136_spi_info[] = { -- { -- .bus_num = 0, -- .chip_select = 0, -- .max_speed_hz = 25000000, -- .modalias = "mx25l6405d", -- } -+static struct ar8327_pad_cfg ap136_ar8327_pad0_cfg; -+static struct ar8327_pad_cfg ap136_ar8327_pad6_cfg; -+ -+static struct ar8327_platform_data ap136_ar8327_data = { -+ .pad0_cfg = &ap136_ar8327_pad0_cfg, -+ .pad6_cfg = &ap136_ar8327_pad6_cfg, -+ .port0_cfg = { -+ .force_link = 1, -+ .speed = AR8327_PORT_SPEED_1000, -+ .duplex = 1, -+ .txpause = 1, -+ .rxpause = 1, -+ }, -+ .port6_cfg = { -+ .force_link = 1, -+ .speed = AR8327_PORT_SPEED_1000, -+ .duplex = 1, -+ .txpause = 1, -+ .rxpause = 1, -+ }, - }; - --static struct ath79_spi_platform_data ap136_spi_data = { -- .bus_num = 0, -- .num_chipselect = 1, -+static struct mdio_board_info ap136_mdio0_info[] = { -+ { -+ .bus_id = "ag71xx-mdio.0", -+ .phy_addr = 0, -+ .platform_data = &ap136_ar8327_data, -+ }, - }; - --#ifdef CONFIG_PCI --static struct ath9k_platform_data ap136_ath9k_data; -+static void __init ap136_common_setup(void) -+{ -+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); -+ -+ ath79_register_m25p80(NULL); -+ -+ ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio), -+ ap136_leds_gpio); -+ ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(ap136_gpio_keys), -+ ap136_gpio_keys); -+ -+ ath79_register_usb(); -+ ath79_register_nfc(); -+ -+ ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL); -+ -+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); - --static int ap136_pci_plat_dev_init(struct pci_dev *dev) -+ ath79_register_mdio(0, 0x0); -+ ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0); -+ -+ mdiobus_register_board_info(ap136_mdio0_info, -+ ARRAY_SIZE(ap136_mdio0_info)); -+ -+ /* GMAC0 is connected to the RMGII interface */ -+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ath79_eth0_data.phy_mask = BIT(0); -+ ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; -+ -+ ath79_register_eth(0); -+ -+ /* GMAC1 is connected tot eh SGMII interface */ -+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; -+ ath79_eth1_data.speed = SPEED_1000; -+ ath79_eth1_data.duplex = DUPLEX_FULL; -+ -+ ath79_register_eth(1); -+} -+ -+static void __init ap136_010_setup(void) - { -- if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0) -- dev->dev.platform_data = &ap136_ath9k_data; -+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); - -- return 0; -+ /* GMAC0 of the AR8327 switch is connected to GMAC0 via RGMII */ -+ ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII; -+ ap136_ar8327_pad0_cfg.txclk_delay_en = true; -+ ap136_ar8327_pad0_cfg.rxclk_delay_en = true; -+ ap136_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1; -+ ap136_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2; -+ -+ /* GMAC6 of the AR8327 switch is connected to GMAC1 via SGMII */ -+ ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII; -+ ap136_ar8327_pad6_cfg.rxclk_delay_en = true; -+ ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0; -+ -+ ath79_eth0_pll_data.pll_1000 = 0xa6000000; -+ ath79_eth1_pll_data.pll_1000 = 0x03000101; -+ -+ ap136_common_setup(); -+ ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL); - } - --static void __init ap136_pci_init(u8 *eeprom) -+MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010", -+ "Atheros AP136-010 reference board", -+ ap136_010_setup); -+ -+static void __init ap136_020_common_setup(void) - { -- memcpy(ap136_ath9k_data.eeprom_data, eeprom, -- sizeof(ap136_ath9k_data.eeprom_data)); -+ /* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */ -+ ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII; -+ ap136_ar8327_pad0_cfg.sgmii_delay_en = true; -+ -+ /* GMAC6 of the AR8327 switch is connected to GMAC0 via RGMII */ -+ ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_RGMII; -+ ap136_ar8327_pad6_cfg.txclk_delay_en = true; -+ ap136_ar8327_pad6_cfg.rxclk_delay_en = true; -+ ap136_ar8327_pad6_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1; -+ ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2; - -- ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init); -- ath79_register_pci(); -+ ath79_eth0_pll_data.pll_1000 = 0x56000000; -+ ath79_eth1_pll_data.pll_1000 = 0x03000101; -+ -+ ap136_common_setup(); - } --#else --static inline void ap136_pci_init(u8 *eeprom) {} --#endif /* CONFIG_PCI */ - --static void __init ap136_setup(void) -+static void __init ap136_020_setup(void) - { - u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); - -- ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio), -- ap136_leds_gpio); -- ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL, -- ARRAY_SIZE(ap136_gpio_keys), -- ap136_gpio_keys); -- ath79_register_spi(&ap136_spi_data, ap136_spi_info, -- ARRAY_SIZE(ap136_spi_info)); -- ath79_register_usb(); -- ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET); -- ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET); -+ ap136_020_common_setup(); -+ ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL); - } - --MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010", -- "Atheros AP136-010 reference board", -- ap136_setup); -+MIPS_MACHINE(ATH79_MACH_AP136_020, "AP136-020", -+ "Atheros AP136-020 reference board", -+ ap136_020_setup); -+ -+/* -+ * AP135-020 is similar to AP136-020, any future AP135 specific init -+ * code can be added here. -+ */ -+static void __init ap135_020_setup(void) -+{ -+ ap136_leds_gpio[0].name = "ap135:green:status"; -+ ap136_leds_gpio[1].name = "ap135:red:status"; -+ ap136_leds_gpio[2].name = "ap135:green:wps"; -+ ap136_leds_gpio[3].name = "ap135:red:wps"; -+ ap136_leds_gpio[4].name = "ap135:red:wlan-2g"; -+ ap136_leds_gpio[5].name = "ap135:red:usb"; -+ -+ ap136_020_common_setup(); -+ ath79_register_pci(); -+} -+ -+MIPS_MACHINE(ATH79_MACH_AP135_020, "AP135-020", -+ "Atheros AP135-020 reference board", -+ ap135_020_setup); ---- a/arch/mips/ath79/Kconfig -+++ b/arch/mips/ath79/Kconfig -@@ -16,16 +16,17 @@ config ATH79_MACH_AP121 - Atheros AP121 reference board. - - config ATH79_MACH_AP136 -- bool "Atheros AP136 reference board" -+ bool "Atheros AP136/AP135 reference board" - select SOC_QCA955X - select ATH79_DEV_GPIO_BUTTONS - select ATH79_DEV_LEDS_GPIO -+ select ATH79_DEV_NFC - select ATH79_DEV_SPI - select ATH79_DEV_USB - select ATH79_DEV_WMAC - help - Say 'Y' here if you want your kernel to support the -- Atheros AP136 reference board. -+ Atheros AP136 or AP135 reference boards. - - config ATH79_MACH_AP81 - bool "Atheros AP81 reference board" diff --git a/target/linux/ar71xx/patches-4.9/611-MIPS-ath79-wdt-timeout.patch b/target/linux/ar71xx/patches-4.9/611-MIPS-ath79-wdt-timeout.patch deleted file mode 100644 index 0927d5a977..0000000000 --- a/target/linux/ar71xx/patches-4.9/611-MIPS-ath79-wdt-timeout.patch +++ /dev/null @@ -1,25 +0,0 @@ -MIPS: ath79: fix maximum timeout - -If the userland tries to set a timeout higher than the max_timeout, then we should fallback to max_timeout. - -Signed-off-by: John Crispin <blogic@openwrt.org> - ---- a/drivers/watchdog/ath79_wdt.c -+++ b/drivers/watchdog/ath79_wdt.c -@@ -115,10 +115,14 @@ static inline void ath79_wdt_disable(voi - - static int ath79_wdt_set_timeout(int val) - { -- if (val < 1 || val > max_timeout) -+ if (val < 1) - return -EINVAL; - -- timeout = val; -+ if (val > max_timeout) -+ timeout = max_timeout; -+ else -+ timeout = val; -+ - ath79_wdt_keepalive(); - - return 0; diff --git a/target/linux/ar71xx/patches-4.9/612-MIPS-ath79-set-buffalo-txgain.patch b/target/linux/ar71xx/patches-4.9/612-MIPS-ath79-set-buffalo-txgain.patch deleted file mode 100644 index 3d100e0549..0000000000 --- a/target/linux/ar71xx/patches-4.9/612-MIPS-ath79-set-buffalo-txgain.patch +++ /dev/null @@ -1,24 +0,0 @@ ---- a/arch/mips/ath79/dev-wmac.c -+++ b/arch/mips/ath79/dev-wmac.c -@@ -319,6 +319,11 @@ void __init ath79_wmac_disable_5ghz(void - ath79_wmac_data.disable_5ghz = true; - } - -+void __init ath79_wmac_set_tx_gain_buffalo(void) -+{ -+ ath79_wmac_data.tx_gain_buffalo = true; -+} -+ - void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr) - { - if (soc_is_ar913x()) ---- a/arch/mips/ath79/dev-wmac.h -+++ b/arch/mips/ath79/dev-wmac.h -@@ -16,6 +16,7 @@ void ath79_register_wmac(u8 *cal_data, u - void ath79_register_wmac_simple(void); - void ath79_wmac_disable_2ghz(void); - void ath79_wmac_disable_5ghz(void); -+void ath79_wmac_set_tx_gain_buffalo(void); - - bool ar93xx_wmac_read_mac_address(u8 *dest); - diff --git a/target/linux/ar71xx/patches-4.9/613-MIPS-ath79-add-ath79_wmac_setup_ext_lna_gpio-helper.patch b/target/linux/ar71xx/patches-4.9/613-MIPS-ath79-add-ath79_wmac_setup_ext_lna_gpio-helper.patch deleted file mode 100644 index 5c1205d59f..0000000000 --- a/target/linux/ar71xx/patches-4.9/613-MIPS-ath79-add-ath79_wmac_setup_ext_lna_gpio-helper.patch +++ /dev/null @@ -1,76 +0,0 @@ ---- a/arch/mips/ath79/dev-wmac.c -+++ b/arch/mips/ath79/dev-wmac.c -@@ -18,9 +18,11 @@ - #include <linux/etherdevice.h> - #include <linux/platform_device.h> - #include <linux/ath9k_platform.h> -+#include <linux/gpio.h> - - #include <asm/mach-ath79/ath79.h> - #include <asm/mach-ath79/ar71xx_regs.h> -+#include "common.h" - #include "dev-wmac.h" - - static u8 ath79_wmac_mac[ETH_ALEN]; -@@ -324,6 +326,51 @@ void __init ath79_wmac_set_tx_gain_buffa - ath79_wmac_data.tx_gain_buffalo = true; - } - -+static int ath79_request_ext_lna_gpio(unsigned chain, int gpio) -+{ -+ char *label; -+ int err; -+ -+ label = kasprintf(GFP_KERNEL, "external LNA%u", chain); -+ if (!label) -+ return -ENOMEM; -+ -+ err = gpio_request_one(gpio, GPIOF_DIR_OUT | GPIOF_INIT_LOW, label); -+ if (err) { -+ pr_err("unable to request GPIO%d for external LNA%u\n", -+ gpio, chain); -+ kfree(label); -+ } -+ -+ return err; -+} -+ -+static void ar934x_set_ext_lna_gpio(unsigned chain, int gpio) -+{ -+ unsigned int sel; -+ int err; -+ -+ if (WARN_ON(chain > 1)) -+ return; -+ -+ err = ath79_request_ext_lna_gpio(chain, gpio); -+ if (err) -+ return; -+ -+ if (chain == 0) -+ sel = AR934X_GPIO_OUT_EXT_LNA0; -+ else -+ sel = AR934X_GPIO_OUT_EXT_LNA1; -+ -+ ath79_gpio_output_select(gpio, sel); -+} -+ -+void __init ath79_wmac_set_ext_lna_gpio(unsigned chain, int gpio) -+{ -+ if (soc_is_ar934x()) -+ ar934x_set_ext_lna_gpio(chain, gpio); -+} -+ - void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr) - { - if (soc_is_ar913x()) ---- a/arch/mips/ath79/dev-wmac.h -+++ b/arch/mips/ath79/dev-wmac.h -@@ -17,6 +17,7 @@ void ath79_register_wmac_simple(void); - void ath79_wmac_disable_2ghz(void); - void ath79_wmac_disable_5ghz(void); - void ath79_wmac_set_tx_gain_buffalo(void); -+void ath79_wmac_set_ext_lna_gpio(unsigned chain, int gpio); - - bool ar93xx_wmac_read_mac_address(u8 *dest); - diff --git a/target/linux/ar71xx/patches-4.9/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-4.9/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch deleted file mode 100644 index ed887cc500..0000000000 --- a/target/linux/ar71xx/patches-4.9/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch +++ /dev/null @@ -1,696 +0,0 @@ -From 5300a7cd7ed2f88488ddba62947b9c6bb9663777 Mon Sep 17 00:00:00 2001 -Message-Id: <5300a7cd7ed2f88488ddba62947b9c6bb9663777.1396122227.git.mschiffer@universe-factory.net> -From: Matthias Schiffer <mschiffer@universe-factory.net> -Date: Sat, 29 Mar 2014 20:26:08 +0100 -Subject: [PATCH 1/2] MIPS: ath79: add support for QCA953x SoC - -Note that the clock calculation looks very similar to the QCA955x, but the -meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. ---- - arch/mips/ath79/Kconfig | 6 +- - arch/mips/ath79/clock.c | 78 ++++++++++++++++++++++++++ - arch/mips/ath79/common.c | 4 ++ - arch/mips/ath79/dev-common.c | 1 + - arch/mips/ath79/dev-wmac.c | 20 +++++++ - arch/mips/ath79/early_printk.c | 1 + - arch/mips/ath79/gpio.c | 4 +- - arch/mips/ath79/irq.c | 4 ++ - arch/mips/ath79/setup.c | 8 ++- - arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 48 ++++++++++++++++ - arch/mips/include/asm/mach-ath79/ath79.h | 11 ++++ - 11 files changed, 182 insertions(+), 3 deletions(-) - ---- a/arch/mips/ath79/Kconfig -+++ b/arch/mips/ath79/Kconfig -@@ -104,6 +104,10 @@ config SOC_AR934X - select PCI_AR724X if PCI - def_bool n - -+config SOC_QCA953X -+ select USB_ARCH_HAS_EHCI -+ def_bool n -+ - config SOC_QCA955X - select HW_HAS_PCI - select PCI_AR724X if PCI -@@ -143,7 +147,7 @@ config ATH79_DEV_USB - def_bool n - - config ATH79_DEV_WMAC -- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X) -+ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X) - def_bool n - - config ATH79_NVRAM ---- a/arch/mips/ath79/clock.c -+++ b/arch/mips/ath79/clock.c -@@ -358,6 +358,87 @@ static void __init ar934x_clocks_init(vo - iounmap(dpll_base); - } - -+static void __init qca953x_clocks_init(void) -+{ -+ unsigned long ref_rate; -+ unsigned long cpu_rate; -+ unsigned long ddr_rate; -+ unsigned long ahb_rate; -+ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; -+ u32 cpu_pll, ddr_pll; -+ -+ /* QCA953X only supports 25MHz ref_clk */ -+ ref_rate = 25 * 1000 * 1000; -+ -+ pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG); -+ out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & -+ QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK; -+ ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) & -+ QCA953X_PLL_CPU_CONFIG_REFDIV_MASK; -+ nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) & -+ QCA953X_PLL_CPU_CONFIG_NINT_MASK; -+ frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) & -+ QCA953X_PLL_CPU_CONFIG_NFRAC_MASK; -+ -+ cpu_pll = nint * ref_rate / ref_div; -+ cpu_pll += frac * (ref_rate >> 6) / ref_div; -+ cpu_pll /= (1 << out_div); -+ -+ pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG); -+ out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & -+ QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK; -+ ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) & -+ QCA953X_PLL_DDR_CONFIG_REFDIV_MASK; -+ nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) & -+ QCA953X_PLL_DDR_CONFIG_NINT_MASK; -+ frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) & -+ QCA953X_PLL_DDR_CONFIG_NFRAC_MASK; -+ -+ ddr_pll = nint * ref_rate / ref_div; -+ ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4); -+ ddr_pll /= (1 << out_div); -+ -+ clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG); -+ -+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & -+ QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; -+ -+ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS) -+ cpu_rate = ref_rate; -+ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL) -+ cpu_rate = cpu_pll / (postdiv + 1); -+ else -+ cpu_rate = ddr_pll / (postdiv + 1); -+ -+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & -+ QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; -+ -+ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS) -+ ddr_rate = ref_rate; -+ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL) -+ ddr_rate = ddr_pll / (postdiv + 1); -+ else -+ ddr_rate = cpu_pll / (postdiv + 1); -+ -+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & -+ QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK; -+ -+ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS) -+ ahb_rate = ref_rate; -+ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) -+ ahb_rate = ddr_pll / (postdiv + 1); -+ else -+ ahb_rate = cpu_pll / (postdiv + 1); -+ -+ ath79_add_sys_clkdev("ref", ref_rate); -+ ath79_add_sys_clkdev("cpu", cpu_rate); -+ ath79_add_sys_clkdev("ddr", ddr_rate); -+ ath79_add_sys_clkdev("ahb", ahb_rate); -+ -+ clk_add_alias("wdt", NULL, "ref", NULL); -+ clk_add_alias("uart", NULL, "ref", NULL); -+} -+ - static void __init qca955x_clocks_init(void) - { - unsigned long ref_rate; -@@ -453,6 +534,8 @@ void __init ath79_clocks_init(void) - ar933x_clocks_init(); - else if (soc_is_ar934x()) - ar934x_clocks_init(); -+ else if (soc_is_qca953x()) -+ qca953x_clocks_init(); - else if (soc_is_qca955x()) - qca955x_clocks_init(); - else ---- a/arch/mips/ath79/common.c -+++ b/arch/mips/ath79/common.c -@@ -103,6 +103,8 @@ void ath79_device_reset_set(u32 mask) - reg = AR933X_RESET_REG_RESET_MODULE; - else if (soc_is_ar934x()) - reg = AR934X_RESET_REG_RESET_MODULE; -+ else if (soc_is_qca953x()) -+ reg = QCA953X_RESET_REG_RESET_MODULE; - else if (soc_is_qca955x()) - reg = QCA955X_RESET_REG_RESET_MODULE; - else -@@ -131,6 +133,8 @@ void ath79_device_reset_clear(u32 mask) - reg = AR933X_RESET_REG_RESET_MODULE; - else if (soc_is_ar934x()) - reg = AR934X_RESET_REG_RESET_MODULE; -+ else if (soc_is_qca953x()) -+ reg = QCA953X_RESET_REG_RESET_MODULE; - else if (soc_is_qca955x()) - reg = QCA955X_RESET_REG_RESET_MODULE; - else ---- a/arch/mips/ath79/dev-common.c -+++ b/arch/mips/ath79/dev-common.c -@@ -94,6 +94,7 @@ void __init ath79_register_uart(void) - soc_is_ar724x() || - soc_is_ar913x() || - soc_is_ar934x() || -+ soc_is_qca953x() || - soc_is_qca955x()) { - ath79_uart_data[0].uartclk = uart_clk_rate; - platform_device_register(&ath79_uart_device); -@@ -157,6 +158,9 @@ void __init ath79_gpio_init(void) - } else if (soc_is_ar934x()) { - ath79_gpio_pdata.ngpios = AR934X_GPIO_COUNT; - ath79_gpio_pdata.oe_inverted = 1; -+ } else if (soc_is_qca953x()) { -+ ath79_gpio_pdata.ngpios = QCA953X_GPIO_COUNT; -+ ath79_gpio_pdata.oe_inverted = 1; - } else if (soc_is_qca955x()) { - ath79_gpio_pdata.ngpios = QCA955X_GPIO_COUNT; - ath79_gpio_pdata.oe_inverted = 1; ---- a/arch/mips/ath79/dev-usb.c -+++ b/arch/mips/ath79/dev-usb.c -@@ -236,6 +236,30 @@ static void __init ar934x_usb_setup(void - &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); - } - -+static void __init qca953x_usb_setup(void) -+{ -+ u32 bootstrap; -+ -+ bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP); -+ -+ ath79_device_reset_set(QCA953X_RESET_USBSUS_OVERRIDE); -+ udelay(1000); -+ -+ ath79_device_reset_clear(QCA953X_RESET_USB_PHY); -+ udelay(1000); -+ -+ ath79_device_reset_clear(QCA953X_RESET_USB_PHY_ANALOG); -+ udelay(1000); -+ -+ ath79_device_reset_clear(QCA953X_RESET_USB_HOST); -+ udelay(1000); -+ -+ ath79_usb_register("ehci-platform", -1, -+ QCA953X_EHCI_BASE, QCA953X_EHCI_SIZE, -+ ATH79_CPU_IRQ(3), -+ &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); -+} -+ - static void qca955x_usb_reset_notifier(struct platform_device *pdev) - { - u32 base; -@@ -286,6 +310,8 @@ void __init ath79_register_usb(void) - ar933x_usb_setup(); - else if (soc_is_ar934x()) - ar934x_usb_setup(); -+ else if (soc_is_qca953x()) -+ qca953x_usb_setup(); - else if (soc_is_qca955x()) - qca955x_usb_setup(); - else ---- a/arch/mips/ath79/dev-wmac.c -+++ b/arch/mips/ath79/dev-wmac.c -@@ -100,7 +100,7 @@ static int ar933x_wmac_reset(void) - return -ETIMEDOUT; - } - --static int ar933x_r1_get_wmac_revision(void) -+static int ar93xx_get_soc_revision(void) - { - return ath79_soc_rev; - } -@@ -125,7 +125,7 @@ static void __init ar933x_wmac_setup(voi - ath79_wmac_data.is_clk_25mhz = true; - - if (ath79_soc_rev == 1) -- ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision; -+ ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision; - - ath79_wmac_data.external_reset = ar933x_wmac_reset; - } -@@ -150,6 +150,21 @@ static void ar934x_wmac_setup(void) - ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision; - } - -+static void qca953x_wmac_setup(void) -+{ -+ ath79_wmac_device.name = "qca953x_wmac"; -+ -+ ath79_wmac_resources[0].start = QCA953X_WMAC_BASE; -+ ath79_wmac_resources[0].end = QCA953X_WMAC_BASE + QCA953X_WMAC_SIZE - 1; -+ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); -+ ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1); -+ -+ /* QCA953X only supports 25MHz ref_clk */ -+ ath79_wmac_data.is_clk_25mhz = true; -+ -+ ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision; -+} -+ - static void qca955x_wmac_setup(void) - { - u32 t; -@@ -379,6 +394,8 @@ void __init ath79_register_wmac(u8 *cal_ - ar933x_wmac_setup(); - else if (soc_is_ar934x()) - ar934x_wmac_setup(); -+ else if (soc_is_qca953x()) -+ qca953x_wmac_setup(); - else if (soc_is_qca955x()) - qca955x_wmac_setup(); - else ---- a/arch/mips/ath79/early_printk.c -+++ b/arch/mips/ath79/early_printk.c -@@ -116,6 +116,8 @@ static void prom_putchar_init(void) - case REV_ID_MAJOR_AR9341: - case REV_ID_MAJOR_AR9342: - case REV_ID_MAJOR_AR9344: -+ case REV_ID_MAJOR_QCA9533: -+ case REV_ID_MAJOR_QCA9533_V2: - case REV_ID_MAJOR_QCA9556: - case REV_ID_MAJOR_QCA9558: - _prom_putchar = prom_putchar_ar71xx; ---- a/arch/mips/ath79/gpio.c -+++ b/arch/mips/ath79/gpio.c -@@ -31,7 +31,7 @@ static void __iomem *ath79_gpio_get_func - soc_is_ar913x() || - soc_is_ar933x()) - reg = AR71XX_GPIO_REG_FUNC; -- else if (soc_is_ar934x()) -+ else if (soc_is_ar934x() || soc_is_qca953x()) - reg = AR934X_GPIO_REG_FUNC; - else - BUG(); -@@ -64,7 +64,7 @@ void __init ath79_gpio_output_select(uns - unsigned int reg; - u32 t, s; - -- BUG_ON(!soc_is_ar934x()); -+ BUG_ON(!soc_is_ar934x() && !soc_is_qca953x()); - - if (gpio >= AR934X_GPIO_COUNT) - return; ---- a/arch/mips/ath79/irq.c -+++ b/arch/mips/ath79/irq.c -@@ -56,6 +56,34 @@ static void ar934x_ip2_irq_init(void) - irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch); - } - -+static void qca953x_ip2_irq_dispatch(struct irq_desc *desc) -+{ -+ u32 status; -+ -+ status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS); -+ -+ if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) { -+ ath79_ddr_wb_flush(3); -+ generic_handle_irq(ATH79_IP2_IRQ(0)); -+ } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) { -+ ath79_ddr_wb_flush(4); -+ generic_handle_irq(ATH79_IP2_IRQ(1)); -+ } else { -+ spurious_interrupt(); -+ } -+} -+ -+static void qca953x_irq_init(void) -+{ -+ int i; -+ -+ for (i = ATH79_IP2_IRQ_BASE; -+ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) -+ irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq); -+ -+ irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch); -+} -+ - static void qca955x_ip2_irq_dispatch(struct irq_desc *desc) - { - u32 status; -@@ -143,7 +171,7 @@ void __init arch_init_irq(void) - soc_is_ar913x() || soc_is_ar933x()) { - irq_wb_chan2 = 3; - irq_wb_chan3 = 2; -- } else if (soc_is_ar934x()) { -+ } else if (soc_is_ar934x() || soc_is_qca953x()) { - irq_wb_chan3 = 2; - } - -@@ -154,6 +182,7 @@ void __init arch_init_irq(void) - else if (soc_is_ar724x() || - soc_is_ar933x() || - soc_is_ar934x() || -+ soc_is_qca953x() || - soc_is_qca955x()) - misc_is_ar71xx = false; - else -@@ -164,6 +193,8 @@ void __init arch_init_irq(void) - - if (soc_is_ar934x()) - ar934x_ip2_irq_init(); -+ else if (soc_is_qca953x()) -+ qca953x_irq_init(); - else if (soc_is_qca955x()) - qca955x_irq_init(); - } ---- a/arch/mips/ath79/setup.c -+++ b/arch/mips/ath79/setup.c -@@ -60,6 +60,7 @@ static void __init ath79_detect_sys_type - u32 major; - u32 minor; - u32 rev = 0; -+ u32 ver = 1; - - id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID); - major = id & REV_ID_MAJOR_MASK; -@@ -152,6 +153,17 @@ static void __init ath79_detect_sys_type - rev = id & AR934X_REV_ID_REVISION_MASK; - break; - -+ case REV_ID_MAJOR_QCA9533_V2: -+ ver = 2; -+ ath79_soc_rev = 2; -+ /* drop through */ -+ -+ case REV_ID_MAJOR_QCA9533: -+ ath79_soc = ATH79_SOC_QCA9533; -+ chip = "9533"; -+ rev = id & QCA953X_REV_ID_REVISION_MASK; -+ break; -+ - case REV_ID_MAJOR_QCA9556: - ath79_soc = ATH79_SOC_QCA9556; - chip = "9556"; -@@ -168,11 +180,12 @@ static void __init ath79_detect_sys_type - panic("ath79: unknown SoC, id:0x%08x", id); - } - -- ath79_soc_rev = rev; -+ if (ver == 1) -+ ath79_soc_rev = rev; - -- if (soc_is_qca955x()) -- sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u", -- chip, rev); -+ if (soc_is_qca953x() || soc_is_qca955x()) -+ sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u", -+ chip, ver, rev); - else - sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); - pr_info("SoC: %s\n", ath79_sys_type); ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -105,6 +105,21 @@ - #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) - #define AR934X_SRIF_SIZE 0x1000 - -+#define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) -+#define QCA953X_GMAC_SIZE 0x14 -+#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) -+#define QCA953X_WMAC_SIZE 0x20000 -+#define QCA953X_EHCI_BASE 0x1b000000 -+#define QCA953X_EHCI_SIZE 0x200 -+#define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) -+#define QCA953X_SRIF_SIZE 0x1000 -+ -+#define QCA953X_PCI_CFG_BASE0 0x14000000 -+#define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) -+#define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) -+#define QCA953X_PCI_MEM_BASE0 0x10000000 -+#define QCA953X_PCI_MEM_SIZE 0x02000000 -+ - #define QCA955X_PCI_MEM_BASE0 0x10000000 - #define QCA955X_PCI_MEM_BASE1 0x12000000 - #define QCA955X_PCI_MEM_SIZE 0x02000000 -@@ -180,6 +195,12 @@ - #define AR934X_OTP_INTF3_ADDRESS 0x3100c - #define AR934X_OTP_PGENB_SETUP_HOLD_TIME_ADDRESS 0x31034 - -+#define QCA953X_DDR_REG_FLUSH_GE0 0x9c -+#define QCA953X_DDR_REG_FLUSH_GE1 0xa0 -+#define QCA953X_DDR_REG_FLUSH_USB 0xa4 -+#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8 -+#define QCA953X_DDR_REG_FLUSH_WMAC 0xac -+ - /* - * PLL block - */ -@@ -289,6 +310,44 @@ - - #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6) - -+#define QCA953X_PLL_CPU_CONFIG_REG 0x00 -+#define QCA953X_PLL_DDR_CONFIG_REG 0x04 -+#define QCA953X_PLL_CLK_CTRL_REG 0x08 -+#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 -+#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c -+#define QCA953X_PLL_ETH_SGMII_CONTROL_REG 0x48 -+ -+#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 -+#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f -+#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6 -+#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f -+#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 -+#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f -+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 -+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 -+ -+#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 -+#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff -+#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10 -+#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f -+#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 -+#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f -+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 -+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 -+ -+#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) -+#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) -+#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) -+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 -+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f -+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 -+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f -+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 -+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f -+#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) -+#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) -+#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) -+ - #define QCA955X_PLL_CPU_CONFIG_REG 0x00 - #define QCA955X_PLL_DDR_CONFIG_REG 0x04 - #define QCA955X_PLL_CLK_CTRL_REG 0x08 -@@ -365,6 +424,10 @@ - #define AR934X_RESET_REG_BOOTSTRAP 0xb0 - #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac - -+#define QCA953X_RESET_REG_RESET_MODULE 0x1c -+#define QCA953X_RESET_REG_BOOTSTRAP 0xb0 -+#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac -+ - #define QCA955X_RESET_REG_RESET_MODULE 0x1c - #define QCA955X_RESET_REG_BOOTSTRAP 0xb0 - #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac -@@ -460,6 +523,27 @@ - #define AR934X_RESET_MBOX BIT(1) - #define AR934X_RESET_I2S BIT(0) - -+#define QCA953X_RESET_USB_EXT_PWR BIT(29) -+#define QCA953X_RESET_EXTERNAL BIT(28) -+#define QCA953X_RESET_RTC BIT(27) -+#define QCA953X_RESET_FULL_CHIP BIT(24) -+#define QCA953X_RESET_GE1_MDIO BIT(23) -+#define QCA953X_RESET_GE0_MDIO BIT(22) -+#define QCA953X_RESET_CPU_NMI BIT(21) -+#define QCA953X_RESET_CPU_COLD BIT(20) -+#define QCA953X_RESET_DDR BIT(16) -+#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) -+#define QCA953X_RESET_GE1_MAC BIT(13) -+#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12) -+#define QCA953X_RESET_USB_PHY_ANALOG BIT(11) -+#define QCA953X_RESET_GE0_MAC BIT(9) -+#define QCA953X_RESET_ETH_SWITCH BIT(8) -+#define QCA953X_RESET_PCIE_PHY BIT(7) -+#define QCA953X_RESET_PCIE BIT(6) -+#define QCA953X_RESET_USB_HOST BIT(5) -+#define QCA953X_RESET_USB_PHY BIT(4) -+#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3) -+ - #define QCA955X_RESET_HOST BIT(31) - #define QCA955X_RESET_SLIC BIT(30) - #define QCA955X_RESET_HDMA BIT(29) -@@ -513,6 +597,13 @@ - #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) - #define AR934X_BOOTSTRAP_DDR1 BIT(0) - -+#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12) -+#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11) -+#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5) -+#define QCA953X_BOOTSTRAP_REF_CLK BIT(4) -+#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1) -+#define QCA953X_BOOTSTRAP_DDR1 BIT(0) -+ - #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) - - #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) -@@ -533,6 +624,24 @@ - AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ - AR934X_PCIE_WMAC_INT_PCIE_RC3) - -+#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0) -+#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1) -+#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) -+#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) -+#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4) -+#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) -+#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) -+#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) -+#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) -+#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \ -+ (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \ -+ QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP) -+ -+#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \ -+ (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \ -+ QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \ -+ QCA953X_PCIE_WMAC_INT_PCIE_RC3) -+ - #define QCA955X_EXT_INT_WMAC_MISC BIT(0) - #define QCA955X_EXT_INT_WMAC_TX BIT(1) - #define QCA955X_EXT_INT_WMAC_RXLP BIT(2) -@@ -575,6 +684,8 @@ - #define REV_ID_MAJOR_AR9341 0x0120 - #define REV_ID_MAJOR_AR9342 0x1120 - #define REV_ID_MAJOR_AR9344 0x2120 -+#define REV_ID_MAJOR_QCA9533 0x0140 -+#define REV_ID_MAJOR_QCA9533_V2 0x0160 - #define REV_ID_MAJOR_QCA9556 0x0130 - #define REV_ID_MAJOR_QCA9558 0x1130 - -@@ -597,6 +708,8 @@ - - #define AR934X_REV_ID_REVISION_MASK 0xf - -+#define QCA953X_REV_ID_REVISION_MASK 0xf -+ - #define QCA955X_REV_ID_REVISION_MASK 0xf - - /* -@@ -644,6 +757,25 @@ - #define AR934X_GPIO_REG_OUT_FUNC5 0x40 - #define AR934X_GPIO_REG_FUNC 0x6c - -+#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c -+#define QCA953X_GPIO_REG_OUT_FUNC1 0x30 -+#define QCA953X_GPIO_REG_OUT_FUNC2 0x34 -+#define QCA953X_GPIO_REG_OUT_FUNC3 0x38 -+#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c -+#define QCA953X_GPIO_REG_IN_ENABLE0 0x44 -+#define QCA953X_GPIO_REG_FUNC 0x6c -+ -+#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10 -+#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11 -+#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9 -+#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8 -+#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12 -+#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41 -+#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42 -+#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43 -+#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44 -+#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45 -+ - #define QCA955X_GPIO_REG_OUT_FUNC0 0x2c - #define QCA955X_GPIO_REG_OUT_FUNC1 0x30 - #define QCA955X_GPIO_REG_OUT_FUNC2 0x34 -@@ -658,6 +790,7 @@ - #define AR913X_GPIO_COUNT 22 - #define AR933X_GPIO_COUNT 30 - #define AR934X_GPIO_COUNT 23 -+#define QCA953X_GPIO_COUNT 18 - #define QCA955X_GPIO_COUNT 24 - - /* -@@ -681,6 +814,24 @@ - #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 - #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 - -+#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0 -+#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4 -+#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8 -+ -+#define QCA953X_SRIF_DDR_DPLL1_REG 0x240 -+#define QCA953X_SRIF_DDR_DPLL2_REG 0x244 -+#define QCA953X_SRIF_DDR_DPLL3_REG 0x248 -+ -+#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27 -+#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f -+#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18 -+#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff -+#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff -+ -+#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30) -+#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13 -+#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7 -+ - #define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) - #define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) - #define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) -@@ -887,6 +1038,16 @@ - #define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16 - - /* -+ * QCA953X GMAC Interface -+ */ -+#define QCA953X_GMAC_REG_ETH_CFG 0x00 -+ -+#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6) -+#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7) -+#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9) -+#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) -+ -+/* - * QCA955X GMAC Interface - */ - ---- a/arch/mips/include/asm/mach-ath79/ath79.h -+++ b/arch/mips/include/asm/mach-ath79/ath79.h -@@ -32,6 +32,7 @@ enum ath79_soc_type { - ATH79_SOC_AR9341, - ATH79_SOC_AR9342, - ATH79_SOC_AR9344, -+ ATH79_SOC_QCA9533, - ATH79_SOC_QCA9556, - ATH79_SOC_QCA9558, - }; -@@ -100,6 +101,16 @@ static inline int soc_is_ar934x(void) - return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344(); - } - -+static inline int soc_is_qca9533(void) -+{ -+ return ath79_soc == ATH79_SOC_QCA9533; -+} -+ -+static inline int soc_is_qca953x(void) -+{ -+ return soc_is_qca9533(); -+} -+ - static inline int soc_is_qca9556(void) - { - return ath79_soc == ATH79_SOC_QCA9556; diff --git a/target/linux/ar71xx/patches-4.9/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-4.9/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch deleted file mode 100644 index 03bb9c31f6..0000000000 --- a/target/linux/ar71xx/patches-4.9/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch +++ /dev/null @@ -1,717 +0,0 @@ ---- a/arch/mips/ath79/Kconfig -+++ b/arch/mips/ath79/Kconfig -@@ -113,6 +113,12 @@ config SOC_QCA955X - select PCI_AR724X if PCI - def_bool n - -+config SOC_QCA956X -+ select USB_ARCH_HAS_EHCI -+ select HW_HAS_PCI -+ select PCI_AR724X if PCI -+ def_bool n -+ - config ATH79_DEV_M25P80 - select ATH79_DEV_SPI - def_bool n -@@ -147,7 +153,7 @@ config ATH79_DEV_USB - def_bool n - - config ATH79_DEV_WMAC -- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X) -+ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X || SOC_QCA956X) - def_bool n - - config ATH79_NVRAM ---- a/arch/mips/ath79/clock.c -+++ b/arch/mips/ath79/clock.c -@@ -524,6 +524,100 @@ static void __init qca955x_clocks_init(v - clk_add_alias("uart", NULL, "ref", NULL); - } - -+static void __init qca956x_clocks_init(void) -+{ -+ unsigned long ref_rate; -+ unsigned long cpu_rate; -+ unsigned long ddr_rate; -+ unsigned long ahb_rate; -+ u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv; -+ u32 cpu_pll, ddr_pll; -+ u32 bootstrap; -+ -+ bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP); -+ if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40) -+ ref_rate = 40 * 1000 * 1000; -+ else -+ ref_rate = 25 * 1000 * 1000; -+ -+ pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG); -+ out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & -+ QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK; -+ ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) & -+ QCA956X_PLL_CPU_CONFIG_REFDIV_MASK; -+ -+ pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG); -+ nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) & -+ QCA956X_PLL_CPU_CONFIG1_NINT_MASK; -+ hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) & -+ QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK; -+ lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) & -+ QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK; -+ -+ cpu_pll = nint * ref_rate / ref_div; -+ cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13); -+ cpu_pll += (hfrac >> 13) * ref_rate / ref_div; -+ cpu_pll /= (1 << out_div); -+ -+ pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG); -+ out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & -+ QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK; -+ ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) & -+ QCA956X_PLL_DDR_CONFIG_REFDIV_MASK; -+ pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG); -+ nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) & -+ QCA956X_PLL_DDR_CONFIG1_NINT_MASK; -+ hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) & -+ QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK; -+ lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) & -+ QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK; -+ -+ ddr_pll = nint * ref_rate / ref_div; -+ ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13); -+ ddr_pll += (hfrac >> 13) * ref_rate / ref_div; -+ ddr_pll /= (1 << out_div); -+ -+ clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG); -+ -+ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & -+ QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; -+ -+ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS) -+ cpu_rate = ref_rate; -+ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL) -+ cpu_rate = ddr_pll / (postdiv + 1); -+ else -+ cpu_rate = cpu_pll / (postdiv + 1); -+ -+ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & -+ QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; -+ -+ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS) -+ ddr_rate = ref_rate; -+ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL) -+ ddr_rate = cpu_pll / (postdiv + 1); -+ else -+ ddr_rate = ddr_pll / (postdiv + 1); -+ -+ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & -+ QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK; -+ -+ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS) -+ ahb_rate = ref_rate; -+ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) -+ ahb_rate = ddr_pll / (postdiv + 1); -+ else -+ ahb_rate = cpu_pll / (postdiv + 1); -+ -+ ath79_add_sys_clkdev("ref", ref_rate); -+ ath79_add_sys_clkdev("cpu", cpu_rate); -+ ath79_add_sys_clkdev("ddr", ddr_rate); -+ ath79_add_sys_clkdev("ahb", ahb_rate); -+ -+ clk_add_alias("wdt", NULL, "ref", NULL); -+ clk_add_alias("uart", NULL, "ref", NULL); -+} -+ - void __init ath79_clocks_init(void) - { - if (soc_is_ar71xx()) -@@ -538,6 +632,8 @@ void __init ath79_clocks_init(void) - qca953x_clocks_init(); - else if (soc_is_qca955x()) - qca955x_clocks_init(); -+ else if (soc_is_qca956x() || soc_is_tp9343()) -+ qca956x_clocks_init(); - else - BUG(); - } ---- a/arch/mips/ath79/common.c -+++ b/arch/mips/ath79/common.c -@@ -107,6 +107,8 @@ void ath79_device_reset_set(u32 mask) - reg = QCA953X_RESET_REG_RESET_MODULE; - else if (soc_is_qca955x()) - reg = QCA955X_RESET_REG_RESET_MODULE; -+ else if (soc_is_qca956x() || soc_is_tp9343()) -+ reg = QCA956X_RESET_REG_RESET_MODULE; - else - panic("Reset register not defined for this SOC"); - -@@ -137,6 +139,8 @@ void ath79_device_reset_clear(u32 mask) - reg = QCA953X_RESET_REG_RESET_MODULE; - else if (soc_is_qca955x()) - reg = QCA955X_RESET_REG_RESET_MODULE; -+ else if (soc_is_qca956x() || soc_is_tp9343()) -+ reg = QCA956X_RESET_REG_RESET_MODULE; - else - panic("Reset register not defined for this SOC"); - -@@ -163,6 +167,8 @@ u32 ath79_device_reset_get(u32 mask) - reg = AR933X_RESET_REG_RESET_MODULE; - else if (soc_is_ar934x()) - reg = AR934X_RESET_REG_RESET_MODULE; -+ else if (soc_is_qca956x() || soc_is_tp9343()) -+ reg = QCA956X_RESET_REG_RESET_MODULE; - else - BUG(); - ---- a/arch/mips/ath79/dev-common.c -+++ b/arch/mips/ath79/dev-common.c -@@ -95,7 +95,9 @@ void __init ath79_register_uart(void) - soc_is_ar913x() || - soc_is_ar934x() || - soc_is_qca953x() || -- soc_is_qca955x()) { -+ soc_is_qca955x() || -+ soc_is_qca956x() || -+ soc_is_tp9343()) { - ath79_uart_data[0].uartclk = uart_clk_rate; - platform_device_register(&ath79_uart_device); - } else if (soc_is_ar933x()) { -@@ -164,6 +166,9 @@ void __init ath79_gpio_init(void) - } else if (soc_is_qca955x()) { - ath79_gpio_pdata.ngpios = QCA955X_GPIO_COUNT; - ath79_gpio_pdata.oe_inverted = 1; -+ } else if (soc_is_qca956x() || soc_is_tp9343()) { -+ ath79_gpio_pdata.ngpios = QCA956X_GPIO_COUNT; -+ ath79_gpio_pdata.oe_inverted = 1; - } else { - BUG(); - } ---- a/arch/mips/ath79/dev-usb.c -+++ b/arch/mips/ath79/dev-usb.c -@@ -296,6 +296,19 @@ static void __init qca955x_usb_setup(voi - &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); - } - -+static void __init qca956x_usb_setup(void) -+{ -+ ath79_usb_register("ehci-platform", 0, -+ QCA956X_EHCI0_BASE, QCA956X_EHCI_SIZE, -+ ATH79_IP3_IRQ(0), -+ &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); -+ -+ ath79_usb_register("ehci-platform", 1, -+ QCA956X_EHCI1_BASE, QCA956X_EHCI_SIZE, -+ ATH79_IP3_IRQ(1), -+ &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); -+} -+ - void __init ath79_register_usb(void) - { - if (soc_is_ar71xx()) -@@ -314,6 +327,8 @@ void __init ath79_register_usb(void) - qca953x_usb_setup(); - else if (soc_is_qca955x()) - qca955x_usb_setup(); -+ else if (soc_is_qca956x()) -+ qca956x_usb_setup(); - else - BUG(); - } ---- a/arch/mips/ath79/dev-wmac.c -+++ b/arch/mips/ath79/dev-wmac.c -@@ -195,6 +195,26 @@ static void qca955x_wmac_setup(void) - #define AR93XX_OTP_READ_DATA \ - (soc_is_ar934x() ? AR934X_OTP_READ_DATA : AR9300_OTP_READ_DATA) - -+static void qca956x_wmac_setup(void) -+{ -+ u32 t; -+ -+ ath79_wmac_device.name = "qca956x_wmac"; -+ -+ ath79_wmac_resources[0].start = QCA956X_WMAC_BASE; -+ ath79_wmac_resources[0].end = QCA956X_WMAC_BASE + QCA956X_WMAC_SIZE - 1; -+ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); -+ ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1); -+ -+ t = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP); -+ if (t & QCA956X_BOOTSTRAP_REF_CLK_40) -+ ath79_wmac_data.is_clk_25mhz = false; -+ else -+ ath79_wmac_data.is_clk_25mhz = true; -+ -+ ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision; -+} -+ - static bool __init - ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data) - { -@@ -398,6 +418,8 @@ void __init ath79_register_wmac(u8 *cal_ - qca953x_wmac_setup(); - else if (soc_is_qca955x()) - qca955x_wmac_setup(); -+ else if (soc_is_qca956x() || soc_is_tp9343()) -+ qca956x_wmac_setup(); - else - BUG(); - ---- a/arch/mips/ath79/early_printk.c -+++ b/arch/mips/ath79/early_printk.c -@@ -120,6 +120,8 @@ static void prom_putchar_init(void) - case REV_ID_MAJOR_QCA9533_V2: - case REV_ID_MAJOR_QCA9556: - case REV_ID_MAJOR_QCA9558: -+ case REV_ID_MAJOR_TP9343: -+ case REV_ID_MAJOR_QCA956X: - _prom_putchar = prom_putchar_ar71xx; - break; - ---- a/arch/mips/ath79/gpio.c -+++ b/arch/mips/ath79/gpio.c -@@ -31,7 +31,10 @@ static void __iomem *ath79_gpio_get_func - soc_is_ar913x() || - soc_is_ar933x()) - reg = AR71XX_GPIO_REG_FUNC; -- else if (soc_is_ar934x() || soc_is_qca953x()) -+ else if (soc_is_ar934x() || -+ soc_is_qca953x() || -+ soc_is_qca956x() || -+ soc_is_tp9343()) - reg = AR934X_GPIO_REG_FUNC; - else - BUG(); -@@ -64,7 +67,7 @@ void __init ath79_gpio_output_select(uns - unsigned int reg; - u32 t, s; - -- BUG_ON(!soc_is_ar934x() && !soc_is_qca953x()); -+ BUG_ON(!soc_is_ar934x() && !soc_is_qca953x() && !soc_is_qca956x()); - - if (gpio >= AR934X_GPIO_COUNT) - return; ---- a/arch/mips/ath79/irq.c -+++ b/arch/mips/ath79/irq.c -@@ -156,6 +156,87 @@ static void qca955x_irq_init(void) - irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch); - } - -+static void qca956x_ip2_irq_dispatch(struct irq_desc *desc) -+{ -+ u32 status; -+ -+ status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS); -+ status &= QCA956X_EXT_INT_PCIE_RC1_ALL | QCA956X_EXT_INT_WMAC_ALL; -+ -+ if (status == 0) { -+ spurious_interrupt(); -+ return; -+ } -+ -+ if (status & QCA956X_EXT_INT_PCIE_RC1_ALL) { -+ /* TODO: flush DDR? */ -+ generic_handle_irq(ATH79_IP2_IRQ(0)); -+ } -+ -+ if (status & QCA956X_EXT_INT_WMAC_ALL) { -+ /* TODO: flsuh DDR? */ -+ generic_handle_irq(ATH79_IP2_IRQ(1)); -+ } -+} -+ -+static void qca956x_ip3_irq_dispatch(struct irq_desc *desc) -+{ -+ u32 status; -+ -+ status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS); -+ status &= QCA956X_EXT_INT_PCIE_RC2_ALL | -+ QCA956X_EXT_INT_USB1 | QCA956X_EXT_INT_USB2; -+ -+ if (status == 0) { -+ spurious_interrupt(); -+ return; -+ } -+ -+ if (status & QCA956X_EXT_INT_USB1) { -+ /* TODO: flush DDR? */ -+ generic_handle_irq(ATH79_IP3_IRQ(0)); -+ } -+ -+ if (status & QCA956X_EXT_INT_USB2) { -+ /* TODO: flush DDR? */ -+ generic_handle_irq(ATH79_IP3_IRQ(1)); -+ } -+ -+ if (status & QCA956X_EXT_INT_PCIE_RC2_ALL) { -+ /* TODO: flush DDR? */ -+ generic_handle_irq(ATH79_IP3_IRQ(2)); -+ } -+} -+ -+static void qca956x_enable_timer_cb(void) { -+ u32 misc; -+ -+ misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE); -+ misc |= MISC_INT_MIPS_SI_TIMERINT_MASK; -+ ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc); -+} -+ -+static void qca956x_irq_init(void) -+{ -+ int i; -+ -+ for (i = ATH79_IP2_IRQ_BASE; -+ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) -+ irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq); -+ -+ irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch); -+ -+ for (i = ATH79_IP3_IRQ_BASE; -+ i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++) -+ irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq); -+ -+ irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch); -+ -+ /* QCA956x timer init workaround has to be applied right before setting -+ * up the clock. Else, there will be no jiffies */ -+ late_time_init = &qca956x_enable_timer_cb; -+} -+ - void __init arch_init_irq(void) - { - unsigned irq_wb_chan2 = -1; -@@ -183,7 +264,9 @@ void __init arch_init_irq(void) - soc_is_ar933x() || - soc_is_ar934x() || - soc_is_qca953x() || -- soc_is_qca955x()) -+ soc_is_qca955x() || -+ soc_is_qca956x() || -+ soc_is_tp9343()) - misc_is_ar71xx = false; - else - BUG(); -@@ -197,4 +280,6 @@ void __init arch_init_irq(void) - qca953x_irq_init(); - else if (soc_is_qca955x()) - qca955x_irq_init(); -+ else if (soc_is_qca956x() || soc_is_tp9343()) -+ qca956x_irq_init(); - } ---- a/arch/mips/ath79/pci.c -+++ b/arch/mips/ath79/pci.c -@@ -68,6 +68,21 @@ static const struct ath79_pci_irq qca955 - }, - }; - -+static const struct ath79_pci_irq qca956x_pci_irq_map[] __initconst = { -+ { -+ .bus = 0, -+ .slot = 0, -+ .pin = 1, -+ .irq = ATH79_PCI_IRQ(0), -+ }, -+ { -+ .bus = 1, -+ .slot = 0, -+ .pin = 1, -+ .irq = ATH79_PCI_IRQ(1), -+ }, -+}; -+ - int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) - { - int irq = -1; -@@ -86,6 +101,9 @@ int __init pcibios_map_irq(const struct - } else if (soc_is_qca955x()) { - ath79_pci_irq_map = qca955x_pci_irq_map; - ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map); -+ } else if (soc_is_qca956x()) { -+ ath79_pci_irq_map = qca956x_pci_irq_map; -+ ath79_pci_nr_irqs = ARRAY_SIZE(qca956x_pci_irq_map); - } else { - pr_crit("pci %s: invalid irq map\n", - pci_name((struct pci_dev *) dev)); -@@ -303,6 +321,15 @@ int __init ath79_register_pci(void) - QCA955X_PCI_MEM_SIZE, - 1, - ATH79_IP3_IRQ(2)); -+ } else if (soc_is_qca956x()) { -+ pdev = ath79_register_pci_ar724x(0, -+ QCA956X_PCI_CFG_BASE1, -+ QCA956X_PCI_CTRL_BASE1, -+ QCA956X_PCI_CRP_BASE1, -+ QCA956X_PCI_MEM_BASE1, -+ QCA956X_PCI_MEM_SIZE, -+ 1, -+ ATH79_IP3_IRQ(2)); - } else { - /* No PCI support */ - return -ENODEV; ---- a/arch/mips/ath79/setup.c -+++ b/arch/mips/ath79/setup.c -@@ -176,6 +176,18 @@ static void __init ath79_detect_sys_type - rev = id & QCA955X_REV_ID_REVISION_MASK; - break; - -+ case REV_ID_MAJOR_QCA956X: -+ ath79_soc = ATH79_SOC_QCA956X; -+ chip = "956X"; -+ rev = id & QCA956X_REV_ID_REVISION_MASK; -+ break; -+ -+ case REV_ID_MAJOR_TP9343: -+ ath79_soc = ATH79_SOC_TP9343; -+ chip = "9343"; -+ rev = id & QCA956X_REV_ID_REVISION_MASK; -+ break; -+ - default: - panic("ath79: unknown SoC, id:0x%08x", id); - } -@@ -183,9 +195,12 @@ static void __init ath79_detect_sys_type - if (ver == 1) - ath79_soc_rev = rev; - -- if (soc_is_qca953x() || soc_is_qca955x()) -+ if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x()) - sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u", - chip, ver, rev); -+ else if (soc_is_tp9343()) -+ sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u", -+ chip, rev); - else - sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); - pr_info("SoC: %s\n", ath79_sys_type); ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -143,6 +143,23 @@ - #define QCA955X_NFC_BASE 0x1b800200 - #define QCA955X_NFC_SIZE 0xb8 - -+#define QCA956X_PCI_MEM_BASE1 0x12000000 -+#define QCA956X_PCI_MEM_SIZE 0x02000000 -+#define QCA956X_PCI_CFG_BASE1 0x16000000 -+#define QCA956X_PCI_CFG_SIZE 0x1000 -+#define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) -+#define QCA956X_PCI_CRP_SIZE 0x1000 -+#define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) -+#define QCA956X_PCI_CTRL_SIZE 0x100 -+ -+#define QCA956X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) -+#define QCA956X_WMAC_SIZE 0x20000 -+#define QCA956X_EHCI0_BASE 0x1b000000 -+#define QCA956X_EHCI1_BASE 0x1b400000 -+#define QCA956X_EHCI_SIZE 0x200 -+#define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) -+#define QCA956X_GMAC_SIZE 0x64 -+ - #define AR9300_OTP_BASE 0x14000 - #define AR9300_OTP_STATUS 0x15f18 - #define AR9300_OTP_STATUS_TYPE 0x7 -@@ -152,6 +169,13 @@ - #define AR9300_OTP_READ_DATA 0x15f1c - - /* -+ * Hidden Registers -+ */ -+#define QCA956X_DAM_RESET_OFFSET 0xb90001bc -+#define QCA956X_DAM_RESET_SIZE 0x4 -+#define QCA956X_INLINE_CHKSUM_ENG BIT(27) -+ -+/* - * DDR_CTRL block - */ - #define AR71XX_DDR_REG_PCI_WIN0 0x7c -@@ -385,6 +409,49 @@ - #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) - #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) - -+#define QCA956X_PLL_CPU_CONFIG_REG 0x00 -+#define QCA956X_PLL_CPU_CONFIG1_REG 0x04 -+#define QCA956X_PLL_DDR_CONFIG_REG 0x08 -+#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c -+#define QCA956X_PLL_CLK_CTRL_REG 0x10 -+ -+#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 -+#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f -+#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 -+#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 -+ -+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0 -+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f -+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5 -+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x1fff -+#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18 -+#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff -+ -+#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 -+#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f -+#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 -+#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 -+ -+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0 -+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f -+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5 -+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x1fff -+#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18 -+#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff -+ -+#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) -+#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) -+#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) -+#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 -+#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f -+#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 -+#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f -+#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 -+#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f -+#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20) -+#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21) -+#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) -+ - /* - * USB_CONFIG block - */ -@@ -432,6 +499,11 @@ - #define QCA955X_RESET_REG_BOOTSTRAP 0xb0 - #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac - -+#define QCA956X_RESET_REG_RESET_MODULE 0x1c -+#define QCA956X_RESET_REG_BOOTSTRAP 0xb0 -+#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac -+ -+#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28) - #define MISC_INT_ETHSW BIT(12) - #define MISC_INT_TIMER4 BIT(10) - #define MISC_INT_TIMER3 BIT(9) -@@ -606,6 +678,8 @@ - - #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) - -+#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2) -+ - #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) - #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) - #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) -@@ -673,6 +747,37 @@ - QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ - QCA955X_EXT_INT_PCIE_RC2_INT3) - -+#define QCA956X_EXT_INT_WMAC_MISC BIT(0) -+#define QCA956X_EXT_INT_WMAC_TX BIT(1) -+#define QCA956X_EXT_INT_WMAC_RXLP BIT(2) -+#define QCA956X_EXT_INT_WMAC_RXHP BIT(3) -+#define QCA956X_EXT_INT_PCIE_RC1 BIT(4) -+#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5) -+#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6) -+#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7) -+#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8) -+#define QCA956X_EXT_INT_PCIE_RC2 BIT(12) -+#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13) -+#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14) -+#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15) -+#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16) -+#define QCA956X_EXT_INT_USB1 BIT(24) -+#define QCA956X_EXT_INT_USB2 BIT(28) -+ -+#define QCA956X_EXT_INT_WMAC_ALL \ -+ (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \ -+ QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP) -+ -+#define QCA956X_EXT_INT_PCIE_RC1_ALL \ -+ (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \ -+ QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \ -+ QCA956X_EXT_INT_PCIE_RC1_INT3) -+ -+#define QCA956X_EXT_INT_PCIE_RC2_ALL \ -+ (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \ -+ QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \ -+ QCA956X_EXT_INT_PCIE_RC2_INT3) -+ - #define REV_ID_MAJOR_MASK 0xfff0 - #define REV_ID_MAJOR_AR71XX 0x00a0 - #define REV_ID_MAJOR_AR913X 0x00b0 -@@ -688,6 +793,8 @@ - #define REV_ID_MAJOR_QCA9533_V2 0x0160 - #define REV_ID_MAJOR_QCA9556 0x0130 - #define REV_ID_MAJOR_QCA9558 0x1130 -+#define REV_ID_MAJOR_TP9343 0x0150 -+#define REV_ID_MAJOR_QCA956X 0x1150 - - #define AR71XX_REV_ID_MINOR_MASK 0x3 - #define AR71XX_REV_ID_MINOR_AR7130 0x0 -@@ -712,6 +819,8 @@ - - #define QCA955X_REV_ID_REVISION_MASK 0xf - -+#define QCA956X_REV_ID_REVISION_MASK 0xf -+ - /* - * SPI block - */ -@@ -784,6 +893,19 @@ - #define QCA955X_GPIO_REG_OUT_FUNC5 0x40 - #define QCA955X_GPIO_REG_FUNC 0x6c - -+#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c -+#define QCA956X_GPIO_REG_OUT_FUNC1 0x30 -+#define QCA956X_GPIO_REG_OUT_FUNC2 0x34 -+#define QCA956X_GPIO_REG_OUT_FUNC3 0x38 -+#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c -+#define QCA956X_GPIO_REG_OUT_FUNC5 0x40 -+#define QCA956X_GPIO_REG_IN_ENABLE0 0x44 -+#define QCA956X_GPIO_REG_IN_ENABLE3 0x50 -+#define QCA956X_GPIO_REG_FUNC 0x6c -+ -+#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32 -+#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33 -+ - #define AR71XX_GPIO_COUNT 16 - #define AR7240_GPIO_COUNT 18 - #define AR7241_GPIO_COUNT 20 -@@ -792,6 +914,7 @@ - #define AR934X_GPIO_COUNT 23 - #define QCA953X_GPIO_COUNT 18 - #define QCA955X_GPIO_COUNT 24 -+#define QCA956X_GPIO_COUNT 23 - - /* - * SRIF block ---- a/arch/mips/include/asm/mach-ath79/ath79.h -+++ b/arch/mips/include/asm/mach-ath79/ath79.h -@@ -35,6 +35,8 @@ enum ath79_soc_type { - ATH79_SOC_QCA9533, - ATH79_SOC_QCA9556, - ATH79_SOC_QCA9558, -+ ATH79_SOC_TP9343, -+ ATH79_SOC_QCA956X, - }; - - extern enum ath79_soc_type ath79_soc; -@@ -126,6 +128,26 @@ static inline int soc_is_qca955x(void) - return soc_is_qca9556() || soc_is_qca9558(); - } - -+static inline int soc_is_tp9343(void) -+{ -+ return ath79_soc == ATH79_SOC_TP9343; -+} -+ -+static inline int soc_is_qca9561(void) -+{ -+ return ath79_soc == ATH79_SOC_QCA956X; -+} -+ -+static inline int soc_is_qca9563(void) -+{ -+ return ath79_soc == ATH79_SOC_QCA956X; -+} -+ -+static inline int soc_is_qca956x(void) -+{ -+ return soc_is_qca9561() || soc_is_qca9563(); -+} -+ - void ath79_ddr_wb_flush(unsigned int reg); - void ath79_ddr_set_pci_windows(void); - diff --git a/target/linux/ar71xx/patches-4.9/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-4.9/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch deleted file mode 100644 index cab2f6f9cb..0000000000 --- a/target/linux/ar71xx/patches-4.9/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch +++ /dev/null @@ -1,38 +0,0 @@ ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -157,6 +157,10 @@ - #define QCA956X_EHCI0_BASE 0x1b000000 - #define QCA956X_EHCI1_BASE 0x1b400000 - #define QCA956X_EHCI_SIZE 0x200 -+#define QCA956X_GMAC_SGMII_BASE (AR71XX_APB_BASE + 0x00070000) -+#define QCA956X_GMAC_SGMII_SIZE 0x64 -+#define QCA956X_PLL_BASE (AR71XX_APB_BASE + 0x00050000) -+#define QCA956X_PLL_SIZE 0x50 - #define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) - #define QCA956X_GMAC_SIZE 0x64 - -@@ -414,6 +418,7 @@ - #define QCA956X_PLL_DDR_CONFIG_REG 0x08 - #define QCA956X_PLL_DDR_CONFIG1_REG 0x0c - #define QCA956X_PLL_CLK_CTRL_REG 0x10 -+#define QCA956X_PLL_ETH_XMII_CONTROL_REG 0x30 - - #define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 - #define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f -@@ -1196,4 +1201,16 @@ - #define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3 - #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20 - -+/* -+ * QCA956X GMAC Interface -+ */ -+ -+#define QCA956X_GMAC_REG_ETH_CFG 0x00 -+ -+#define QCA956X_ETH_CFG_SW_ONLY_MODE BIT(7) -+#define QCA956X_ETH_CFG_SW_PHY_SWAP BIT(8) -+#define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(9) -+#define QCA956X_ETH_CFG_SW_APB_ACCESS BIT(10) -+#define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) -+ - #endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/target/linux/ar71xx/patches-4.9/630-MIPS-ath79-fix-chained-irq-disable.patch b/target/linux/ar71xx/patches-4.9/630-MIPS-ath79-fix-chained-irq-disable.patch deleted file mode 100644 index 2b92b88d03..0000000000 --- a/target/linux/ar71xx/patches-4.9/630-MIPS-ath79-fix-chained-irq-disable.patch +++ /dev/null @@ -1,106 +0,0 @@ ---- a/arch/mips/ath79/irq.c -+++ b/arch/mips/ath79/irq.c -@@ -27,6 +27,9 @@ - #include "machtypes.h" - - -+static struct irq_chip ip2_chip; -+static struct irq_chip ip3_chip; -+ - static void ar934x_ip2_irq_dispatch(struct irq_desc *desc) - { - u32 status; -@@ -50,8 +53,7 @@ static void ar934x_ip2_irq_init(void) - - for (i = ATH79_IP2_IRQ_BASE; - i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) -- irq_set_chip_and_handler(i, &dummy_irq_chip, -- handle_level_irq); -+ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq); - - irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch); - } -@@ -79,7 +81,7 @@ static void qca953x_irq_init(void) - - for (i = ATH79_IP2_IRQ_BASE; - i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) -- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq); -+ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq); - - irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch); - } -@@ -143,15 +145,13 @@ static void qca955x_irq_init(void) - - for (i = ATH79_IP2_IRQ_BASE; - i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) -- irq_set_chip_and_handler(i, &dummy_irq_chip, -- handle_level_irq); -+ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq); - - irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch); - - for (i = ATH79_IP3_IRQ_BASE; - i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++) -- irq_set_chip_and_handler(i, &dummy_irq_chip, -- handle_level_irq); -+ irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq); - - irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch); - } -@@ -222,13 +222,13 @@ static void qca956x_irq_init(void) - - for (i = ATH79_IP2_IRQ_BASE; - i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) -- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq); -+ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq); - - irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch); - - for (i = ATH79_IP3_IRQ_BASE; - i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++) -- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq); -+ irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq); - - irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch); - -@@ -237,12 +237,40 @@ static void qca956x_irq_init(void) - late_time_init = &qca956x_enable_timer_cb; - } - -+static void ath79_ip2_disable(struct irq_data *data) -+{ -+ disable_irq(ATH79_CPU_IRQ(2)); -+} -+ -+static void ath79_ip2_enable(struct irq_data *data) -+{ -+ enable_irq(ATH79_CPU_IRQ(2)); -+} -+ -+static void ath79_ip3_disable(struct irq_data *data) -+{ -+ disable_irq(ATH79_CPU_IRQ(3)); -+} -+ -+static void ath79_ip3_enable(struct irq_data *data) -+{ -+ enable_irq(ATH79_CPU_IRQ(3)); -+} -+ - void __init arch_init_irq(void) - { - unsigned irq_wb_chan2 = -1; - unsigned irq_wb_chan3 = -1; - bool misc_is_ar71xx; - -+ ip2_chip = dummy_irq_chip; -+ ip2_chip.irq_disable = ath79_ip2_disable; -+ ip2_chip.irq_enable = ath79_ip2_enable; -+ -+ ip3_chip = dummy_irq_chip; -+ ip3_chip.irq_disable = ath79_ip3_disable; -+ ip3_chip.irq_enable = ath79_ip3_enable; -+ - if (mips_machtype == ATH79_MACH_GENERIC_OF) { - irqchip_init(); - return; diff --git a/target/linux/ar71xx/patches-4.9/631-MIPS-ath79-wmac-enable-set-led-pin.patch b/target/linux/ar71xx/patches-4.9/631-MIPS-ath79-wmac-enable-set-led-pin.patch deleted file mode 100644 index a312217711..0000000000 --- a/target/linux/ar71xx/patches-4.9/631-MIPS-ath79-wmac-enable-set-led-pin.patch +++ /dev/null @@ -1,24 +0,0 @@ ---- a/arch/mips/ath79/dev-wmac.c -+++ b/arch/mips/ath79/dev-wmac.c -@@ -406,6 +406,11 @@ void __init ath79_wmac_set_ext_lna_gpio( - ar934x_set_ext_lna_gpio(chain, gpio); - } - -+void __init ath79_wmac_set_led_pin(int gpio) -+{ -+ ath79_wmac_data.led_pin = gpio; -+} -+ - void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr) - { - if (soc_is_ar913x()) ---- a/arch/mips/ath79/dev-wmac.h -+++ b/arch/mips/ath79/dev-wmac.h -@@ -18,6 +18,7 @@ void ath79_wmac_disable_2ghz(void); - void ath79_wmac_disable_5ghz(void); - void ath79_wmac_set_tx_gain_buffalo(void); - void ath79_wmac_set_ext_lna_gpio(unsigned chain, int gpio); -+void ath79_wmac_set_led_pin(int gpio); - - bool ar93xx_wmac_read_mac_address(u8 *dest); - diff --git a/target/linux/ar71xx/patches-4.9/632-MIPS-ath79-gpio-enable-set-direction.patch b/target/linux/ar71xx/patches-4.9/632-MIPS-ath79-gpio-enable-set-direction.patch deleted file mode 100644 index 4cf36325e1..0000000000 --- a/target/linux/ar71xx/patches-4.9/632-MIPS-ath79-gpio-enable-set-direction.patch +++ /dev/null @@ -1,32 +0,0 @@ ---- a/arch/mips/ath79/common.h -+++ b/arch/mips/ath79/common.h -@@ -28,6 +28,7 @@ void ath79_gpio_function_enable(u32 mask - void ath79_gpio_function_disable(u32 mask); - void ath79_gpio_function_setup(u32 set, u32 clear); - void ath79_gpio_output_select(unsigned gpio, u8 val); -+int ath79_gpio_direction_select(unsigned gpio, bool oe); - void ath79_gpio_init(void); - - #endif /* __ATH79_COMMON_H */ ---- a/arch/mips/ath79/gpio.c -+++ b/arch/mips/ath79/gpio.c -@@ -83,3 +83,19 @@ void __init ath79_gpio_output_select(uns - /* flush write */ - (void) __raw_readl(base + reg); - } -+ -+int ath79_gpio_direction_select(unsigned gpio, bool oe) -+{ -+ void __iomem *base = ath79_gpio_base; -+ bool ieq_1 = (soc_is_ar934x() || -+ soc_is_qca953x()); -+ -+ if ((ieq_1 && oe) || (!ieq_1 && !oe)) -+ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << gpio), -+ base + AR71XX_GPIO_REG_OE); -+ else -+ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << gpio), -+ base + AR71XX_GPIO_REG_OE); -+ -+ return 0; -+} diff --git a/target/linux/ar71xx/patches-4.9/640-MIPS-ath79-add-QCA955x-wmac-reset.patch b/target/linux/ar71xx/patches-4.9/640-MIPS-ath79-add-QCA955x-wmac-reset.patch deleted file mode 100644 index bb315a1e65..0000000000 --- a/target/linux/ar71xx/patches-4.9/640-MIPS-ath79-add-QCA955x-wmac-reset.patch +++ /dev/null @@ -1,82 +0,0 @@ ---- a/arch/mips/ath79/common.c -+++ b/arch/mips/ath79/common.c -@@ -38,7 +38,7 @@ unsigned int ath79_soc_rev; - void __iomem *ath79_pll_base; - void __iomem *ath79_reset_base; - EXPORT_SYMBOL_GPL(ath79_reset_base); --static void __iomem *ath79_ddr_base; -+void __iomem *ath79_ddr_base; - static void __iomem *ath79_ddr_wb_flush_base; - static void __iomem *ath79_ddr_pci_win_base; - ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -32,7 +32,7 @@ - #define AR71XX_SPI_SIZE 0x01000000 - - #define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) --#define AR71XX_DDR_CTRL_SIZE 0x100 -+#define AR71XX_DDR_CTRL_SIZE 0x200 - #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) - #define AR71XX_UART_SIZE 0x100 - #define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) -@@ -229,6 +229,9 @@ - #define QCA953X_DDR_REG_FLUSH_PCIE 0xa8 - #define QCA953X_DDR_REG_FLUSH_WMAC 0xac - -+#define QCA955X_DDR_CTL_CONFIG 0x108 -+#define QCA955X_DDR_CTL_CONFIG_ACT_WMAC BIT(23) -+ - /* - * PLL block - */ ---- a/arch/mips/ath79/dev-wmac.c -+++ b/arch/mips/ath79/dev-wmac.c -@@ -165,6 +165,27 @@ static void qca953x_wmac_setup(void) - ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision; - } - -+static int ar955x_wmac_reset(void) -+{ -+ int i; -+ -+ /* Try to wait for WMAC DDR activity to stop */ -+ for (i = 0; i < 10; i++) { -+ if (!(__raw_readl(ath79_ddr_base + QCA955X_DDR_CTL_CONFIG) & -+ QCA955X_DDR_CTL_CONFIG_ACT_WMAC)) -+ break; -+ -+ udelay(10); -+ } -+ -+ ath79_device_reset_set(QCA955X_RESET_RTC); -+ udelay(10); -+ ath79_device_reset_clear(QCA955X_RESET_RTC); -+ udelay(10); -+ -+ return 0; -+} -+ - static void qca955x_wmac_setup(void) - { - u32 t; -@@ -181,6 +202,8 @@ static void qca955x_wmac_setup(void) - ath79_wmac_data.is_clk_25mhz = false; - else - ath79_wmac_data.is_clk_25mhz = true; -+ -+ ath79_wmac_data.external_reset = ar955x_wmac_reset; - } - - #define AR93XX_WMAC_SIZE \ ---- a/arch/mips/ath79/common.h -+++ b/arch/mips/ath79/common.h -@@ -19,6 +19,8 @@ - #define ATH79_MEM_SIZE_MIN (2 * 1024 * 1024) - #define ATH79_MEM_SIZE_MAX (256 * 1024 * 1024) - -+extern void __iomem *ath79_ddr_base; -+ - void ath79_clocks_init(void); - unsigned long ath79_get_sys_clk_rate(const char *id); - diff --git a/target/linux/ar71xx/patches-4.9/700-MIPS-ath79-add-openwrt-Kconfig.patch b/target/linux/ar71xx/patches-4.9/700-MIPS-ath79-add-openwrt-Kconfig.patch deleted file mode 100644 index 5d4b180003..0000000000 --- a/target/linux/ar71xx/patches-4.9/700-MIPS-ath79-add-openwrt-Kconfig.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/mips/ath79/Kconfig -+++ b/arch/mips/ath79/Kconfig -@@ -82,6 +82,8 @@ config ATH79_MACH_UBNT_XM - Say 'Y' here if you want your kernel to support the - Ubiquiti Networks XM (rev 1.0) board. - -+source "arch/mips/ath79/Kconfig.openwrt" -+ - endmenu - - config SOC_AR71XX diff --git a/target/linux/ar71xx/patches-4.9/701-MIPS-ath79-add-routerboard-detection.patch b/target/linux/ar71xx/patches-4.9/701-MIPS-ath79-add-routerboard-detection.patch deleted file mode 100644 index ae9e7772b5..0000000000 --- a/target/linux/ar71xx/patches-4.9/701-MIPS-ath79-add-routerboard-detection.patch +++ /dev/null @@ -1,35 +0,0 @@ ---- a/arch/mips/ath79/prom.c -+++ b/arch/mips/ath79/prom.c -@@ -136,6 +136,32 @@ void __init prom_init(void) - initrd_end = initrd_start + fw_getenvl("initrd_size"); - } - #endif -+ -+ if (strstr(arcs_cmdline, "board=750Gr3") || -+ strstr(arcs_cmdline, "board=750i") || -+ strstr(arcs_cmdline, "board=750-hb") || -+ strstr(arcs_cmdline, "board=411") || -+ strstr(arcs_cmdline, "board=433") || -+ strstr(arcs_cmdline, "board=435") || -+ strstr(arcs_cmdline, "board=450") || -+ strstr(arcs_cmdline, "board=493") || -+ strstr(arcs_cmdline, "board=951G") || -+ strstr(arcs_cmdline, "board=H951L") || -+ strstr(arcs_cmdline, "board=952-hb") || -+ strstr(arcs_cmdline, "board=953gs") || -+ strstr(arcs_cmdline, "board=962") || -+ strstr(arcs_cmdline, "board=lhg") || -+ strstr(arcs_cmdline, "board=map-hb") || -+ strstr(arcs_cmdline, "board=map2-hb") || -+ strstr(arcs_cmdline, "board=wap-hb") || -+ strstr(arcs_cmdline, "board=wap-lte") || -+ strstr(arcs_cmdline, "board=wapg-sc") || -+ strstr(arcs_cmdline, "board=2011L") || -+ strstr(arcs_cmdline, "board=2011r") || -+ strstr(arcs_cmdline, "board=711Gr100") || -+ strstr(arcs_cmdline, "board=911L") || -+ strstr(arcs_cmdline, "board=922gs")) -+ ath79_prom_append_cmdline("console", "ttyS0,115200"); - } - - void __init prom_free_prom_memory(void) diff --git a/target/linux/ar71xx/patches-4.9/702-MIPS-ath79-fixup-routerboot-board-parameter.patch b/target/linux/ar71xx/patches-4.9/702-MIPS-ath79-fixup-routerboot-board-parameter.patch deleted file mode 100644 index b8715bba9e..0000000000 --- a/target/linux/ar71xx/patches-4.9/702-MIPS-ath79-fixup-routerboot-board-parameter.patch +++ /dev/null @@ -1,43 +0,0 @@ -From: Gabor Juhos <juhosg@freemail.hu> -Date: Sat, 2 Dec 2017 19:15:29 +0100 -Subject: [PATCH] MIPS: ath79: fix board detection with newer RouterBOOT versions - -Recent RouterBOOT version (at least version 3.41 on RB911G-5HPacD) -use "Board=" kernel parameter instead of "board=" to pass the board -name to the kernel. Due to this change the board detection code is -not working on the devices shipped with the new RouterBOOT version. -Because the kernel is unable to identify these boards they become -unusable despite that they are supported by the current code. - -Update the prom_init code to convert the 'Board' kernel parameter to -'board'. After this change, the board detection works also with the -new RouterBOOT versions. - -Signed-off-by: Gabor Juhos <juhosg@freemail.hu> ---- ---- a/arch/mips/ath79/prom.c -+++ b/arch/mips/ath79/prom.c -@@ -104,6 +104,7 @@ static int __init ath79_prom_init_myload - void __init prom_init(void) - { - const char *env; -+ char *c; - - if (ath79_prom_init_myloader()) - return; -@@ -137,6 +138,15 @@ void __init prom_init(void) - } - #endif - -+ /* -+ * RouterBOOT uses "Board" kernel parameter instead of "board" since -+ * version 3.41 (or so). Replace the first character of the parameter -+ * to keep board detection working. -+ */ -+ c = strstr(arcs_cmdline, "Board="); -+ if (c) -+ c[0] = 'b'; -+ - if (strstr(arcs_cmdline, "board=750Gr3") || - strstr(arcs_cmdline, "board=750i") || - strstr(arcs_cmdline, "board=750-hb") || diff --git a/target/linux/ar71xx/patches-4.9/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch b/target/linux/ar71xx/patches-4.9/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch deleted file mode 100644 index a65f7d993f..0000000000 --- a/target/linux/ar71xx/patches-4.9/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch +++ /dev/null @@ -1,38 +0,0 @@ ---- a/arch/mips/ath79/gpio.c -+++ b/arch/mips/ath79/gpio.c -@@ -33,6 +33,7 @@ static void __iomem *ath79_gpio_get_func - reg = AR71XX_GPIO_REG_FUNC; - else if (soc_is_ar934x() || - soc_is_qca953x() || -+ soc_is_qca955x() || - soc_is_qca956x() || - soc_is_tp9343()) - reg = AR934X_GPIO_REG_FUNC; -@@ -64,15 +65,21 @@ void ath79_gpio_function_disable(u32 mas - void __init ath79_gpio_output_select(unsigned gpio, u8 val) - { - void __iomem *base = ath79_gpio_base; -- unsigned int reg; -+ unsigned int reg, reg_base; - u32 t, s; - -- BUG_ON(!soc_is_ar934x() && !soc_is_qca953x() && !soc_is_qca956x()); -- -- if (gpio >= AR934X_GPIO_COUNT) -- return; -+ if (soc_is_ar934x()) -+ reg_base = AR934X_GPIO_REG_OUT_FUNC0; -+ else if (soc_is_qca953x()) -+ reg_base = QCA953X_GPIO_REG_OUT_FUNC0; -+ else if (soc_is_qca955x()) -+ reg_base = QCA955X_GPIO_REG_OUT_FUNC0; -+ else if (soc_is_qca956x()) -+ reg_base = QCA956X_GPIO_REG_OUT_FUNC0; -+ else -+ BUG(); - -- reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4); -+ reg = reg_base + 4 * (gpio / 4); - s = 8 * (gpio % 4); - - t = __raw_readl(base + reg); diff --git a/target/linux/ar71xx/patches-4.9/740-MIPS-ath79-add-PCI-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-4.9/740-MIPS-ath79-add-PCI-for-QCA953x-SoC.patch deleted file mode 100644 index a57351efde..0000000000 --- a/target/linux/ar71xx/patches-4.9/740-MIPS-ath79-add-PCI-for-QCA953x-SoC.patch +++ /dev/null @@ -1,44 +0,0 @@ ---- a/arch/mips/ath79/pci.c -+++ b/arch/mips/ath79/pci.c -@@ -53,6 +53,15 @@ static const struct ath79_pci_irq ar724x - } - }; - -+static const struct ath79_pci_irq qca953x_pci_irq_map[] __initconst = { -+ { -+ .bus = 0, -+ .slot = 0, -+ .pin = 1, -+ .irq = ATH79_PCI_IRQ(0), -+ }, -+}; -+ - static const struct ath79_pci_irq qca955x_pci_irq_map[] __initconst = { - { - .bus = 0, -@@ -98,6 +107,9 @@ int __init pcibios_map_irq(const struct - soc_is_ar9344()) { - ath79_pci_irq_map = ar724x_pci_irq_map; - ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map); -+ } else if (soc_is_qca953x()) { -+ ath79_pci_irq_map = qca953x_pci_irq_map; -+ ath79_pci_nr_irqs = ARRAY_SIZE(qca953x_pci_irq_map); - } else if (soc_is_qca955x()) { - ath79_pci_irq_map = qca955x_pci_irq_map; - ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map); -@@ -303,6 +315,15 @@ int __init ath79_register_pci(void) - AR724X_PCI_MEM_SIZE, - 0, - ATH79_IP2_IRQ(0)); -+ } else if (soc_is_qca9533()) { -+ pdev = ath79_register_pci_ar724x(0, -+ QCA953X_PCI_CFG_BASE0, -+ QCA953X_PCI_CTRL_BASE0, -+ QCA953X_PCI_CRP_BASE0, -+ QCA953X_PCI_MEM_BASE0, -+ QCA953X_PCI_MEM_SIZE, -+ 0, -+ ATH79_IP2_IRQ(0)); - } else if (soc_is_qca9558()) { - pdev = ath79_register_pci_ar724x(0, - QCA955X_PCI_CFG_BASE0, diff --git a/target/linux/ar71xx/patches-4.9/741-MIPS-ath79-add-PCI-for-QCA9556-SoC.patch b/target/linux/ar71xx/patches-4.9/741-MIPS-ath79-add-PCI-for-QCA9556-SoC.patch deleted file mode 100644 index 5ca0784253..0000000000 --- a/target/linux/ar71xx/patches-4.9/741-MIPS-ath79-add-PCI-for-QCA9556-SoC.patch +++ /dev/null @@ -1,12 +0,0 @@ ---- a/arch/mips/ath79/pci.c -+++ b/arch/mips/ath79/pci.c -@@ -324,7 +324,8 @@ int __init ath79_register_pci(void) - QCA953X_PCI_MEM_SIZE, - 0, - ATH79_IP2_IRQ(0)); -- } else if (soc_is_qca9558()) { -+ } else if (soc_is_qca9558() || -+ soc_is_qca9556()) { - pdev = ath79_register_pci_ar724x(0, - QCA955X_PCI_CFG_BASE0, - QCA955X_PCI_CTRL_BASE0, diff --git a/target/linux/ar71xx/patches-4.9/818-MIPS-ath79-add-nu801-led-driver.patch b/target/linux/ar71xx/patches-4.9/818-MIPS-ath79-add-nu801-led-driver.patch deleted file mode 100644 index 337447e2bf..0000000000 --- a/target/linux/ar71xx/patches-4.9/818-MIPS-ath79-add-nu801-led-driver.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/leds/Kconfig -+++ b/drivers/leds/Kconfig -@@ -606,6 +606,13 @@ config LEDS_IS31FL32XX - - comment "LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)" - -+config LEDS_NU801 -+ tristate "LED driver for NU801 RGB LED" -+ depends on LEDS_CLASS && (ATH79_MACH_MR18 || ATH79_MACH_Z1) -+ help -+ This option enables support for NU801 RGB LED driver chips -+ accessed via GPIO. -+ - config LEDS_BLINKM - tristate "LED support for the BlinkM I2C RGB LED" - depends on LEDS_CLASS ---- a/drivers/leds/Makefile -+++ b/drivers/leds/Makefile -@@ -56,6 +56,7 @@ obj-$(CONFIG_LEDS_ADP5520) += leds-adp5 - obj-$(CONFIG_LEDS_DELL_NETBOOKS) += dell-led.o - obj-$(CONFIG_LEDS_MC13783) += leds-mc13783.o - obj-$(CONFIG_LEDS_RB750) += leds-rb750.o -+obj-$(CONFIG_LEDS_NU801) += leds-nu801.o - obj-$(CONFIG_LEDS_NS2) += leds-ns2.o - obj-$(CONFIG_LEDS_NETXBIG) += leds-netxbig.o - obj-$(CONFIG_LEDS_ASIC3) += leds-asic3.o diff --git a/target/linux/ar71xx/patches-4.9/820-MIPS-ath79-add_gpio_function2_setup.patch b/target/linux/ar71xx/patches-4.9/820-MIPS-ath79-add_gpio_function2_setup.patch deleted file mode 100644 index afa7b69b43..0000000000 --- a/target/linux/ar71xx/patches-4.9/820-MIPS-ath79-add_gpio_function2_setup.patch +++ /dev/null @@ -1,67 +0,0 @@ -Add access to the function2 gpio register. This probably has to be -converted into a pimux driver later on. This is needed for some setup -functions on the Arduino Yun. - ---- a/arch/mips/ath79/common.h -+++ b/arch/mips/ath79/common.h -@@ -29,6 +29,7 @@ void ath79_ddr_ctrl_init(void); - void ath79_gpio_function_enable(u32 mask); - void ath79_gpio_function_disable(u32 mask); - void ath79_gpio_function_setup(u32 set, u32 clear); -+void ath79_gpio_function2_setup(u32 set, u32 clear); - void ath79_gpio_output_select(unsigned gpio, u8 val); - int ath79_gpio_direction_select(unsigned gpio, bool oe); - void ath79_gpio_init(void); ---- a/arch/mips/ath79/gpio.c -+++ b/arch/mips/ath79/gpio.c -@@ -43,6 +43,31 @@ static void __iomem *ath79_gpio_get_func - return ath79_gpio_base + reg; - } - -+static void __iomem *ath79_gpio_get_function2_reg(void) -+{ -+ u32 reg = 0; -+ -+ if (soc_is_ar71xx() || -+ soc_is_ar724x() || -+ soc_is_ar913x() || -+ soc_is_ar933x()) -+ reg = AR71XX_GPIO_REG_FUNC_2; -+ else -+ BUG(); -+ -+ return ath79_gpio_base + reg; -+} -+ -+ -+void ath79_gpio_function2_setup(u32 set, u32 clear) -+{ -+ void __iomem *reg = ath79_gpio_get_function2_reg(); -+ -+ __raw_writel((__raw_readl(reg) & ~clear) | set, reg); -+ /* flush write */ -+ __raw_readl(reg); -+} -+ - void ath79_gpio_function_setup(u32 set, u32 clear) - { - void __iomem *reg = ath79_gpio_get_function_reg(); ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -865,6 +865,7 @@ - #define AR71XX_GPIO_REG_INT_PENDING 0x20 - #define AR71XX_GPIO_REG_INT_ENABLE 0x24 - #define AR71XX_GPIO_REG_FUNC 0x28 -+#define AR71XX_GPIO_REG_FUNC_2 0x30 - - #define AR934X_GPIO_REG_OUT_FUNC0 0x2c - #define AR934X_GPIO_REG_OUT_FUNC1 0x30 -@@ -989,6 +990,8 @@ - #define AR724X_GPIO_FUNC_UART_EN BIT(1) - #define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) - -+#define AR933X_GPIO_FUNC2_JUMPSTART_DISABLE BIT(9) -+ - #define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22) - #define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) - #define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20) diff --git a/target/linux/ar71xx/patches-4.9/900-mdio_bitbang_ignore_ta_value.patch b/target/linux/ar71xx/patches-4.9/900-mdio_bitbang_ignore_ta_value.patch deleted file mode 100644 index 8f8f349a66..0000000000 --- a/target/linux/ar71xx/patches-4.9/900-mdio_bitbang_ignore_ta_value.patch +++ /dev/null @@ -1,32 +0,0 @@ ---- a/drivers/net/phy/mdio-bitbang.c -+++ b/drivers/net/phy/mdio-bitbang.c -@@ -155,7 +155,7 @@ static int mdiobb_cmd_addr(struct mdiobb - static int mdiobb_read(struct mii_bus *bus, int phy, int reg) - { - struct mdiobb_ctrl *ctrl = bus->priv; -- int ret, i; -+ int ret; - - if (reg & MII_ADDR_C45) { - reg = mdiobb_cmd_addr(ctrl, phy, reg); -@@ -165,19 +165,7 @@ static int mdiobb_read(struct mii_bus *b - - ctrl->ops->set_mdio_dir(ctrl, 0); - -- /* check the turnaround bit: the PHY should be driving it to zero, if this -- * PHY is listed in phy_ignore_ta_mask as having broken TA, skip that -- */ -- if (mdiobb_get_bit(ctrl) != 0 && -- !(bus->phy_ignore_ta_mask & (1 << phy))) { -- /* PHY didn't drive TA low -- flush any bits it -- * may be trying to send. -- */ -- for (i = 0; i < 32; i++) -- mdiobb_get_bit(ctrl); -- -- return 0xffff; -- } -+ mdiobb_get_bit(ctrl); - - ret = mdiobb_get_num(ctrl, 16); - mdiobb_get_bit(ctrl); diff --git a/target/linux/ar71xx/patches-4.9/901-phy-mdio-bitbang-prevent-rescheduling-during-command.patch b/target/linux/ar71xx/patches-4.9/901-phy-mdio-bitbang-prevent-rescheduling-during-command.patch deleted file mode 100644 index a830346a31..0000000000 --- a/target/linux/ar71xx/patches-4.9/901-phy-mdio-bitbang-prevent-rescheduling-during-command.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 66e584435ac0de6e0abeb6d7166fe4fe25d6bb73 Mon Sep 17 00:00:00 2001 -From: Jonas Gorski <jogo@openwrt.org> -Date: Tue, 16 Jun 2015 13:15:08 +0200 -Subject: [PATCH] phy/mdio-bitbang: prevent rescheduling during command - -It seems some phys have some maximum timings for accessing the MDIO line, -resulting in bit errors under cpu stress. Prevent this from happening by -disabling interrupts when sending commands. - -Signed-off-by: Jonas Gorski <jogo@openwrt.org> ---- - drivers/net/phy/mdio-bitbang.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/drivers/net/phy/mdio-bitbang.c -+++ b/drivers/net/phy/mdio-bitbang.c -@@ -17,6 +17,7 @@ - * kind, whether express or implied. - */ - -+#include <linux/irqflags.h> - #include <linux/module.h> - #include <linux/mdio-bitbang.h> - #include <linux/types.h> -@@ -156,7 +157,9 @@ static int mdiobb_read(struct mii_bus *b - { - struct mdiobb_ctrl *ctrl = bus->priv; - int ret; -+ unsigned long flags; - -+ local_irq_save(flags); - if (reg & MII_ADDR_C45) { - reg = mdiobb_cmd_addr(ctrl, phy, reg); - mdiobb_cmd(ctrl, MDIO_C45_READ, phy, reg); -@@ -169,13 +172,17 @@ static int mdiobb_read(struct mii_bus *b - - ret = mdiobb_get_num(ctrl, 16); - mdiobb_get_bit(ctrl); -+ local_irq_restore(flags); -+ - return ret; - } - - static int mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val) - { - struct mdiobb_ctrl *ctrl = bus->priv; -+ unsigned long flags; - -+ local_irq_save(flags); - if (reg & MII_ADDR_C45) { - reg = mdiobb_cmd_addr(ctrl, phy, reg); - mdiobb_cmd(ctrl, MDIO_C45_WRITE, phy, reg); -@@ -190,6 +197,8 @@ static int mdiobb_write(struct mii_bus * - - ctrl->ops->set_mdio_dir(ctrl, 0); - mdiobb_get_bit(ctrl); -+ local_irq_restore(flags); -+ - return 0; - } - diff --git a/target/linux/ar71xx/patches-4.9/902-at803x-add-reset-gpio-pdata.patch b/target/linux/ar71xx/patches-4.9/902-at803x-add-reset-gpio-pdata.patch deleted file mode 100644 index 7822158cf2..0000000000 --- a/target/linux/ar71xx/patches-4.9/902-at803x-add-reset-gpio-pdata.patch +++ /dev/null @@ -1,68 +0,0 @@ -Add support for configuring AT803x GPIO reset via platform data. -This is necessary, because ath79 is not converted to device tree yet. - -Signed-off-by: Felix Fietkau <nbd@nbd.name> - ---- a/include/linux/platform_data/phy-at803x.h -+++ b/include/linux/platform_data/phy-at803x.h -@@ -6,6 +6,8 @@ struct at803x_platform_data { - int enable_rgmii_tx_delay:1; - int enable_rgmii_rx_delay:1; - int fixup_rgmii_tx_delay:1; -+ int has_reset_gpio:1; -+ int reset_gpio; - }; - - #endif /* _PHY_AT803X_PDATA_H */ ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c -@@ -261,6 +261,7 @@ static int at803x_resume(struct phy_devi - - static int at803x_probe(struct phy_device *phydev) - { -+ struct at803x_platform_data *pdata; - struct device *dev = &phydev->mdio.dev; - struct at803x_priv *priv; - struct gpio_desc *gpiod_reset; -@@ -273,6 +274,12 @@ static int at803x_probe(struct phy_devic - phydev->drv->phy_id != ATH8032_PHY_ID) - goto does_not_require_reset_workaround; - -+ pdata = dev_get_platdata(dev); -+ if (pdata && pdata->has_reset_gpio) { -+ devm_gpio_request(dev, pdata->reset_gpio, "reset"); -+ gpio_direction_output(pdata->reset_gpio, 1); -+ } -+ - gpiod_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); - if (IS_ERR(gpiod_reset)) - return PTR_ERR(gpiod_reset); -@@ -404,15 +411,23 @@ static void at803x_link_change_notify(st - * cannot recover from by software. - */ - if (phydev->state == PHY_NOLINK) { -- if (priv->gpiod_reset && !priv->phy_reset) { -+ if ((priv->gpiod_reset || (pdata && pdata->has_reset_gpio)) && -+ !priv->phy_reset) { - struct at803x_context context; - - at803x_context_save(phydev, &context); - -- gpiod_set_value(priv->gpiod_reset, 1); -- msleep(1); -- gpiod_set_value(priv->gpiod_reset, 0); -- msleep(1); -+ if (pdata && pdata->has_reset_gpio) { -+ gpio_set_value_cansleep(pdata->reset_gpio, 0); -+ msleep(1); -+ gpio_set_value_cansleep(pdata->reset_gpio, 1); -+ msleep(1); -+ } else { -+ gpiod_set_value(priv->gpiod_reset, 1); -+ msleep(1); -+ gpiod_set_value(priv->gpiod_reset, 0); -+ msleep(1); -+ } - - at803x_context_restore(phydev, &context); - diff --git a/target/linux/ar71xx/patches-4.9/903-at803x-add-sgmii-aneg-override-pdata.patch b/target/linux/ar71xx/patches-4.9/903-at803x-add-sgmii-aneg-override-pdata.patch deleted file mode 100644 index fc640af17d..0000000000 --- a/target/linux/ar71xx/patches-4.9/903-at803x-add-sgmii-aneg-override-pdata.patch +++ /dev/null @@ -1,38 +0,0 @@ ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c -@@ -460,12 +460,15 @@ static void at803x_link_change_notify(st - - static int at803x_aneg_done(struct phy_device *phydev) - { -+ struct at803x_platform_data *pdata; - int ccr; - - int aneg_done = genphy_aneg_done(phydev); - if (aneg_done != BMSR_ANEGCOMPLETE) - return aneg_done; - -+ pdata = dev_get_platdata(&phydev->mdio.dev); -+ - /* - * in SGMII mode, if copper side autoneg is successful, - * also check SGMII side autoneg result -@@ -480,7 +483,8 @@ static int at803x_aneg_done(struct phy_d - /* check if the SGMII link is OK. */ - if (!(phy_read(phydev, AT803X_PSSR) & AT803X_PSSR_MR_AN_COMPLETE)) { - pr_warn("803x_aneg_done: SGMII link is not ok\n"); -- aneg_done = 0; -+ if (!pdata || !pdata->override_sgmii_aneg) -+ aneg_done = 0; - } - /* switch back to copper page */ - phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr | AT803X_BT_BX_REG_SEL); ---- a/include/linux/platform_data/phy-at803x.h -+++ b/include/linux/platform_data/phy-at803x.h -@@ -7,6 +7,7 @@ struct at803x_platform_data { - int enable_rgmii_rx_delay:1; - int fixup_rgmii_tx_delay:1; - int has_reset_gpio:1; -+ int override_sgmii_aneg:1; - int reset_gpio; - }; - diff --git a/target/linux/ar71xx/patches-4.9/910-unaligned_access_hacks.patch b/target/linux/ar71xx/patches-4.9/910-unaligned_access_hacks.patch deleted file mode 100644 index 049ee78d33..0000000000 --- a/target/linux/ar71xx/patches-4.9/910-unaligned_access_hacks.patch +++ /dev/null @@ -1,980 +0,0 @@ ---- a/arch/mips/include/asm/checksum.h -+++ b/arch/mips/include/asm/checksum.h -@@ -134,26 +134,30 @@ static inline __sum16 ip_fast_csum(const - const unsigned int *stop = word + ihl; - unsigned int csum; - int carry; -+ unsigned int w; - -- csum = word[0]; -- csum += word[1]; -- carry = (csum < word[1]); -+ csum = net_hdr_word(word++); -+ -+ w = net_hdr_word(word++); -+ csum += w; -+ carry = (csum < w); - csum += carry; - -- csum += word[2]; -- carry = (csum < word[2]); -+ w = net_hdr_word(word++); -+ csum += w; -+ carry = (csum < w); - csum += carry; - -- csum += word[3]; -- carry = (csum < word[3]); -+ w = net_hdr_word(word++); -+ csum += w; -+ carry = (csum < w); - csum += carry; - -- word += 4; - do { -- csum += *word; -- carry = (csum < *word); -+ w = net_hdr_word(word++); -+ csum += w; -+ carry = (csum < w); - csum += carry; -- word++; - } while (word != stop); - - return csum_fold(csum); -@@ -214,73 +218,6 @@ static inline __sum16 ip_compute_csum(co - return csum_fold(csum_partial(buff, len, 0)); - } - --#define _HAVE_ARCH_IPV6_CSUM --static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr, -- const struct in6_addr *daddr, -- __u32 len, __u8 proto, -- __wsum sum) --{ -- __wsum tmp; -- -- __asm__( -- " .set push # csum_ipv6_magic\n" -- " .set noreorder \n" -- " .set noat \n" -- " addu %0, %5 # proto (long in network byte order)\n" -- " sltu $1, %0, %5 \n" -- " addu %0, $1 \n" -- -- " addu %0, %6 # csum\n" -- " sltu $1, %0, %6 \n" -- " lw %1, 0(%2) # four words source address\n" -- " addu %0, $1 \n" -- " addu %0, %1 \n" -- " sltu $1, %0, %1 \n" -- -- " lw %1, 4(%2) \n" -- " addu %0, $1 \n" -- " addu %0, %1 \n" -- " sltu $1, %0, %1 \n" -- -- " lw %1, 8(%2) \n" -- " addu %0, $1 \n" -- " addu %0, %1 \n" -- " sltu $1, %0, %1 \n" -- -- " lw %1, 12(%2) \n" -- " addu %0, $1 \n" -- " addu %0, %1 \n" -- " sltu $1, %0, %1 \n" -- -- " lw %1, 0(%3) \n" -- " addu %0, $1 \n" -- " addu %0, %1 \n" -- " sltu $1, %0, %1 \n" -- -- " lw %1, 4(%3) \n" -- " addu %0, $1 \n" -- " addu %0, %1 \n" -- " sltu $1, %0, %1 \n" -- -- " lw %1, 8(%3) \n" -- " addu %0, $1 \n" -- " addu %0, %1 \n" -- " sltu $1, %0, %1 \n" -- -- " lw %1, 12(%3) \n" -- " addu %0, $1 \n" -- " addu %0, %1 \n" -- " sltu $1, %0, %1 \n" -- -- " addu %0, $1 # Add final carry\n" -- " .set pop" -- : "=&r" (sum), "=&r" (tmp) -- : "r" (saddr), "r" (daddr), -- "0" (htonl(len)), "r" (htonl(proto)), "r" (sum)); -- -- return csum_fold(sum); --} -- - #include <asm-generic/checksum.h> - #endif /* CONFIG_GENERIC_CSUM */ - ---- a/include/uapi/linux/ip.h -+++ b/include/uapi/linux/ip.h -@@ -102,7 +102,7 @@ struct iphdr { - __be32 saddr; - __be32 daddr; - /*The options start here. */ --}; -+} __attribute__((packed, aligned(2))); - - - struct ip_auth_hdr { ---- a/include/uapi/linux/ipv6.h -+++ b/include/uapi/linux/ipv6.h -@@ -129,7 +129,7 @@ struct ipv6hdr { - - struct in6_addr saddr; - struct in6_addr daddr; --}; -+} __attribute__((packed, aligned(2))); - - - /* index values for the variables in ipv6_devconf */ ---- a/include/uapi/linux/tcp.h -+++ b/include/uapi/linux/tcp.h -@@ -54,7 +54,7 @@ struct tcphdr { - __be16 window; - __sum16 check; - __be16 urg_ptr; --}; -+} __attribute__((packed, aligned(2))); - - /* - * The union cast uses a gcc extension to avoid aliasing problems -@@ -64,7 +64,7 @@ struct tcphdr { - union tcp_word_hdr { - struct tcphdr hdr; - __be32 words[5]; --}; -+} __attribute__((packed, aligned(2))); - - #define tcp_flag_word(tp) ( ((union tcp_word_hdr *)(tp))->words [3]) - ---- a/include/uapi/linux/udp.h -+++ b/include/uapi/linux/udp.h -@@ -24,7 +24,7 @@ struct udphdr { - __be16 dest; - __be16 len; - __sum16 check; --}; -+} __attribute__((packed, aligned(2))); - - /* UDP socket options */ - #define UDP_CORK 1 /* Never send partially complete segments */ ---- a/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c -+++ b/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c -@@ -41,8 +41,8 @@ static bool ipv4_pkt_to_tuple(const stru - if (ap == NULL) - return false; - -- tuple->src.u3.ip = ap[0]; -- tuple->dst.u3.ip = ap[1]; -+ tuple->src.u3.ip = net_hdr_word(ap++); -+ tuple->dst.u3.ip = net_hdr_word(ap); - - return true; - } ---- a/include/uapi/linux/icmp.h -+++ b/include/uapi/linux/icmp.h -@@ -81,7 +81,7 @@ struct icmphdr { - } frag; - __u8 reserved[4]; - } un; --}; -+} __attribute__((packed, aligned(2))); - - - /* ---- a/include/uapi/linux/in6.h -+++ b/include/uapi/linux/in6.h -@@ -42,7 +42,7 @@ struct in6_addr { - #define s6_addr16 in6_u.u6_addr16 - #define s6_addr32 in6_u.u6_addr32 - #endif --}; -+} __attribute__((packed, aligned(2))); - #endif /* __UAPI_DEF_IN6_ADDR */ - - #if __UAPI_DEF_SOCKADDR_IN6 ---- a/net/ipv6/tcp_ipv6.c -+++ b/net/ipv6/tcp_ipv6.c -@@ -39,6 +39,7 @@ - #include <linux/ipsec.h> - #include <linux/times.h> - #include <linux/slab.h> -+#include <asm/unaligned.h> - #include <linux/uaccess.h> - #include <linux/ipv6.h> - #include <linux/icmpv6.h> -@@ -796,10 +797,10 @@ static void tcp_v6_send_response(const s - topt = (__be32 *)(t1 + 1); - - if (tsecr) { -- *topt++ = htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) | -- (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP); -- *topt++ = htonl(tsval); -- *topt++ = htonl(tsecr); -+ put_unaligned_be32((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) | -+ (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP, topt++); -+ put_unaligned_be32(tsval, topt++); -+ put_unaligned_be32(tsecr, topt++); - } - - #ifdef CONFIG_TCP_MD5SIG ---- a/include/linux/ipv6.h -+++ b/include/linux/ipv6.h -@@ -5,6 +5,7 @@ - - #define ipv6_optlen(p) (((p)->hdrlen+1) << 3) - #define ipv6_authlen(p) (((p)->hdrlen+2) << 2) -+ - /* - * This structure contains configuration options per IPv6 link. - */ ---- a/net/ipv6/datagram.c -+++ b/net/ipv6/datagram.c -@@ -471,7 +471,7 @@ int ipv6_recv_error(struct sock *sk, str - ipv6_iface_scope_id(&sin->sin6_addr, - IP6CB(skb)->iif); - } else { -- ipv6_addr_set_v4mapped(*(__be32 *)(nh + serr->addr_offset), -+ ipv6_addr_set_v4mapped(net_hdr_word(nh + serr->addr_offset), - &sin->sin6_addr); - sin->sin6_scope_id = 0; - } -@@ -817,12 +817,12 @@ int ip6_datagram_send_ctl(struct net *ne - } - - if (fl6->flowlabel&IPV6_FLOWINFO_MASK) { -- if ((fl6->flowlabel^*(__be32 *)CMSG_DATA(cmsg))&~IPV6_FLOWINFO_MASK) { -+ if ((fl6->flowlabel^net_hdr_word(CMSG_DATA(cmsg)))&~IPV6_FLOWINFO_MASK) { - err = -EINVAL; - goto exit_f; - } - } -- fl6->flowlabel = IPV6_FLOWINFO_MASK & *(__be32 *)CMSG_DATA(cmsg); -+ fl6->flowlabel = IPV6_FLOWINFO_MASK & net_hdr_word(CMSG_DATA(cmsg)); - break; - - case IPV6_2292HOPOPTS: ---- a/net/ipv6/ip6_gre.c -+++ b/net/ipv6/ip6_gre.c -@@ -397,7 +397,7 @@ static void ip6gre_err(struct sk_buff *s - return; - ipv6h = (const struct ipv6hdr *)skb->data; - greh = (const struct gre_base_hdr *)(skb->data + offset); -- key = key_off ? *(__be32 *)(skb->data + key_off) : 0; -+ key = key_off ? net_hdr_word((__be32 *)(skb->data + key_off)) : 0; - - t = ip6gre_tunnel_lookup(skb->dev, &ipv6h->daddr, &ipv6h->saddr, - key, greh->protocol); ---- a/net/ipv6/exthdrs.c -+++ b/net/ipv6/exthdrs.c -@@ -574,7 +574,7 @@ static bool ipv6_hop_jumbo(struct sk_buf - goto drop; - } - -- pkt_len = ntohl(*(__be32 *)(nh + optoff + 2)); -+ pkt_len = ntohl(net_hdr_word(nh + optoff + 2)); - if (pkt_len <= IPV6_MAXPLEN) { - __IP6_INC_STATS(net, ipv6_skb_idev(skb), - IPSTATS_MIB_INHDRERRORS); ---- a/include/linux/types.h -+++ b/include/linux/types.h -@@ -231,5 +231,11 @@ typedef void (*call_rcu_func_t)(struct r - /* clocksource cycle base type */ - typedef u64 cycle_t; - -+struct net_hdr_word { -+ u32 words[1]; -+} __attribute__((packed, aligned(2))); -+ -+#define net_hdr_word(_p) (((struct net_hdr_word *) (_p))->words[0]) -+ - #endif /* __ASSEMBLY__ */ - #endif /* _LINUX_TYPES_H */ ---- a/net/ipv4/af_inet.c -+++ b/net/ipv4/af_inet.c -@@ -1319,8 +1319,8 @@ struct sk_buff **inet_gro_receive(struct - if (unlikely(ip_fast_csum((u8 *)iph, 5))) - goto out_unlock; - -- id = ntohl(*(__be32 *)&iph->id); -- flush = (u16)((ntohl(*(__be32 *)iph) ^ skb_gro_len(skb)) | (id & ~IP_DF)); -+ id = ntohl(net_hdr_word(&iph->id)); -+ flush = (u16)((ntohl(net_hdr_word(iph)) ^ skb_gro_len(skb)) | (id & ~IP_DF)); - id >>= 16; - - for (p = *head; p; p = p->next) { ---- a/net/ipv4/route.c -+++ b/net/ipv4/route.c -@@ -461,7 +461,7 @@ static struct neighbour *ipv4_neigh_look - else if (skb) - pkey = &ip_hdr(skb)->daddr; - -- n = __ipv4_neigh_lookup(dev, *(__force u32 *)pkey); -+ n = __ipv4_neigh_lookup(dev, net_hdr_word(pkey)); - if (n) - return n; - return neigh_create(&arp_tbl, pkey, dev); ---- a/net/ipv4/tcp_output.c -+++ b/net/ipv4/tcp_output.c -@@ -453,48 +453,53 @@ static void tcp_options_write(__be32 *pt - u16 options = opts->options; /* mungable copy */ - - if (unlikely(OPTION_MD5 & options)) { -- *ptr++ = htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) | -- (TCPOPT_MD5SIG << 8) | TCPOLEN_MD5SIG); -+ net_hdr_word(ptr++) = -+ htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) | -+ (TCPOPT_MD5SIG << 8) | TCPOLEN_MD5SIG); - /* overload cookie hash location */ - opts->hash_location = (__u8 *)ptr; - ptr += 4; - } - - if (unlikely(opts->mss)) { -- *ptr++ = htonl((TCPOPT_MSS << 24) | -- (TCPOLEN_MSS << 16) | -- opts->mss); -+ net_hdr_word(ptr++) = -+ htonl((TCPOPT_MSS << 24) | (TCPOLEN_MSS << 16) | -+ opts->mss); - } - - if (likely(OPTION_TS & options)) { - if (unlikely(OPTION_SACK_ADVERTISE & options)) { -- *ptr++ = htonl((TCPOPT_SACK_PERM << 24) | -- (TCPOLEN_SACK_PERM << 16) | -- (TCPOPT_TIMESTAMP << 8) | -- TCPOLEN_TIMESTAMP); -+ net_hdr_word(ptr++) = -+ htonl((TCPOPT_SACK_PERM << 24) | -+ (TCPOLEN_SACK_PERM << 16) | -+ (TCPOPT_TIMESTAMP << 8) | -+ TCPOLEN_TIMESTAMP); - options &= ~OPTION_SACK_ADVERTISE; - } else { -- *ptr++ = htonl((TCPOPT_NOP << 24) | -- (TCPOPT_NOP << 16) | -- (TCPOPT_TIMESTAMP << 8) | -- TCPOLEN_TIMESTAMP); -+ net_hdr_word(ptr++) = -+ htonl((TCPOPT_NOP << 24) | -+ (TCPOPT_NOP << 16) | -+ (TCPOPT_TIMESTAMP << 8) | -+ TCPOLEN_TIMESTAMP); - } -- *ptr++ = htonl(opts->tsval); -- *ptr++ = htonl(opts->tsecr); -+ net_hdr_word(ptr++) = htonl(opts->tsval); -+ net_hdr_word(ptr++) = htonl(opts->tsecr); - } - - if (unlikely(OPTION_SACK_ADVERTISE & options)) { -- *ptr++ = htonl((TCPOPT_NOP << 24) | -- (TCPOPT_NOP << 16) | -- (TCPOPT_SACK_PERM << 8) | -- TCPOLEN_SACK_PERM); -+ net_hdr_word(ptr++) = -+ htonl((TCPOPT_NOP << 24) | -+ (TCPOPT_NOP << 16) | -+ (TCPOPT_SACK_PERM << 8) | -+ TCPOLEN_SACK_PERM); - } - - if (unlikely(OPTION_WSCALE & options)) { -- *ptr++ = htonl((TCPOPT_NOP << 24) | -- (TCPOPT_WINDOW << 16) | -- (TCPOLEN_WINDOW << 8) | -- opts->ws); -+ net_hdr_word(ptr++) = -+ htonl((TCPOPT_NOP << 24) | -+ (TCPOPT_WINDOW << 16) | -+ (TCPOLEN_WINDOW << 8) | -+ opts->ws); - } - - if (unlikely(opts->num_sack_blocks)) { -@@ -502,16 +507,17 @@ static void tcp_options_write(__be32 *pt - tp->duplicate_sack : tp->selective_acks; - int this_sack; - -- *ptr++ = htonl((TCPOPT_NOP << 24) | -- (TCPOPT_NOP << 16) | -- (TCPOPT_SACK << 8) | -- (TCPOLEN_SACK_BASE + (opts->num_sack_blocks * -+ net_hdr_word(ptr++) = -+ htonl((TCPOPT_NOP << 24) | -+ (TCPOPT_NOP << 16) | -+ (TCPOPT_SACK << 8) | -+ (TCPOLEN_SACK_BASE + (opts->num_sack_blocks * - TCPOLEN_SACK_PERBLOCK))); - - for (this_sack = 0; this_sack < opts->num_sack_blocks; - ++this_sack) { -- *ptr++ = htonl(sp[this_sack].start_seq); -- *ptr++ = htonl(sp[this_sack].end_seq); -+ net_hdr_word(ptr++) = htonl(sp[this_sack].start_seq); -+ net_hdr_word(ptr++) = htonl(sp[this_sack].end_seq); - } - - tp->rx_opt.dsack = 0; -@@ -524,13 +530,14 @@ static void tcp_options_write(__be32 *pt - - if (foc->exp) { - len = TCPOLEN_EXP_FASTOPEN_BASE + foc->len; -- *ptr = htonl((TCPOPT_EXP << 24) | (len << 16) | -+ net_hdr_word(ptr) = -+ htonl((TCPOPT_EXP << 24) | (len << 16) | - TCPOPT_FASTOPEN_MAGIC); - p += TCPOLEN_EXP_FASTOPEN_BASE; - } else { - len = TCPOLEN_FASTOPEN_BASE + foc->len; -- *p++ = TCPOPT_FASTOPEN; -- *p++ = len; -+ net_hdr_word(p++) = TCPOPT_FASTOPEN; -+ net_hdr_word(p++) = len; - } - - memcpy(p, foc->val, foc->len); ---- a/net/ipv4/igmp.c -+++ b/net/ipv4/igmp.c -@@ -537,7 +537,7 @@ static struct sk_buff *add_grec(struct s - if (!skb) - return NULL; - psrc = (__be32 *)skb_put(skb, sizeof(__be32)); -- *psrc = psf->sf_inaddr; -+ net_hdr_word(psrc) = psf->sf_inaddr; - scount++; stotal++; - if ((type == IGMPV3_ALLOW_NEW_SOURCES || - type == IGMPV3_BLOCK_OLD_SOURCES) && psf->sf_crcount) { ---- a/include/uapi/linux/igmp.h -+++ b/include/uapi/linux/igmp.h -@@ -32,7 +32,7 @@ struct igmphdr { - __u8 code; /* For newer IGMP */ - __sum16 csum; - __be32 group; --}; -+} __attribute__((packed, aligned(2))); - - /* V3 group record types [grec_type] */ - #define IGMPV3_MODE_IS_INCLUDE 1 -@@ -48,7 +48,7 @@ struct igmpv3_grec { - __be16 grec_nsrcs; - __be32 grec_mca; - __be32 grec_src[0]; --}; -+} __attribute__((packed, aligned(2))); - - struct igmpv3_report { - __u8 type; -@@ -57,7 +57,7 @@ struct igmpv3_report { - __be16 resv2; - __be16 ngrec; - struct igmpv3_grec grec[0]; --}; -+} __attribute__((packed, aligned(2))); - - struct igmpv3_query { - __u8 type; -@@ -78,7 +78,7 @@ struct igmpv3_query { - __u8 qqic; - __be16 nsrcs; - __be32 srcs[0]; --}; -+} __attribute__((packed, aligned(2))); - - #define IGMP_HOST_MEMBERSHIP_QUERY 0x11 /* From RFC1112 */ - #define IGMP_HOST_MEMBERSHIP_REPORT 0x12 /* Ditto */ ---- a/net/core/flow_dissector.c -+++ b/net/core/flow_dissector.c -@@ -84,7 +84,7 @@ __be32 __skb_flow_get_ports(const struct - ports = __skb_header_pointer(skb, thoff + poff, - sizeof(_ports), data, hlen, &_ports); - if (ports) -- return *ports; -+ return (__be32)net_hdr_word(ports); - } - - return 0; ---- a/include/uapi/linux/icmpv6.h -+++ b/include/uapi/linux/icmpv6.h -@@ -76,7 +76,7 @@ struct icmp6hdr { - #define icmp6_addrconf_other icmp6_dataun.u_nd_ra.other - #define icmp6_rt_lifetime icmp6_dataun.u_nd_ra.rt_lifetime - #define icmp6_router_pref icmp6_dataun.u_nd_ra.router_pref --}; -+} __attribute__((packed, aligned(2))); - - - #define ICMPV6_ROUTER_PREF_LOW 0x3 ---- a/include/net/ndisc.h -+++ b/include/net/ndisc.h -@@ -87,7 +87,7 @@ struct ra_msg { - struct icmp6hdr icmph; - __be32 reachable_time; - __be32 retrans_timer; --}; -+} __attribute__((packed, aligned(2))); - - struct rd_msg { - struct icmp6hdr icmph; -@@ -365,10 +365,10 @@ static inline u32 ndisc_hashfn(const voi - { - const u32 *p32 = pkey; - -- return (((p32[0] ^ hash32_ptr(dev)) * hash_rnd[0]) + -- (p32[1] * hash_rnd[1]) + -- (p32[2] * hash_rnd[2]) + -- (p32[3] * hash_rnd[3])); -+ return (((net_hdr_word(&p32[0]) ^ hash32_ptr(dev)) * hash_rnd[0]) + -+ (net_hdr_word(&p32[1]) * hash_rnd[1]) + -+ (net_hdr_word(&p32[2]) * hash_rnd[2]) + -+ (net_hdr_word(&p32[3]) * hash_rnd[3])); - } - - static inline struct neighbour *__ipv6_neigh_lookup_noref(struct net_device *dev, const void *pkey) ---- a/net/sched/cls_u32.c -+++ b/net/sched/cls_u32.c -@@ -159,7 +159,7 @@ next_knode: - data = skb_header_pointer(skb, toff, 4, &hdata); - if (!data) - goto out; -- if ((*data ^ key->val) & key->mask) { -+ if ((net_hdr_word(data) ^ key->val) & key->mask) { - n = rcu_dereference_bh(n->next); - goto next_knode; - } -@@ -212,8 +212,8 @@ check_terminal: - &hdata); - if (!data) - goto out; -- sel = ht->divisor & u32_hash_fold(*data, &n->sel, -- n->fshift); -+ sel = ht->divisor & u32_hash_fold(net_hdr_word(data), -+ &n->sel, n->fshift); - } - if (!(n->sel.flags & (TC_U32_VAROFFSET | TC_U32_OFFSET | TC_U32_EAT))) - goto next_ht; ---- a/net/ipv6/ip6_offload.c -+++ b/net/ipv6/ip6_offload.c -@@ -221,7 +221,7 @@ static struct sk_buff **ipv6_gro_receive - continue; - - iph2 = (struct ipv6hdr *)(p->data + off); -- first_word = *(__be32 *)iph ^ *(__be32 *)iph2; -+ first_word = net_hdr_word(iph) ^ net_hdr_word(iph2); - - /* All fields must match except length and Traffic Class. - * XXX skbs on the gro_list have all been parsed and pulled ---- a/include/net/addrconf.h -+++ b/include/net/addrconf.h -@@ -46,7 +46,7 @@ struct prefix_info { - __be32 reserved2; - - struct in6_addr prefix; --}; -+} __attribute__((packed, aligned(2))); - - - #include <linux/netdevice.h> ---- a/include/net/inet_ecn.h -+++ b/include/net/inet_ecn.h -@@ -124,9 +124,9 @@ static inline int IP6_ECN_set_ce(struct - if (INET_ECN_is_not_ect(ipv6_get_dsfield(iph))) - return 0; - -- from = *(__be32 *)iph; -+ from = net_hdr_word(iph); - to = from | htonl(INET_ECN_CE << 20); -- *(__be32 *)iph = to; -+ net_hdr_word(iph) = to; - if (skb->ip_summed == CHECKSUM_COMPLETE) - skb->csum = csum_add(csum_sub(skb->csum, (__force __wsum)from), - (__force __wsum)to); -@@ -135,7 +135,7 @@ static inline int IP6_ECN_set_ce(struct - - static inline void IP6_ECN_clear(struct ipv6hdr *iph) - { -- *(__be32*)iph &= ~htonl(INET_ECN_MASK << 20); -+ net_hdr_word(iph) &= ~htonl(INET_ECN_MASK << 20); - } - - static inline void ipv6_copy_dscp(unsigned int dscp, struct ipv6hdr *inner) ---- a/include/net/ipv6.h -+++ b/include/net/ipv6.h -@@ -107,7 +107,7 @@ struct frag_hdr { - __u8 reserved; - __be16 frag_off; - __be32 identification; --}; -+} __attribute__((packed, aligned(2))); - - #define IP6_MF 0x0001 - #define IP6_OFFSET 0xFFF8 -@@ -443,8 +443,8 @@ static inline void __ipv6_addr_set_half( - } - #endif - #endif -- addr[0] = wh; -- addr[1] = wl; -+ net_hdr_word(&addr[0]) = wh; -+ net_hdr_word(&addr[1]) = wl; - } - - static inline void ipv6_addr_set(struct in6_addr *addr, -@@ -503,6 +503,8 @@ static inline bool ipv6_prefix_equal(con - const __be32 *a1 = addr1->s6_addr32; - const __be32 *a2 = addr2->s6_addr32; - unsigned int pdw, pbi; -+ /* Used for last <32-bit fraction of prefix */ -+ u32 pbia1, pbia2; - - /* check complete u32 in prefix */ - pdw = prefixlen >> 5; -@@ -511,7 +513,9 @@ static inline bool ipv6_prefix_equal(con - - /* check incomplete u32 in prefix */ - pbi = prefixlen & 0x1f; -- if (pbi && ((a1[pdw] ^ a2[pdw]) & htonl((0xffffffff) << (32 - pbi)))) -+ pbia1 = net_hdr_word(&a1[pdw]); -+ pbia2 = net_hdr_word(&a2[pdw]); -+ if (pbi && ((pbia1 ^ pbia2) & htonl((0xffffffff) << (32 - pbi)))) - return false; - - return true; -@@ -655,13 +659,13 @@ static inline void ipv6_addr_set_v4mappe - */ - static inline int __ipv6_addr_diff32(const void *token1, const void *token2, int addrlen) - { -- const __be32 *a1 = token1, *a2 = token2; -+ const struct in6_addr *a1 = token1, *a2 = token2; - int i; - - addrlen >>= 2; - - for (i = 0; i < addrlen; i++) { -- __be32 xb = a1[i] ^ a2[i]; -+ __be32 xb = a1->s6_addr32[i] ^ a2->s6_addr32[i]; - if (xb) - return i * 32 + 31 - __fls(ntohl(xb)); - } -@@ -830,17 +834,18 @@ static inline int ip6_default_np_autolab - static inline void ip6_flow_hdr(struct ipv6hdr *hdr, unsigned int tclass, - __be32 flowlabel) - { -- *(__be32 *)hdr = htonl(0x60000000 | (tclass << 20)) | flowlabel; -+ net_hdr_word((__be32 *)hdr) = -+ htonl(0x60000000 | (tclass << 20)) | flowlabel; - } - - static inline __be32 ip6_flowinfo(const struct ipv6hdr *hdr) - { -- return *(__be32 *)hdr & IPV6_FLOWINFO_MASK; -+ return net_hdr_word((__be32 *)hdr) & IPV6_FLOWINFO_MASK; - } - - static inline __be32 ip6_flowlabel(const struct ipv6hdr *hdr) - { -- return *(__be32 *)hdr & IPV6_FLOWLABEL_MASK; -+ return net_hdr_word((__be32 *)hdr) & IPV6_FLOWLABEL_MASK; - } - - static inline u8 ip6_tclass(__be32 flowinfo) ---- a/include/net/secure_seq.h -+++ b/include/net/secure_seq.h -@@ -2,6 +2,7 @@ - #define _NET_SECURE_SEQ - - #include <linux/types.h> -+#include <linux/in6.h> - - u32 secure_ipv4_port_ephemeral(__be32 saddr, __be32 daddr, __be16 dport); - u32 secure_ipv6_port_ephemeral(const __be32 *saddr, const __be32 *daddr, ---- a/include/uapi/linux/in.h -+++ b/include/uapi/linux/in.h -@@ -83,7 +83,7 @@ enum { - /* Internet address. */ - struct in_addr { - __be32 s_addr; --}; -+} __attribute__((packed, aligned(2))); - #endif - - #define IP_TOS 1 ---- a/net/core/secure_seq.c -+++ b/net/core/secure_seq.c -@@ -46,11 +46,12 @@ __u32 secure_tcpv6_sequence_number(const - u32 secret[MD5_MESSAGE_BYTES / 4]; - u32 hash[MD5_DIGEST_WORDS]; - u32 i; -+ const struct in6_addr *daddr6 = (struct in6_addr *) daddr; - - net_secret_init(); - memcpy(hash, saddr, 16); - for (i = 0; i < 4; i++) -- secret[i] = net_secret[i] + (__force u32)daddr[i]; -+ secret[i] = net_secret[i] + (__force u32)daddr6->s6_addr32[i]; - secret[4] = net_secret[4] + - (((__force u16)sport << 16) + (__force u16)dport); - for (i = 5; i < MD5_MESSAGE_BYTES / 4; i++) -@@ -68,11 +69,12 @@ u32 secure_ipv6_port_ephemeral(const __b - u32 secret[MD5_MESSAGE_BYTES / 4]; - u32 hash[MD5_DIGEST_WORDS]; - u32 i; -+ const struct in6_addr *daddr6 = (struct in6_addr *) daddr; - - net_secret_init(); - memcpy(hash, saddr, 16); - for (i = 0; i < 4; i++) -- secret[i] = net_secret[i] + (__force u32) daddr[i]; -+ secret[i] = net_secret[i] + (__force u32) daddr6->s6_addr32[i]; - secret[4] = net_secret[4] + (__force u32)dport; - for (i = 5; i < MD5_MESSAGE_BYTES / 4; i++) - secret[i] = net_secret[i]; -@@ -146,6 +148,7 @@ EXPORT_SYMBOL(secure_dccp_sequence_numbe - u64 secure_dccpv6_sequence_number(__be32 *saddr, __be32 *daddr, - __be16 sport, __be16 dport) - { -+ const struct in6_addr *daddr6 = (struct in6_addr *) daddr; - u32 secret[MD5_MESSAGE_BYTES / 4]; - u32 hash[MD5_DIGEST_WORDS]; - u64 seq; -@@ -154,7 +157,7 @@ u64 secure_dccpv6_sequence_number(__be32 - net_secret_init(); - memcpy(hash, saddr, 16); - for (i = 0; i < 4; i++) -- secret[i] = net_secret[i] + (__force u32)daddr[i]; -+ secret[i] = net_secret[i] + (__force u32)daddr6->s6_addr32[i]; - secret[4] = net_secret[4] + - (((__force u16)sport << 16) + (__force u16)dport); - for (i = 5; i < MD5_MESSAGE_BYTES / 4; i++) ---- a/net/ipv6/ip6_fib.c -+++ b/net/ipv6/ip6_fib.c -@@ -136,7 +136,7 @@ static __be32 addr_bit_set(const void *t - * See include/asm-generic/bitops/le.h. - */ - return (__force __be32)(1 << ((~fn_bit ^ BITOP_BE32_SWIZZLE) & 0x1f)) & -- addr[fn_bit >> 5]; -+ net_hdr_word(&addr[fn_bit >> 5]); - } - - static struct fib6_node *node_alloc(void) ---- a/net/netfilter/nf_conntrack_proto_tcp.c -+++ b/net/netfilter/nf_conntrack_proto_tcp.c -@@ -452,7 +452,7 @@ static void tcp_sack(const struct sk_buf - - /* Fast path for timestamp-only option */ - if (length == TCPOLEN_TSTAMP_ALIGNED -- && *(__be32 *)ptr == htonl((TCPOPT_NOP << 24) -+ && net_hdr_word(ptr) == htonl((TCPOPT_NOP << 24) - | (TCPOPT_NOP << 16) - | (TCPOPT_TIMESTAMP << 8) - | TCPOLEN_TIMESTAMP)) ---- a/net/xfrm/xfrm_input.c -+++ b/net/xfrm/xfrm_input.c -@@ -154,8 +154,8 @@ int xfrm_parse_spi(struct sk_buff *skb, - if (!pskb_may_pull(skb, hlen)) - return -EINVAL; - -- *spi = *(__be32 *)(skb_transport_header(skb) + offset); -- *seq = *(__be32 *)(skb_transport_header(skb) + offset_seq); -+ *spi = net_hdr_word(skb_transport_header(skb) + offset); -+ *seq = net_hdr_word(skb_transport_header(skb) + offset_seq); - return 0; - } - ---- a/net/ipv4/tcp_input.c -+++ b/net/ipv4/tcp_input.c -@@ -3910,14 +3910,16 @@ static bool tcp_parse_aligned_timestamp( - { - const __be32 *ptr = (const __be32 *)(th + 1); - -- if (*ptr == htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) -- | (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) { -+ if (net_hdr_word(ptr) == -+ htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) | -+ (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) { - tp->rx_opt.saw_tstamp = 1; - ++ptr; -- tp->rx_opt.rcv_tsval = ntohl(*ptr); -+ tp->rx_opt.rcv_tsval = get_unaligned_be32(ptr); - ++ptr; -- if (*ptr) -- tp->rx_opt.rcv_tsecr = ntohl(*ptr) - tp->tsoffset; -+ if (net_hdr_word(ptr)) -+ tp->rx_opt.rcv_tsecr = get_unaligned_be32(ptr) - -+ tp->tsoffset; - else - tp->rx_opt.rcv_tsecr = 0; - return true; ---- a/include/uapi/linux/if_pppox.h -+++ b/include/uapi/linux/if_pppox.h -@@ -50,6 +50,7 @@ struct pppoe_addr { - */ - struct pptp_addr { - __u16 call_id; -+ __u16 pad; - struct in_addr sin_addr; - }; - ---- a/net/ipv6/netfilter/nf_log_ipv6.c -+++ b/net/ipv6/netfilter/nf_log_ipv6.c -@@ -66,9 +66,9 @@ static void dump_ipv6_packet(struct nf_l - /* Max length: 44 "LEN=65535 TC=255 HOPLIMIT=255 FLOWLBL=FFFFF " */ - nf_log_buf_add(m, "LEN=%Zu TC=%u HOPLIMIT=%u FLOWLBL=%u ", - ntohs(ih->payload_len) + sizeof(struct ipv6hdr), -- (ntohl(*(__be32 *)ih) & 0x0ff00000) >> 20, -+ (ntohl(net_hdr_word(ih)) & 0x0ff00000) >> 20, - ih->hop_limit, -- (ntohl(*(__be32 *)ih) & 0x000fffff)); -+ (ntohl(net_hdr_word(ih)) & 0x000fffff)); - - fragment = 0; - ptr = ip6hoff + sizeof(struct ipv6hdr); ---- a/include/net/neighbour.h -+++ b/include/net/neighbour.h -@@ -263,8 +263,10 @@ static inline bool neigh_key_eq128(const - const u32 *n32 = (const u32 *)n->primary_key; - const u32 *p32 = pkey; - -- return ((n32[0] ^ p32[0]) | (n32[1] ^ p32[1]) | -- (n32[2] ^ p32[2]) | (n32[3] ^ p32[3])) == 0; -+ return ((n32[0] ^ net_hdr_word(&p32[0])) | -+ (n32[1] ^ net_hdr_word(&p32[1])) | -+ (n32[2] ^ net_hdr_word(&p32[2])) | -+ (n32[3] ^ net_hdr_word(&p32[3]))) == 0; - } - - static inline struct neighbour *___neigh_lookup_noref( ---- a/include/uapi/linux/netfilter_arp/arp_tables.h -+++ b/include/uapi/linux/netfilter_arp/arp_tables.h -@@ -69,7 +69,7 @@ struct arpt_arp { - __u8 flags; - /* Inverse flags */ - __u16 invflags; --}; -+} __attribute__((aligned(4))); - - /* Values for "flag" field in struct arpt_ip (general arp structure). - * No flags defined yet. ---- a/net/core/utils.c -+++ b/net/core/utils.c -@@ -321,8 +321,14 @@ void inet_proto_csum_replace16(__sum16 * - bool pseudohdr) - { - __be32 diff[] = { -- ~from[0], ~from[1], ~from[2], ~from[3], -- to[0], to[1], to[2], to[3], -+ ~net_hdr_word(&from[0]), -+ ~net_hdr_word(&from[1]), -+ ~net_hdr_word(&from[2]), -+ ~net_hdr_word(&from[3]), -+ net_hdr_word(&to[0]), -+ net_hdr_word(&to[1]), -+ net_hdr_word(&to[2]), -+ net_hdr_word(&to[3]), - }; - if (skb->ip_summed != CHECKSUM_PARTIAL) { - *sum = csum_fold(csum_partial(diff, sizeof(diff), ---- a/drivers/net/vxlan.c -+++ b/drivers/net/vxlan.c -@@ -1789,15 +1789,15 @@ static int vxlan_build_skb(struct sk_buf - goto out_free; - - vxh = (struct vxlanhdr *) __skb_push(skb, sizeof(*vxh)); -- vxh->vx_flags = VXLAN_HF_VNI; -- vxh->vx_vni = vxlan_vni_field(vni); -+ net_hdr_word(&vxh->vx_flags) = VXLAN_HF_VNI; -+ net_hdr_word(&vxh->vx_vni) = vxlan_vni_field(vni); - - if (type & SKB_GSO_TUNNEL_REMCSUM) { - unsigned int start; - - start = skb_checksum_start_offset(skb) - sizeof(struct vxlanhdr); -- vxh->vx_vni |= vxlan_compute_rco(start, skb->csum_offset); -- vxh->vx_flags |= VXLAN_HF_RCO; -+ net_hdr_word(&vxh->vx_vni) |= vxlan_compute_rco(start, skb->csum_offset); -+ net_hdr_word(&vxh->vx_flags) |= VXLAN_HF_RCO; - - if (!skb_is_gso(skb)) { - skb->ip_summed = CHECKSUM_NONE; ---- a/include/linux/etherdevice.h -+++ b/include/linux/etherdevice.h -@@ -435,7 +435,7 @@ static inline bool is_etherdev_addr(cons - * @b: Pointer to Ethernet header - * - * Compare two Ethernet headers, returns 0 if equal. -- * This assumes that the network header (i.e., IP header) is 4-byte -+ * This assumes that the network header (i.e., IP header) is 2-byte - * aligned OR the platform can handle unaligned access. This is the - * case for all packets coming into netif_receive_skb or similar - * entry points. -@@ -458,11 +458,12 @@ static inline unsigned long compare_ethe - fold |= *(unsigned long *)(a + 6) ^ *(unsigned long *)(b + 6); - return fold; - #else -- u32 *a32 = (u32 *)((u8 *)a + 2); -- u32 *b32 = (u32 *)((u8 *)b + 2); -+ const u16 *a16 = a; -+ const u16 *b16 = b; - -- return (*(u16 *)a ^ *(u16 *)b) | (a32[0] ^ b32[0]) | -- (a32[1] ^ b32[1]) | (a32[2] ^ b32[2]); -+ return (a16[0] ^ b16[0]) | (a16[1] ^ b16[1]) | (a16[2] ^ b16[2]) | -+ (a16[3] ^ b16[3]) | (a16[4] ^ b16[4]) | (a16[5] ^ b16[5]) | -+ (a16[6] ^ b16[6]); - #endif - } - ---- a/net/ipv4/tcp_offload.c -+++ b/net/ipv4/tcp_offload.c -@@ -218,7 +218,7 @@ struct sk_buff **tcp_gro_receive(struct - - th2 = tcp_hdr(p); - -- if (*(u32 *)&th->source ^ *(u32 *)&th2->source) { -+ if (net_hdr_word(&th->source) ^ net_hdr_word(&th2->source)) { - NAPI_GRO_CB(p)->same_flow = 0; - continue; - } -@@ -236,8 +236,8 @@ found: - ~(TCP_FLAG_CWR | TCP_FLAG_FIN | TCP_FLAG_PSH)); - flush |= (__force int)(th->ack_seq ^ th2->ack_seq); - for (i = sizeof(*th); i < thlen; i += 4) -- flush |= *(u32 *)((u8 *)th + i) ^ -- *(u32 *)((u8 *)th2 + i); -+ flush |= net_hdr_word((u8 *)th + i) ^ -+ net_hdr_word((u8 *)th2 + i); - - /* When we receive our second frame we can made a decision on if we - * continue this flow as an atomic flow with a fixed ID or if we use ---- a/net/ipv6/netfilter/ip6table_mangle.c -+++ b/net/ipv6/netfilter/ip6table_mangle.c -@@ -58,7 +58,7 @@ ip6t_mangle_out(struct sk_buff *skb, con - hop_limit = ipv6_hdr(skb)->hop_limit; - - /* flowlabel and prio (includes version, which shouldn't change either */ -- flowlabel = *((u_int32_t *)ipv6_hdr(skb)); -+ flowlabel = net_hdr_word(ipv6_hdr(skb)); - - ret = ip6t_do_table(skb, state, state->net->ipv6.ip6table_mangle); - -@@ -67,7 +67,7 @@ ip6t_mangle_out(struct sk_buff *skb, con - !ipv6_addr_equal(&ipv6_hdr(skb)->daddr, &daddr) || - skb->mark != mark || - ipv6_hdr(skb)->hop_limit != hop_limit || -- flowlabel != *((u_int32_t *)ipv6_hdr(skb)))) { -+ flowlabel != net_hdr_word(ipv6_hdr(skb)))) { - err = ip6_route_me_harder(state->net, skb); - if (err < 0) - ret = NF_DROP_ERR(err); diff --git a/target/linux/ar71xx/patches-4.9/920-usb-chipidea-AR933x-platform-support.patch b/target/linux/ar71xx/patches-4.9/920-usb-chipidea-AR933x-platform-support.patch deleted file mode 100644 index b0e69af9c1..0000000000 --- a/target/linux/ar71xx/patches-4.9/920-usb-chipidea-AR933x-platform-support.patch +++ /dev/null @@ -1,124 +0,0 @@ ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -659,6 +659,7 @@ - - #define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) - #define AR933X_BOOTSTRAP_EEPBUSY BIT(4) -+#define AR933X_BOOTSTRAP_USB_MODE_HOST BIT(3) - #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) - - #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) -@@ -688,6 +689,8 @@ - - #define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2) - -+#define AR933X_USB_CONFIG_HOST_ONLY BIT(8) -+ - #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) - #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) - #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) ---- a/arch/mips/ath79/dev-usb.c -+++ b/arch/mips/ath79/dev-usb.c -@@ -19,6 +19,9 @@ - #include <linux/platform_device.h> - #include <linux/usb/ehci_pdriver.h> - #include <linux/usb/ohci_pdriver.h> -+#include <linux/usb/otg.h> -+#include <linux/usb/chipidea.h> -+#include <linux/usb/usb_phy_generic.h> - - #include <asm/mach-ath79/ath79.h> - #include <asm/mach-ath79/ar71xx_regs.h> -@@ -170,6 +173,44 @@ static void __init ar913x_usb_setup(void - &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); - } - -+static void __init ar9xxx_ci_usb_setup(int bus_id, int irq) -+{ -+ struct ci_hdrc_platform_data ci_pdata; -+ bool host_mode = true; -+ -+ if (soc_is_ar933x()) -+ host_mode = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP) & -+ AR933X_BOOTSTRAP_USB_MODE_HOST; -+ else -+ host_mode = !(ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP) & -+ AR934X_BOOTSTRAP_USB_MODE_DEVICE); -+ -+ if (host_mode) { -+ ath79_usb_register("ehci-platform", bus_id, -+ AR934X_EHCI_BASE, AR934X_EHCI_SIZE, -+ irq, &ath79_ehci_pdata_v2, -+ sizeof(ath79_ehci_pdata_v2)); -+ -+ return; -+ } -+ -+ memset(&ci_pdata, 0, sizeof(ci_pdata)); -+ ci_pdata.name = "ci_hdrc_ar9xxx"; -+ ci_pdata.capoffset = DEF_CAPOFFSET; -+ ci_pdata.dr_mode = USB_DR_MODE_PERIPHERAL; -+ ci_pdata.flags = CI_HDRC_DUAL_ROLE_NOT_OTG | CI_HDRC_DP_ALWAYS_PULLUP; -+ ci_pdata.vbus_extcon.edev = ERR_PTR(-ENODEV); -+ ci_pdata.id_extcon.edev = ERR_PTR(-ENODEV); -+ ci_pdata.itc_setting = 1; -+ -+ platform_device_register_simple("usb_phy_generic", -+ PLATFORM_DEVID_AUTO, NULL, 0); -+ -+ ath79_usb_register("ci_hdrc", -1, -+ AR934X_EHCI_BASE, AR934X_EHCI_SIZE, -+ irq, &ci_pdata, sizeof(ci_pdata)); -+} -+ - static void __init ar933x_usb_setup(void) - { - ath79_device_reset_set(AR933X_RESET_USBSUS_OVERRIDE); -@@ -181,10 +222,7 @@ static void __init ar933x_usb_setup(void - ath79_device_reset_clear(AR933X_RESET_USB_PHY); - mdelay(10); - -- ath79_usb_register("ehci-platform", -1, -- AR933X_EHCI_BASE, AR933X_EHCI_SIZE, -- ATH79_CPU_IRQ(3), -- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); -+ ar9xxx_ci_usb_setup(-1, ATH79_CPU_IRQ(3)); - } - - static void enable_tx_tx_idp_violation_fix(unsigned base) -@@ -230,10 +268,7 @@ static void __init ar934x_usb_setup(void - if (ath79_soc_rev >= 3) - ath79_ehci_pdata_v2.reset_notifier = ar934x_usb_reset_notifier; - -- ath79_usb_register("ehci-platform", -1, -- AR934X_EHCI_BASE, AR934X_EHCI_SIZE, -- ATH79_CPU_IRQ(3), -- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); -+ ar9xxx_ci_usb_setup(-1, ATH79_CPU_IRQ(3)); - } - - static void __init qca953x_usb_setup(void) -@@ -254,10 +289,7 @@ static void __init qca953x_usb_setup(voi - ath79_device_reset_clear(QCA953X_RESET_USB_HOST); - udelay(1000); - -- ath79_usb_register("ehci-platform", -1, -- QCA953X_EHCI_BASE, QCA953X_EHCI_SIZE, -- ATH79_CPU_IRQ(3), -- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); -+ ar9xxx_ci_usb_setup(-1, ATH79_CPU_IRQ(3)); - } - - static void qca955x_usb_reset_notifier(struct platform_device *pdev) -@@ -285,10 +317,7 @@ static void __init qca955x_usb_setup(voi - { - ath79_ehci_pdata_v2.reset_notifier = qca955x_usb_reset_notifier; - -- ath79_usb_register("ehci-platform", 0, -- QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE, -- ATH79_IP3_IRQ(0), -- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); -+ ar9xxx_ci_usb_setup(0, ATH79_IP3_IRQ(0)); - - ath79_usb_register("ehci-platform", 1, - QCA955X_EHCI1_BASE, QCA955X_EHCI_SIZE, diff --git a/target/linux/ar71xx/patches-4.9/921-MIPS-ath79-add-even-more-register-defines-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-4.9/921-MIPS-ath79-add-even-more-register-defines-for-QCA956x-SoC.patch deleted file mode 100644 index a4608ea48d..0000000000 --- a/target/linux/ar71xx/patches-4.9/921-MIPS-ath79-add-even-more-register-defines-for-QCA956x-SoC.patch +++ /dev/null @@ -1,194 +0,0 @@ -Add more registers for QCA955x and QCA956x. - ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -175,6 +175,35 @@ - /* - * Hidden Registers - */ -+#define QCA956X_MAC_CFG_BASE 0xb9000000 -+#define QCA956X_MAC_CFG_SIZE 0x64 -+ -+#define QCA956X_MAC_CFG1_REG 0x00 -+#define QCA956X_MAC_CFG1_SOFT_RST BIT(31) -+#define QCA956X_MAC_CFG1_RX_RST BIT(19) -+#define QCA956X_MAC_CFG1_TX_RST BIT(18) -+#define QCA956X_MAC_CFG1_LOOPBACK BIT(8) -+#define QCA956X_MAC_CFG1_RX_EN BIT(2) -+#define QCA956X_MAC_CFG1_TX_EN BIT(0) -+ -+#define QCA956X_MAC_CFG2_REG 0x04 -+#define QCA956X_MAC_CFG2_IF_1000 BIT(9) -+#define QCA956X_MAC_CFG2_IF_10_100 BIT(8) -+#define QCA956X_MAC_CFG2_HUGE_FRAME_EN BIT(5) -+#define QCA956X_MAC_CFG2_LEN_CHECK BIT(4) -+#define QCA956X_MAC_CFG2_PAD_CRC_EN BIT(2) -+#define QCA956X_MAC_CFG2_FDX BIT(0) -+ -+#define QCA956X_MAC_MII_MGMT_CFG_REG 0x20 -+#define QCA956X_MGMT_CFG_CLK_DIV_20 0x07 -+ -+#define QCA956X_MAC_FIFO_CFG0_REG 0x48 -+#define QCA956X_MAC_FIFO_CFG1_REG 0x4c -+#define QCA956X_MAC_FIFO_CFG2_REG 0x50 -+#define QCA956X_MAC_FIFO_CFG3_REG 0x54 -+#define QCA956X_MAC_FIFO_CFG4_REG 0x58 -+#define QCA956X_MAC_FIFO_CFG5_REG 0x5c -+ - #define QCA956X_DAM_RESET_OFFSET 0xb90001bc - #define QCA956X_DAM_RESET_SIZE 0x4 - #define QCA956X_INLINE_CHKSUM_ENG BIT(27) -@@ -384,6 +413,7 @@ - #define QCA955X_PLL_CLK_CTRL_REG 0x08 - #define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28 - #define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48 -+#define QCA955X_PLL_ETH_SGMII_SERDES_REG 0x4c - - #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 - #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f -@@ -416,12 +446,18 @@ - #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) - #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) - -+#define QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT BIT(2) -+#define QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK BIT(1) -+#define QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL BIT(0) -+ - #define QCA956X_PLL_CPU_CONFIG_REG 0x00 - #define QCA956X_PLL_CPU_CONFIG1_REG 0x04 - #define QCA956X_PLL_DDR_CONFIG_REG 0x08 - #define QCA956X_PLL_DDR_CONFIG1_REG 0x0c - #define QCA956X_PLL_CLK_CTRL_REG 0x10 -+#define QCA956X_PLL_SWITCH_CLOCK_CONTROL_REG 0x28 - #define QCA956X_PLL_ETH_XMII_CONTROL_REG 0x30 -+#define QCA956X_PLL_ETH_SGMII_SERDES_REG 0x4c - - #define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 - #define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f -@@ -460,6 +496,31 @@ - #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21) - #define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) - -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_I2C_CLK_SELB BIT(5) -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1 BIT(6) -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_UART1_CLK_SEL BIT(7) -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SHIFT 8 -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK 0xf -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_EN_PLL_TOP BIT(12) -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2 BIT(13) -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1 BIT(14) -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2 BIT(15) -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE BIT(16) -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_EEE_ENABLE BIT(17) -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL BIT(18) -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCHCLK_SEL BIT(19) -+ -+#define QCA956X_PLL_ETH_XMII_TX_INVERT BIT(1) -+#define QCA956X_PLL_ETH_XMII_GIGE BIT(25) -+#define QCA956X_PLL_ETH_XMII_RX_DELAY_SHIFT 28 -+#define QCA956X_PLL_ETH_XMII_RX_DELAY_MASK 0x3 -+#define QCA956X_PLL_ETH_XMII_TX_DELAY_SHIFT 26 -+#define QCA956X_PLL_ETH_XMII_TX_DELAY_MASK 3 -+ -+#define QCA956X_PLL_ETH_SGMII_SERDES_LOCK_DETECT BIT(2) -+#define QCA956X_PLL_ETH_SGMII_SERDES_PLL_REFCLK BIT(1) -+#define QCA956X_PLL_ETH_SGMII_SERDES_EN_PLL BIT(0) -+ - /* - * USB_CONFIG block - */ -@@ -657,6 +718,25 @@ - #define QCA955X_RESET_MBOX BIT(1) - #define QCA955X_RESET_I2S BIT(0) - -+#define QCA956X_RESET_EXTERNAL BIT(28) -+#define QCA956X_RESET_FULL_CHIP BIT(24) -+#define QCA956X_RESET_GE1_MDIO BIT(23) -+#define QCA956X_RESET_GE0_MDIO BIT(22) -+#define QCA956X_RESET_CPU_NMI BIT(21) -+#define QCA956X_RESET_CPU_COLD BIT(20) -+#define QCA956X_RESET_DMA BIT(19) -+#define QCA956X_RESET_DDR BIT(16) -+#define QCA956X_RESET_GE1_MAC BIT(13) -+#define QCA956X_RESET_SGMII_ANALOG BIT(12) -+#define QCA956X_RESET_USB_PHY_ANALOG BIT(11) -+#define QCA956X_RESET_GE0_MAC BIT(9) -+#define QCA956X_RESET_SGMII BIT(8) -+#define QCA956X_RESET_USB_HOST BIT(5) -+#define QCA956X_RESET_USB_PHY BIT(4) -+#define QCA956X_RESET_USBSUS_OVERRIDE BIT(3) -+#define QCA956X_RESET_SWITCH_ANALOG BIT(2) -+#define QCA956X_RESET_SWITCH BIT(0) -+ - #define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) - #define AR933X_BOOTSTRAP_EEPBUSY BIT(4) - #define AR933X_BOOTSTRAP_USB_MODE_HOST BIT(3) -@@ -1189,6 +1269,7 @@ - */ - - #define QCA955X_GMAC_REG_ETH_CFG 0x00 -+#define QCA955X_GMAC_REG_SGMII_SERDES 0x18 - - #define QCA955X_ETH_CFG_RGMII_EN BIT(0) - #define QCA955X_ETH_CFG_MII_GE0 BIT(1) -@@ -1210,16 +1291,58 @@ - #define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3 - #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20 - -+#define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15) -+#define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23 -+#define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf - /* - * QCA956X GMAC Interface - */ - --#define QCA956X_GMAC_REG_ETH_CFG 0x00 -+#define QCA956X_GMAC_REG_ETH_CFG 0x00 -+#define QCA956X_GMAC_REG_SGMII_RESET 0x14 -+#define QCA956X_GMAC_REG_SGMII_SERDES 0x18 -+#define QCA956X_GMAC_REG_MR_AN_CONTROL 0x1c -+#define QCA956X_GMAC_REG_SGMII_CONFIG 0x34 -+#define QCA956X_GMAC_REG_SGMII_DEBUG 0x58 - -+#define QCA956X_ETH_CFG_RGMII_EN BIT(0) -+#define QCA956X_ETH_CFG_GE0_SGMII BIT(6) - #define QCA956X_ETH_CFG_SW_ONLY_MODE BIT(7) --#define QCA956X_ETH_CFG_SW_PHY_SWAP BIT(8) -+#define QCA956X_ETH_CFG_SW_PHY_SWAP BIT(8) - #define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(9) - #define QCA956X_ETH_CFG_SW_APB_ACCESS BIT(10) - #define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) -+#define QCA956X_ETH_CFG_RXD_DELAY_MASK 0x3 -+#define QCA956X_ETH_CFG_RXD_DELAY_SHIFT 14 -+#define QCA956X_ETH_CFG_RDV_DELAY_MASK 0x3 -+#define QCA956X_ETH_CFG_RDV_DELAY_SHIFT 16 -+ -+#define QCA956X_SGMII_RESET_RX_CLK_N_RESET 0x0 -+#define QCA956X_SGMII_RESET_RX_CLK_N BIT(0) -+#define QCA956X_SGMII_RESET_TX_CLK_N BIT(1) -+#define QCA956X_SGMII_RESET_RX_125M_N BIT(2) -+#define QCA956X_SGMII_RESET_TX_125M_N BIT(3) -+#define QCA956X_SGMII_RESET_HW_RX_125M_N BIT(4) -+ -+#define QCA956X_SGMII_SERDES_CDR_BW_MASK 0x3 -+#define QCA956X_SGMII_SERDES_CDR_BW_SHIFT 1 -+#define QCA956X_SGMII_SERDES_TX_DR_CTRL_MASK 0x7 -+#define QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT 4 -+#define QCA956X_SGMII_SERDES_PLL_BW BIT(8) -+#define QCA956X_SGMII_SERDES_VCO_FAST BIT(9) -+#define QCA956X_SGMII_SERDES_VCO_SLOW BIT(10) -+#define QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15) -+#define QCA956X_SGMII_SERDES_EN_SIGNAL_DETECT BIT(16) -+#define QCA956X_SGMII_SERDES_FIBER_SDO BIT(17) -+#define QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23 -+#define QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf -+#define QCA956X_SGMII_SERDES_VCO_REG_SHIFT 27 -+#define QCA956X_SGMII_SERDES_VCO_REG_MASK 0xf -+ -+#define QCA956X_MR_AN_CONTROL_AN_ENABLE BIT(12) -+#define QCA956X_MR_AN_CONTROL_PHY_RESET BIT(15) -+ -+#define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT 0 -+#define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK 0x7 - - #endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/target/linux/ar71xx/patches-4.9/930-chipidea-pullup.patch b/target/linux/ar71xx/patches-4.9/930-chipidea-pullup.patch deleted file mode 100644 index 1c4ef3891c..0000000000 --- a/target/linux/ar71xx/patches-4.9/930-chipidea-pullup.patch +++ /dev/null @@ -1,72 +0,0 @@ ---- a/drivers/usb/chipidea/ci.h -+++ b/drivers/usb/chipidea/ci.h -@@ -199,6 +199,7 @@ struct hw_bank { - * @in_lpm: if the core in low power mode - * @wakeup_int: if wakeup interrupt occur - * @rev: The revision number for controller -+ * @dp_always_pullup: keep dp always pullup at device mode - */ - struct ci_hdrc { - struct device *dev; -@@ -248,6 +249,7 @@ struct ci_hdrc { - bool in_lpm; - bool wakeup_int; - enum ci_revision rev; -+ bool dp_always_pullup; - }; - - static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci) ---- a/drivers/usb/chipidea/core.c -+++ b/drivers/usb/chipidea/core.c -@@ -839,7 +839,7 @@ static inline void ci_role_destroy(struc - { - ci_hdrc_gadget_destroy(ci); - ci_hdrc_host_destroy(ci); -- if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) -+ if (!ci->dp_always_pullup && ci->roles[CI_ROLE_GADGET]) - ci_hdrc_otg_destroy(ci); - } - -@@ -890,6 +890,9 @@ static int ci_hdrc_probe(struct platform - ci->supports_runtime_pm = !!(ci->platdata->flags & - CI_HDRC_SUPPORTS_RUNTIME_PM); - -+ ci->dp_always_pullup = !!(ci->platdata->flags & -+ CI_HDRC_DP_ALWAYS_PULLUP); -+ - ret = hw_device_init(ci, base); - if (ret < 0) { - dev_err(dev, "can't initialize hardware\n"); -@@ -963,7 +966,7 @@ static int ci_hdrc_probe(struct platform - goto deinit_gadget; - } - -- if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) { -+ if (!ci->dp_always_pullup && ci->roles[CI_ROLE_GADGET]) { - ret = ci_hdrc_otg_init(ci); - if (ret) { - dev_err(dev, "init otg fails, ret = %d\n", ret); ---- a/drivers/usb/chipidea/otg.c -+++ b/drivers/usb/chipidea/otg.c -@@ -131,8 +131,10 @@ enum ci_role ci_otg_role(struct ci_hdrc - - void ci_handle_vbus_change(struct ci_hdrc *ci) - { -- if (!ci->is_otg) -+ if (ci->dp_always_pullup) { -+ usb_gadget_vbus_connect(&ci->gadget); - return; -+ } - - if (hw_read_otgsc(ci, OTGSC_BSV) && !ci->vbus_active) - usb_gadget_vbus_connect(&ci->gadget); ---- a/include/linux/usb/chipidea.h -+++ b/include/linux/usb/chipidea.h -@@ -57,6 +57,7 @@ struct ci_hdrc_platform_data { - #define CI_HDRC_OVERRIDE_AHB_BURST BIT(9) - #define CI_HDRC_OVERRIDE_TX_BURST BIT(10) - #define CI_HDRC_OVERRIDE_RX_BURST BIT(11) -+#define CI_HDRC_DP_ALWAYS_PULLUP BIT(12) - enum usb_dr_mode dr_mode; - #define CI_HDRC_CONTROLLER_RESET_EVENT 0 - #define CI_HDRC_CONTROLLER_STOPPED_EVENT 1 diff --git a/target/linux/ar71xx/patches-4.9/940-qca955x-add-more-registers.patch b/target/linux/ar71xx/patches-4.9/940-qca955x-add-more-registers.patch deleted file mode 100644 index ff72308465..0000000000 --- a/target/linux/ar71xx/patches-4.9/940-qca955x-add-more-registers.patch +++ /dev/null @@ -1,42 +0,0 @@ ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -134,7 +134,7 @@ - #define QCA955X_PCI_CTRL_SIZE 0x100 - - #define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) --#define QCA955X_GMAC_SIZE 0x40 -+#define QCA955X_GMAC_SIZE 0x64 - #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) - #define QCA955X_WMAC_SIZE 0x20000 - #define QCA955X_EHCI0_BASE 0x1b000000 -@@ -1269,7 +1269,11 @@ - */ - - #define QCA955X_GMAC_REG_ETH_CFG 0x00 -+#define QCA955X_GMAC_REG_SGMII_RESET 0x14 - #define QCA955X_GMAC_REG_SGMII_SERDES 0x18 -+#define QCA955X_GMAC_REG_MR_AN_CONTROL 0x1c -+#define QCA955X_GMAC_REG_MR_AN_STATUS 0x20 -+#define QCA955X_GMAC_REG_SGMII_DEBUG 0x58 - - #define QCA955X_ETH_CFG_RGMII_EN BIT(0) - #define QCA955X_ETH_CFG_MII_GE0 BIT(1) -@@ -1291,6 +1295,18 @@ - #define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3 - #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20 - -+#define QCA955X_SGMII_RESET_RX_CLK_N_RESET 0x0 -+#define QCA955X_SGMII_RESET_RX_CLK_N BIT(0) -+#define QCA955X_SGMII_RESET_TX_CLK_N BIT(1) -+#define QCA955X_SGMII_RESET_RX_125M_N BIT(2) -+#define QCA955X_SGMII_RESET_TX_125M_N BIT(3) -+#define QCA955X_SGMII_RESET_HW_RX_125M_N BIT(4) -+ -+#define QCA955X_MR_AN_CONTROL_PHY_RESET BIT(15) -+#define QCA955X_MR_AN_CONTROL_AN_ENABLE BIT(12) -+ -+#define QCA955X_MR_AN_STATUS_AN_ABILITY BIT(3) -+ - #define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15) - #define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23 - #define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf diff --git a/target/linux/ar71xx/patches-4.9/999-mdio_hack.patch b/target/linux/ar71xx/patches-4.9/999-mdio_hack.patch deleted file mode 100644 index 846c6a52a2..0000000000 --- a/target/linux/ar71xx/patches-4.9/999-mdio_hack.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- a/drivers/net/phy/mdio-boardinfo.c -+++ b/drivers/net/phy/mdio-boardinfo.c -@@ -49,6 +49,7 @@ mdiobus_register_board_info(struct mdio_ - - for (i = 0; i < n; i++, be++, info++) { - memcpy(&be->board_info, info, sizeof(*info)); -+ be->board_info.phy_addr = be->board_info.mdio_addr; - mutex_lock(&__mdio_board_lock); - list_add_tail(&be->list, &__mdio_board_list); - mutex_unlock(&__mdio_board_lock); ---- a/include/linux/phy.h -+++ b/include/linux/phy.h -@@ -872,6 +872,7 @@ extern struct bus_type mdio_bus_type; - - struct mdio_board_info { - const char *bus_id; -+ int mdio_addr; - int phy_addr; - - const void *platform_data; |