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| author | Gabor Juhos <juhosg@openwrt.org> | 2011-04-07 20:52:53 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2011-04-07 20:52:53 +0000 |
| commit | ccd3ebd30948dbd6f0e1278055cdd5bbb756c194 (patch) | |
| tree | 59ebce103e238808bd2f514611d7d11b269e36f5 /target | |
| parent | 91470edada63138ca56dc0b911e3827cfc348d81 (diff) | |
| download | upstream-ccd3ebd30948dbd6f0e1278055cdd5bbb756c194.tar.gz upstream-ccd3ebd30948dbd6f0e1278055cdd5bbb756c194.tar.bz2 upstream-ccd3ebd30948dbd6f0e1278055cdd5bbb756c194.zip | |
ar71xx: add AR934x specific UART clock initialization
Signed-off-by: Jaiganesh Narayanan <jnarayanan@atheros.com>
SVN-Revision: 26511
Diffstat (limited to 'target')
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/ar71xx/devices.c | 27 |
1 files changed, 25 insertions, 2 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c b/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c index 45300d7bfa..a3f4aaf7f5 100644 --- a/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c +++ b/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c @@ -1,10 +1,12 @@ /* * Atheros AR71xx SoC platform devices * + * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org> * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> * - * Parts of this file are based on Atheros' 2.6.15 BSP + * Parts of this file are based on Atheros 2.6.15 BSP + * Parts of this file are based on Atheros 2.6.31 BSP * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published @@ -57,7 +59,28 @@ static struct platform_device ar71xx_uart_device = { void __init ar71xx_add_device_uart(void) { - ar71xx_uart_data[0].uartclk = ar71xx_ahb_freq; + switch (ar71xx_soc) { + case AR71XX_SOC_AR7130: + case AR71XX_SOC_AR7141: + case AR71XX_SOC_AR7161: + case AR71XX_SOC_AR7240: + case AR71XX_SOC_AR7241: + case AR71XX_SOC_AR7242: + case AR71XX_SOC_AR9130: + case AR71XX_SOC_AR9132: + ar71xx_uart_data[0].uartclk = ar71xx_ahb_freq; + break; + + case AR71XX_SOC_AR9341: + case AR71XX_SOC_AR9342: + case AR71XX_SOC_AR9344: + ar71xx_uart_data[0].uartclk = ar934x_ref_freq; + break; + + default: + BUG(); + + } platform_device_register(&ar71xx_uart_device); } |