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authorGabor Juhos <juhosg@openwrt.org>2008-11-27 22:40:34 +0000
committerGabor Juhos <juhosg@openwrt.org>2008-11-27 22:40:34 +0000
commitf506e75eb0f13ffe757bd36580983648789710ff (patch)
treec155e1e5d89d3058d81eccb94473487df84d6694 /target
parentbd20af97c2c22211a48700f29fdcb2f647d84e3a (diff)
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ag71xx driver: add more register bit definitions
SVN-Revision: 13387
Diffstat (limited to 'target')
-rw-r--r--target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h14
1 files changed, 8 insertions, 6 deletions
diff --git a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
index d8851160f7..cbc6f75e4d 100644
--- a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
+++ b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
@@ -198,12 +198,14 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
#define AG71XX_REG_INT_ENABLE 0x0198
#define AG71XX_REG_INT_STATUS 0x019c
-#define MAC_CFG1_TXE BIT(0)
-#define MAC_CFG1_STX BIT(1)
-#define MAC_CFG1_RXE BIT(2)
-#define MAC_CFG1_SRX BIT(3)
-#define MAC_CFG1_LB BIT(8)
-#define MAC_CFG1_SR BIT(31)
+#define MAC_CFG1_TXE BIT(0) /* Tx Enable */
+#define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
+#define MAC_CFG1_RXE BIT(2) /* Rx Enable */
+#define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
+#define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
+#define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
+#define MAC_CFG1_LB BIT(8) /* Loopback mode */
+#define MAC_CFG1_SR BIT(31) /* Soft Reset */
#define MAC_CFG2_FDX BIT(0)
#define MAC_CFG2_CRC_EN BIT(1)