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| author | Gabor Juhos <juhosg@openwrt.org> | 2013-02-10 13:18:48 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2013-02-10 13:18:48 +0000 |
| commit | 393163b098d43ec8addb456e0c592b5fcea32f33 (patch) | |
| tree | dd64643032b20144e5d99f08a219325096f2226e /target | |
| parent | 5ed480598d26b56906af2a2cbc6e83582faa0df3 (diff) | |
| download | upstream-393163b098d43ec8addb456e0c592b5fcea32f33.tar.gz upstream-393163b098d43ec8addb456e0c592b5fcea32f33.tar.bz2 upstream-393163b098d43ec8addb456e0c592b5fcea32f33.zip | |
generic: ar8216: add defines for the AR8316 POSTRIP register
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 35539
Diffstat (limited to 'target')
| -rw-r--r-- | target/linux/generic/files/drivers/net/phy/ar8216.c | 4 | ||||
| -rw-r--r-- | target/linux/generic/files/drivers/net/phy/ar8216.h | 30 |
2 files changed, 32 insertions, 2 deletions
diff --git a/target/linux/generic/files/drivers/net/phy/ar8216.c b/target/linux/generic/files/drivers/net/phy/ar8216.c index ec6d232668..720b0eec34 100644 --- a/target/linux/generic/files/drivers/net/phy/ar8216.c +++ b/target/linux/generic/files/drivers/net/phy/ar8216.c @@ -788,7 +788,7 @@ ar8316_hw_init(struct ar8216_priv *priv) u32 val, newval; struct mii_bus *bus; - val = priv->read(priv, 0x8); + val = priv->read(priv, AR8316_REG_POSTRIP); if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) { if (priv->port4_phy) { @@ -812,7 +812,7 @@ ar8316_hw_init(struct ar8216_priv *priv) if (val == newval) goto out; - priv->write(priv, 0x8, newval); + priv->write(priv, AR8316_REG_POSTRIP, newval); /* Initialize the ports */ bus = priv->mii_bus; diff --git a/target/linux/generic/files/drivers/net/phy/ar8216.h b/target/linux/generic/files/drivers/net/phy/ar8216.h index c83bf44e18..95d9a96e75 100644 --- a/target/linux/generic/files/drivers/net/phy/ar8216.h +++ b/target/linux/generic/files/drivers/net/phy/ar8216.h @@ -255,6 +255,36 @@ #define AR8236_STATS_TXDEFER 0xa0 #define AR8236_STATS_TXLATECOL 0xa4 +#define AR8316_REG_POSTRIP 0x0008 +#define AR8316_POSTRIP_MAC0_GMII_EN BIT(0) +#define AR8316_POSTRIP_MAC0_RGMII_EN BIT(1) +#define AR8316_POSTRIP_PHY4_GMII_EN BIT(2) +#define AR8316_POSTRIP_PHY4_RGMII_EN BIT(3) +#define AR8316_POSTRIP_MAC0_MAC_MODE BIT(4) +#define AR8316_POSTRIP_RTL_MODE BIT(5) +#define AR8316_POSTRIP_RGMII_RXCLK_DELAY_EN BIT(6) +#define AR8316_POSTRIP_RGMII_TXCLK_DELAY_EN BIT(7) +#define AR8316_POSTRIP_SERDES_EN BIT(8) +#define AR8316_POSTRIP_SEL_ANA_RST BIT(9) +#define AR8316_POSTRIP_GATE_25M_EN BIT(10) +#define AR8316_POSTRIP_SEL_CLK25M BIT(11) +#define AR8316_POSTRIP_HIB_PULSE_HW BIT(12) +#define AR8316_POSTRIP_DBG_MODE_I BIT(13) +#define AR8316_POSTRIP_MAC5_MAC_MODE BIT(14) +#define AR8316_POSTRIP_MAC5_PHY_MODE BIT(15) +#define AR8316_POSTRIP_POWER_DOWN_HW BIT(16) +#define AR8316_POSTRIP_LPW_STATE_EN BIT(17) +#define AR8316_POSTRIP_MAN_EN BIT(18) +#define AR8316_POSTRIP_PHY_PLL_ON BIT(19) +#define AR8316_POSTRIP_LPW_EXIT BIT(20) +#define AR8316_POSTRIP_TXDELAY_S0 BIT(21) +#define AR8316_POSTRIP_TXDELAY_S1 BIT(22) +#define AR8316_POSTRIP_RXDELAY_S0 BIT(23) +#define AR8316_POSTRIP_LED_OPEN_EN BIT(24) +#define AR8316_POSTRIP_SPI_EN BIT(25) +#define AR8316_POSTRIP_RXDELAY_S1 BIT(26) +#define AR8316_POSTRIP_POWER_ON_SEL BIT(31) + #define AR8327_NUM_PORTS 7 #define AR8327_NUM_PHYS 5 #define AR8327_PORTS_ALL 0x7f |