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authorGabor Juhos <juhosg@openwrt.org>2012-12-22 12:12:50 +0000
committerGabor Juhos <juhosg@openwrt.org>2012-12-22 12:12:50 +0000
commit64d31e6c6b137e6b15b1fd3a2cc465fc7d4105af (patch)
treed45fbcd214f3d4911d3c8a01184c7fe0b78d3f80 /target
parent5dec87afefef15bd619d7586f1f5d241a695104d (diff)
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ar71xx: register the second ethernet interface on the AP136
Also fix the default network configuration according to the new setup. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 34854
Diffstat (limited to 'target')
-rwxr-xr-xtarget/linux/ar71xx/base-files/etc/uci-defaults/network7
-rw-r--r--target/linux/ar71xx/patches-3.6/609-MIPS-ath79-ap136-fixes.patch25
2 files changed, 27 insertions, 5 deletions
diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/network b/target/linux/ar71xx/base-files/etc/uci-defaults/network
index 7832da59b5..d6b60650c7 100755
--- a/target/linux/ar71xx/base-files/etc/uci-defaults/network
+++ b/target/linux/ar71xx/base-files/etc/uci-defaults/network
@@ -22,6 +22,13 @@ ubnt-unifi-outdoor)
ucidef_set_interface_lan "eth0 eth1"
;;
+ap136)
+ ucidef_set_interfaces_lan_wan "eth0" "eth1"
+ ucidef_add_switch "switch0" "1" "1"
+ ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 4"
+ ucidef_add_switch_vlan "switch0" "2" "5 6"
+ ;;
+
db120 |\
rb-2011l | \
rb-2011uas-2hnd)
diff --git a/target/linux/ar71xx/patches-3.6/609-MIPS-ath79-ap136-fixes.patch b/target/linux/ar71xx/patches-3.6/609-MIPS-ath79-ap136-fixes.patch
index 8325cdbb8f..58cd680ce4 100644
--- a/target/linux/ar71xx/patches-3.6/609-MIPS-ath79-ap136-fixes.patch
+++ b/target/linux/ar71xx/patches-3.6/609-MIPS-ath79-ap136-fixes.patch
@@ -56,7 +56,7 @@
static struct gpio_led ap136_leds_gpio[] __initdata = {
{
-@@ -98,63 +104,91 @@ static struct gpio_keys_button ap136_gpi
+@@ -98,63 +104,106 @@ static struct gpio_keys_button ap136_gpi
},
};
@@ -99,7 +99,14 @@
+ .duplex = 1,
+ .txpause = 1,
+ .rxpause = 1,
-+ }
++ },
++ .port6_cfg = {
++ .force_link = 1,
++ .speed = AR8327_PORT_SPEED_1000,
++ .duplex = 1,
++ .txpause = 1,
++ .rxpause = 1,
++ },
};
-#ifdef CONFIG_PCI
@@ -132,11 +139,11 @@
+
+ t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
+ t |= QCA955X_ETH_CFG_RGMII_EN;
++
++ __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
- ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
- ath79_register_pci();
-+ __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
-+
+ iounmap(base);
}
-#else
@@ -172,13 +179,21 @@
+ mdiobus_register_board_info(ap136_mdio0_info,
+ ARRAY_SIZE(ap136_mdio0_info));
+
-+ /* GMAC0 is connected to an AR8327 switch */
++ /* GMAC0 is connected to GMAC0 of the AR8327 switch via RGMII */
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth0_data.phy_mask = BIT(0);
+ ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
+ ath79_eth0_pll_data.pll_1000 = 0xa6000000;
+
+ ath79_register_eth(0);
++
++ /* GMAC1 is connected to GMAC6 of the AR8327 switch via SGMII */
++ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
++ ath79_eth1_data.speed = SPEED_1000;
++ ath79_eth1_data.duplex = DUPLEX_FULL;
++ ath79_eth1_pll_data.pll_1000 = 0x03000101;
++
++ ath79_register_eth(1);
}
MIPS_MACHINE(ATH79_MACH_AP136, "AP136", "Atheros AP136 reference board",