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| author | John Crispin <john@openwrt.org> | 2007-12-10 20:26:15 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2007-12-10 20:26:15 +0000 |
| commit | 6e2b3bc158ea27c8e8dd2aa717df138cba8c274a (patch) | |
| tree | 48d1f5851c3a528a3e4a06c64c75186bd051e446 /target | |
| parent | f02869b17a56881d47f255546f3a1b992e7f0a8a (diff) | |
| download | upstream-6e2b3bc158ea27c8e8dd2aa717df138cba8c274a.tar.gz upstream-6e2b3bc158ea27c8e8dd2aa717df138cba8c274a.tar.bz2 upstream-6e2b3bc158ea27c8e8dd2aa717df138cba8c274a.zip | |
added CONFIG_DANUBE_PCI_HW_SWAP
SVN-Revision: 9705
Diffstat (limited to 'target')
| -rw-r--r-- | target/linux/danube/files/arch/mips/danube/pci.c | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/target/linux/danube/files/arch/mips/danube/pci.c b/target/linux/danube/files/arch/mips/danube/pci.c index 3f7b7f8b87..1896336d81 100644 --- a/target/linux/danube/files/arch/mips/danube/pci.c +++ b/target/linux/danube/files/arch/mips/danube/pci.c @@ -77,15 +77,25 @@ danube_pci_config_access(unsigned char access_type, /* Perform access */ if (access_type == PCI_ACCESS_WRITE) { +#ifdef CONFIG_DANUBE_PCI_HW_SWAP + writel(swab32(*data), ((u32*)cfg_base)); +#else writel(*data, ((u32*)cfg_base)); +#endif } else { *data = readl(((u32*)(cfg_base))); +#ifdef CONFIG_DANUBE_PCI_HW_SWAP + *data = swab32(*data); +#endif } wmb(); /* clean possible Master abort */ cfg_base = (danube_pci_mapped_cfg | (0x0 << DANUBE_PCI_CFG_FUNNUM_SHF)) + 4; temp = readl(((u32*)(cfg_base))); +#ifdef CONFIG_DANUBE_PCI_HW_SWAP + temp = swab32 (temp); +#endif cfg_base = (danube_pci_mapped_cfg | (0x68 << DANUBE_PCI_CFG_FUNNUM_SHF)) + 4; writel(temp, ((u32*)cfg_base)); @@ -250,9 +260,14 @@ static void __init danube_pci_startup (void){ writel(0x0e000008, PCI_CR_BAR11MASK); writel(0, PCI_CR_PCI_ADDR_MAP11); writel(0, PCI_CS_BASE_ADDR1); +#ifdef CONFIG_DANUBE_PCI_HW_SWAP + /* both TX and RX endian swap are enabled */ + DANUBE_PCI_REG32 (PCI_CR_PCI_EOI_REG) |= 3; + wmb (); +#endif /*TODO: disable BAR2 & BAR3 - why was this in the origianl infineon code */ - // writel(readl(PCI_CR_BAR12MASK) | 0x80000000, PCI_CR_BAR12MASK); - // writel(readl(PCI_CR_BAR13MASK) | 0x80000000, PCI_CR_BAR13MASK); + writel(readl(PCI_CR_BAR12MASK) | 0x80000000, PCI_CR_BAR12MASK); + writel(readl(PCI_CR_BAR13MASK) | 0x80000000, PCI_CR_BAR13MASK); /*use 8 dw burse length */ writel(0x303, PCI_CR_FCI_BURST_LENGTH); |