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authorHauke Mehrtens <hauke@openwrt.org>2012-12-13 18:54:04 +0000
committerHauke Mehrtens <hauke@openwrt.org>2012-12-13 18:54:04 +0000
commit39d92a01356d4c6b11a9c94c4af3ada854a10f3a (patch)
treee0a9221177563db53958e401aca99f43641da9d2 /target
parentfc858e4562cdbaa9cffce20ac85327dead7fa026 (diff)
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brcm47xx: BCMA - Broadcom 2011 SDK Updates
I noticed these changes when reviewing the 2011 Broadcom SDK. I haven't noticed any obvious changes in behavior with them applied; but thought I should at least pass them on. Signed-off-by: Nathan Hintz <nlhintz@hotmail.com> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34670 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target')
-rw-r--r--target/linux/brcm47xx/patches-3.6/241-bcma-broadcom-2011-sdk-updates.patch50
1 files changed, 50 insertions, 0 deletions
diff --git a/target/linux/brcm47xx/patches-3.6/241-bcma-broadcom-2011-sdk-updates.patch b/target/linux/brcm47xx/patches-3.6/241-bcma-broadcom-2011-sdk-updates.patch
new file mode 100644
index 0000000000..ef356e2700
--- /dev/null
+++ b/target/linux/brcm47xx/patches-3.6/241-bcma-broadcom-2011-sdk-updates.patch
@@ -0,0 +1,50 @@
+--- a/drivers/bcma/core.c
++++ b/drivers/bcma/core.c
+@@ -43,6 +43,7 @@ int bcma_core_enable(struct bcma_device
+ bcma_aread32(core, BCMA_IOCTL);
+
+ bcma_awrite32(core, BCMA_RESET_CTL, 0);
++ bcma_aread32(core, BCMA_RESET_CTL);
+ udelay(1);
+
+ bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
+--- a/include/linux/bcma/bcma_driver_pci.h
++++ b/include/linux/bcma/bcma_driver_pci.h
+@@ -179,6 +179,8 @@ struct pci_dev;
+ #define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */
+ #define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */
+
++#define BCMA_CORE_PCI_CFG_DEVCTRL 0xd8
++
+ /* PCIE Root Capability Register bits (Host mode only) */
+ #define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
+
+--- a/drivers/bcma/driver_pci_host.c
++++ b/drivers/bcma/driver_pci_host.c
+@@ -430,7 +430,7 @@ void __devinit bcma_core_pci_hostmode_in
+ /* Reset RC */
+ usleep_range(3000, 5000);
+ pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
+- usleep_range(1000, 2000);
++ msleep(50);
+ pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
+ BCMA_CORE_PCI_CTL_RST_OE);
+
+@@ -492,6 +492,17 @@ void __devinit bcma_core_pci_hostmode_in
+
+ bcma_core_pci_enable_crs(pc);
+
++ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706 ||
++ bus->chipinfo.id == BCMA_CHIP_ID_BCM4716) {
++ u16 val16;
++ bcma_extpci_read_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
++ &val16, sizeof(val16));
++ val16 |= (2 << 5); /* Max payload size of 512 */
++ val16 |= (2 << 12); /* MRRS 512 */
++ bcma_extpci_write_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
++ &val16, sizeof(val16));
++ }
++
+ /* Enable PCI bridge BAR0 memory & master access */
+ tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));