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authorFelix Fietkau <nbd@openwrt.org>2015-04-20 15:00:41 +0000
committerFelix Fietkau <nbd@openwrt.org>2015-04-20 15:00:41 +0000
commitc75a0e86b13ec1cd35b0fa56cd5c222172a1407d (patch)
tree06877df41e2c97d1141520094b4464dfaf8383b1 /target
parent5c6925a23b84430782ab84eac75ade065c6adbb3 (diff)
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ar71xx: add mask and shift for RXD/RDV bits in AR934X register file
The commit r38948 ("ag71xx: add F1E specific feature bit definitions to AR934X register file") introduced definitions for some bits in the RDV/RXD part of the ETH_CFG register of AR934x. These are incomplete because ETH_RXDV_DELAY is specified as 17:16 and ETH_RXD_DELAY is specified 15:14. The original commit only specified the lower bits. The upper bits also have to be unset when the lower bits should only be set. Signed-off-by: Sven Eckelmann <sven@open-mesh.com> SVN-Revision: 45522
Diffstat (limited to 'target')
-rw-r--r--target/linux/ar71xx/patches-3.18/601-MIPS-ath79-add-more-register-defines.patch6
1 files changed, 5 insertions, 1 deletions
diff --git a/target/linux/ar71xx/patches-3.18/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.18/601-MIPS-ath79-add-more-register-defines.patch
index 2dec0209d7..8bf7658314 100644
--- a/target/linux/ar71xx/patches-3.18/601-MIPS-ath79-add-more-register-defines.patch
+++ b/target/linux/ar71xx/patches-3.18/601-MIPS-ath79-add-more-register-defines.patch
@@ -207,7 +207,7 @@
#define AR934X_GPIO_REG_FUNC 0x6c
#define AR71XX_GPIO_COUNT 16
-@@ -560,4 +663,149 @@
+@@ -560,4 +663,153 @@
#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
@@ -345,7 +345,11 @@
+#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
+#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
+#define AR934X_ETH_CFG_RXD_DELAY BIT(14)
++#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3
++#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14
+#define AR934X_ETH_CFG_RDV_DELAY BIT(16)
++#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3
++#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
+
+/*
+ * QCA955X GMAC Interface