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authorFelix Fietkau <nbd@nbd.name>2018-02-27 15:09:43 +0100
committerFelix Fietkau <nbd@nbd.name>2018-02-27 17:30:33 +0100
commitd8655868ca04d12ad5ed36e26fc63d61b076e33d (patch)
tree467f37f82c37cf5e1d8dfa7a723274d755fe953e /target
parent86e5a6d985e1666e685b1cacb204039ddf03f4cb (diff)
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ramips: fix spurious IRQ7 events when using perf on 4.14
Upstream handling of MIPS CPU IRQs is rather hackish and the interrupts are being enabled unconditionally in various places because of legacy code. Performance counter events are routed both through the GIC and through legacy CPU IRQ7 events, causing spurious interrupts. Fix this by disabling IRQ7 when trying to access the performance counter IRQ. Signed-off-by: Felix Fietkau <nbd@nbd.name>
Diffstat (limited to 'target')
-rw-r--r--target/linux/ramips/patches-4.14/110-mt7621-perfctr-fix.patch15
1 files changed, 15 insertions, 0 deletions
diff --git a/target/linux/ramips/patches-4.14/110-mt7621-perfctr-fix.patch b/target/linux/ramips/patches-4.14/110-mt7621-perfctr-fix.patch
new file mode 100644
index 0000000000..4c40e65ab9
--- /dev/null
+++ b/target/linux/ramips/patches-4.14/110-mt7621-perfctr-fix.patch
@@ -0,0 +1,15 @@
+--- a/arch/mips/ralink/irq-gic.c
++++ b/arch/mips/ralink/irq-gic.c
+@@ -15,6 +15,12 @@
+
+ int get_c0_perfcount_int(void)
+ {
++ /*
++ * Performance counter events are routed through GIC.
++ * Prevent them from firing on CPU IRQ7 as well
++ */
++ clear_c0_status(IE_SW0 << 7);
++
+ return gic_get_c0_perfcount_int();
+ }
+ EXPORT_SYMBOL_GPL(get_c0_perfcount_int);