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authorGabor Juhos <juhosg@openwrt.org>2010-01-27 21:01:48 +0000
committerGabor Juhos <juhosg@openwrt.org>2010-01-27 21:01:48 +0000
commit6bfdc7c99874d8f0ec72c4cd84ef9179e4c939bf (patch)
treeb9a8949c75551b53331783d219a094fe1fd299c2 /target
parent4e7fded1c43fd7396e9c442eaf30454fd2bc736c (diff)
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rtl8366s: reset the chip early, this allows ethernet to work as soon as possible
SVN-Revision: 19355
Diffstat (limited to 'target')
-rw-r--r--target/linux/generic-2.6/files/drivers/net/phy/rtl8366s.c54
1 files changed, 34 insertions, 20 deletions
diff --git a/target/linux/generic-2.6/files/drivers/net/phy/rtl8366s.c b/target/linux/generic-2.6/files/drivers/net/phy/rtl8366s.c
index 833e455dd0..babeddc44a 100644
--- a/target/linux/generic-2.6/files/drivers/net/phy/rtl8366s.c
+++ b/target/linux/generic-2.6/files/drivers/net/phy/rtl8366s.c
@@ -26,7 +26,7 @@
#endif
#define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver"
-#define RTL8366S_DRIVER_VER "0.2.0"
+#define RTL8366S_DRIVER_VER "0.2.1"
#define RTL8366S_PHY_NO_MAX 4
#define RTL8366S_PHY_PAGE_MAX 7
@@ -230,6 +230,31 @@ static inline struct rtl8366s *sw_to_rtl8366s(struct switch_dev *sw)
return container_of(sw, struct rtl8366s, dev);
}
+static int rtl8366s_reset_chip(struct rtl8366s *rtl)
+{
+ struct rtl8366_smi *smi = &rtl->smi;
+ int timeout = 10;
+ u32 data;
+
+ rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
+ RTL8366_CHIP_CTRL_RESET_HW);
+ do {
+ msleep(1);
+ if (rtl8366_smi_read_reg(smi, RTL8366_RESET_CTRL_REG, &data))
+ return -EIO;
+
+ if (!(data & RTL8366_CHIP_CTRL_RESET_HW))
+ break;
+ } while (--timeout);
+
+ if (!timeout) {
+ printk("Timeout waiting for the switch to reset\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+
static int rtl8366s_read_phy_reg(struct rtl8366s *rtl,
u32 phy_no, u32 page, u32 addr, u32 *data)
{
@@ -1301,25 +1326,11 @@ static int rtl8366s_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
static int rtl8366s_sw_reset_switch(struct switch_dev *dev)
{
struct rtl8366s *rtl = sw_to_rtl8366s(dev);
- struct rtl8366_smi *smi = &rtl->smi;
- int timeout = 10;
- u32 data;
-
- rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
- RTL8366_CHIP_CTRL_RESET_HW);
- do {
- msleep(1);
- if (rtl8366_smi_read_reg(smi, RTL8366_RESET_CTRL_REG, &data))
- return -EIO;
-
- if (!(data & RTL8366_CHIP_CTRL_RESET_HW))
- break;
- } while (--timeout);
+ int err;
- if (!timeout) {
- printk("Timeout waiting for the switch to reset\n");
- return -EIO;
- }
+ err = rtl8366s_reset_chip(rtl);
+ if (err)
+ return err;
return rtl8366s_reset_vlan(rtl);
}
@@ -1553,8 +1564,11 @@ static int rtl8366s_setup(struct rtl8366s *rtl)
dev_info(rtl->parent, "RTL%04x ver. %u chip found\n",
chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
- rtl8366s_debugfs_init(rtl);
+ ret = rtl8366s_reset_chip(rtl);
+ if (ret)
+ return ret;
+ rtl8366s_debugfs_init(rtl);
return 0;
}