aboutsummaryrefslogtreecommitdiffstats
path: root/target
diff options
context:
space:
mode:
authorImre Kaloz <kaloz@openwrt.org>2012-12-23 18:53:38 +0000
committerImre Kaloz <kaloz@openwrt.org>2012-12-23 18:53:38 +0000
commit2c05915b2406c3f5a0acca92789cd307edfcd145 (patch)
treea5278a630c0a33e57c3f026a99a5997c503abfc8 /target
parent970adc9eb9b1bf93c9e34ab6533f6e16f8d29967 (diff)
downloadupstream-2c05915b2406c3f5a0acca92789cd307edfcd145.tar.gz
upstream-2c05915b2406c3f5a0acca92789cd307edfcd145.tar.bz2
upstream-2c05915b2406c3f5a0acca92789cd307edfcd145.zip
add nol2x0 cmdline to disable l2x0 cache
L2 cache via L2X0 cache controller available on some ARM boards can provide a performance boost in some situations but decrease performance in others. This adds a kernel cmdline to disable L2X0 for cns3xxx based boards. Signed-off-by: Tim Harvey <tharvey@gateworks.com> SVN-Revision: 34874
Diffstat (limited to 'target')
-rw-r--r--target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/laguna.c2
-rw-r--r--target/linux/cns3xxx/patches-3.3/097-l2x0_cmdline_disable.patch47
2 files changed, 47 insertions, 2 deletions
diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/laguna.c b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/laguna.c
index 19bc2ededb..84a440bf18 100644
--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/laguna.c
+++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/laguna.c
@@ -710,8 +710,6 @@ static struct gpio laguna_gpio_gw2380[] = {
*/
static void __init laguna_init(void)
{
- cns3xxx_l2x0_init();
-
platform_device_register(&laguna_watchdog);
platform_device_register(&laguna_i2c_controller);
diff --git a/target/linux/cns3xxx/patches-3.3/097-l2x0_cmdline_disable.patch b/target/linux/cns3xxx/patches-3.3/097-l2x0_cmdline_disable.patch
new file mode 100644
index 0000000000..87b1090166
--- /dev/null
+++ b/target/linux/cns3xxx/patches-3.3/097-l2x0_cmdline_disable.patch
@@ -0,0 +1,47 @@
+--- a/arch/arm/mach-cns3xxx/core.c
++++ b/arch/arm/mach-cns3xxx/core.c
+@@ -284,11 +284,24 @@ struct sys_timer cns3xxx_timer = {
+
+ #ifdef CONFIG_CACHE_L2X0
+
++static int cns3xxx_l2x0_enable = 1;
++
++static int __init cns3xxx_l2x0_disable(char *s)
++{
++ cns3xxx_l2x0_enable = 0;
++ return 1;
++}
++__setup("nol2x0", cns3xxx_l2x0_disable);
++
+ void __init cns3xxx_l2x0_init(void)
+ {
+- void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
++ void __iomem *base;
+ u32 val;
+
++ if (!cns3xxx_l2x0_enable)
++ return;
++
++ base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
+ if (WARN_ON(!base))
+ return;
+
+@@ -321,6 +334,7 @@ void __init cns3xxx_l2x0_init(void)
+ /* 32 KiB, 8-way, parity disable */
+ l2x0_init(base, 0x00540000, 0xfe000fff);
+ }
++arch_initcall(cns3xxx_l2x0_init);
+
+ #endif /* CONFIG_CACHE_L2X0 */
+
+--- a/arch/arm/mach-cns3xxx/cns3420vb.c
++++ b/arch/arm/mach-cns3xxx/cns3420vb.c
+@@ -193,8 +193,6 @@ static struct platform_device *cns3420_p
+
+ static void __init cns3420_init(void)
+ {
+- cns3xxx_l2x0_init();
+-
+ platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
+
+ cns3xxx_ahci_init();