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authorChuanhong Guo <gch981213@gmail.com>2018-08-12 21:13:31 +0800
committerMathias Kresin <dev@kresin.me>2018-08-13 08:37:19 +0200
commitcf50f720695eb2d9d232a588b5a7f4959ef3fcee (patch)
tree8f7a0efe94226da9beb1f30cd2532679636ae156 /target
parent42b3fdf9812f799c07bd30899a2bb2cff7d1a200 (diff)
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ath79: ar913x: fix eth pll register
PLL for eth0 internal clock on ar913x is at 0x18050014 and AR913X_ETH0_PLL_SHIFT is 20 instead of 17 Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Diffstat (limited to 'target')
-rw-r--r--target/linux/ath79/dts/ar9132.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/linux/ath79/dts/ar9132.dtsi b/target/linux/ath79/dts/ar9132.dtsi
index 01572c022e..9d8ddcf9ba 100644
--- a/target/linux/ath79/dts/ar9132.dtsi
+++ b/target/linux/ath79/dts/ar9132.dtsi
@@ -189,7 +189,7 @@
reg = <0x19000000 0x200
0x18070000 0x4>;
pll-data = <0x1a000000 0x13000a44 0x00441099>;
- pll-reg = <0x4 0x10 17>;
+ pll-reg = <0x4 0x14 20>;
pll-handle = <&pll>;
resets = <&rst 9>;
reset-names = "mac";