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authorSven Eckelmann <sven.eckelmann@open-mesh.com>2016-05-19 20:20:59 +0200
committerSven Eckelmann <sven@narfation.org>2016-09-21 18:16:54 +0200
commitf8d1f1c678be771589b54e5bb74fa703c6153813 (patch)
treef023ec989372ac50e7b05242b5ea78f04594abc1 /target
parentb92fcfb75eb3c1632f403ec2f0b6e2c5831779f0 (diff)
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ar71xx: Use private version of ath79_setup_qca955x_eth_cfg for MR900
The MR900 must unset some bits in ETH_CFG which were set by u-boot to work correctly under OpenWrt. But the global function ath79_setup_qca955x_eth_cfg will not unset all of them to increase the backward compatiblity with older mach-* files. A private (simplified) version for MR900 can be used instead. Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com> Backport of r49069
Diffstat (limited to 'target')
-rw-r--r--target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c24
1 files changed, 23 insertions, 1 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c
index 3634bf0576..b439f58892 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c
@@ -110,6 +110,28 @@ static struct mdio_board_info mr900_mdio0_info[] = {
},
};
+static void __init mr900_setup_qca955x_eth_cfg(u32 mask,
+ unsigned int rxd,
+ unsigned int rxdv,
+ unsigned int txd,
+ unsigned int txe)
+{
+ void __iomem *base;
+ u32 t;
+
+ base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
+
+ t = mask;
+ t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT;
+ t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT;
+ t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT;
+ t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT;
+
+ __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
+
+ iounmap(base);
+}
+
static void __init mr900_setup(void)
{
u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
@@ -139,7 +161,7 @@ static void __init mr900_setup(void)
}
pdata->use_eeprom = true;
- ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+ mr900_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_register_mdio(0, 0x0);
mdiobus_register_board_info(mr900_mdio0_info,