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authorJohn Crispin <blogic@openwrt.org>2014-11-06 11:11:44 +0000
committerJohn Crispin <blogic@openwrt.org>2014-11-06 11:11:44 +0000
commit7996c754bda748cd3921a08405fe41d4dab7a6f4 (patch)
tree835be2c22f8b9c782ee09b94cd170809a765fe83 /target
parent2fca043064596359127dad73eefb19f4fa01c4b6 (diff)
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ralink: only apply ephy1 fixup if the phy is present
this broke e1700 lan2 as the fixup was applied to the phy inside the mt7530. Signed-off-by: John Crispin <blogic@openwrt.org> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@43200 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target')
-rw-r--r--target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620a.c75
1 files changed, 40 insertions, 35 deletions
diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620a.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620a.c
index 4bba8cc838..0f9fc35fe3 100644
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620a.c
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620a.c
@@ -72,6 +72,8 @@
#define GSW_REG_IMR 0x7008
#define GSW_REG_ISR 0x700c
+#define GSW_REG_GPC1 0x7014
+#define GSW_PHY1_DISABLE BIT(25)
#define SYSC_REG_CFG1 0x14
@@ -414,43 +416,46 @@ static void gsw_hw_init(struct mt7620_gsw *gsw)
rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
gsw_w32(gsw, gsw_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
- /*correct PHY setting L3.0 BGA*/
- _mt7620_mii_write(gsw, 1, 31, 0x4000); //global, page 4
+ /* EPHY1 fixup - only run if the ephy is enabled */
+ if (gsw_r32(gsw, GSW_REG_GPC1) & GSW_PHY1_DISABLE == GSW_PHY1_DISABLE) {
+ /*correct PHY setting L3.0 BGA*/
+ _mt7620_mii_write(gsw, 1, 31, 0x4000); //global, page 4
- _mt7620_mii_write(gsw, 1, 17, 0x7444);
- if (is_BGA)
- _mt7620_mii_write(gsw, 1, 19, 0x0114);
- else
- _mt7620_mii_write(gsw, 1, 19, 0x0117);
-
- _mt7620_mii_write(gsw, 1, 22, 0x10cf);
- _mt7620_mii_write(gsw, 1, 25, 0x6212);
- _mt7620_mii_write(gsw, 1, 26, 0x0777);
- _mt7620_mii_write(gsw, 1, 29, 0x4000);
- _mt7620_mii_write(gsw, 1, 28, 0xc077);
- _mt7620_mii_write(gsw, 1, 24, 0x0000);
-
- _mt7620_mii_write(gsw, 1, 31, 0x3000); //global, page 3
- _mt7620_mii_write(gsw, 1, 17, 0x4838);
-
- _mt7620_mii_write(gsw, 1, 31, 0x2000); //global, page 2
- if (is_BGA) {
- _mt7620_mii_write(gsw, 1, 21, 0x0515);
- _mt7620_mii_write(gsw, 1, 22, 0x0053);
- _mt7620_mii_write(gsw, 1, 23, 0x00bf);
- _mt7620_mii_write(gsw, 1, 24, 0x0aaf);
- _mt7620_mii_write(gsw, 1, 25, 0x0fad);
- _mt7620_mii_write(gsw, 1, 26, 0x0fc1);
- } else {
- _mt7620_mii_write(gsw, 1, 21, 0x0517);
- _mt7620_mii_write(gsw, 1, 22, 0x0fd2);
- _mt7620_mii_write(gsw, 1, 23, 0x00bf);
- _mt7620_mii_write(gsw, 1, 24, 0x0aab);
- _mt7620_mii_write(gsw, 1, 25, 0x00ae);
- _mt7620_mii_write(gsw, 1, 26, 0x0fff);
+ _mt7620_mii_write(gsw, 1, 17, 0x7444);
+ if (is_BGA)
+ _mt7620_mii_write(gsw, 1, 19, 0x0114);
+ else
+ _mt7620_mii_write(gsw, 1, 19, 0x0117);
+
+ _mt7620_mii_write(gsw, 1, 22, 0x10cf);
+ _mt7620_mii_write(gsw, 1, 25, 0x6212);
+ _mt7620_mii_write(gsw, 1, 26, 0x0777);
+ _mt7620_mii_write(gsw, 1, 29, 0x4000);
+ _mt7620_mii_write(gsw, 1, 28, 0xc077);
+ _mt7620_mii_write(gsw, 1, 24, 0x0000);
+
+ _mt7620_mii_write(gsw, 1, 31, 0x3000); //global, page 3
+ _mt7620_mii_write(gsw, 1, 17, 0x4838);
+
+ _mt7620_mii_write(gsw, 1, 31, 0x2000); //global, page 2
+ if (is_BGA) {
+ _mt7620_mii_write(gsw, 1, 21, 0x0515);
+ _mt7620_mii_write(gsw, 1, 22, 0x0053);
+ _mt7620_mii_write(gsw, 1, 23, 0x00bf);
+ _mt7620_mii_write(gsw, 1, 24, 0x0aaf);
+ _mt7620_mii_write(gsw, 1, 25, 0x0fad);
+ _mt7620_mii_write(gsw, 1, 26, 0x0fc1);
+ } else {
+ _mt7620_mii_write(gsw, 1, 21, 0x0517);
+ _mt7620_mii_write(gsw, 1, 22, 0x0fd2);
+ _mt7620_mii_write(gsw, 1, 23, 0x00bf);
+ _mt7620_mii_write(gsw, 1, 24, 0x0aab);
+ _mt7620_mii_write(gsw, 1, 25, 0x00ae);
+ _mt7620_mii_write(gsw, 1, 26, 0x0fff);
+ }
+ _mt7620_mii_write(gsw, 1, 31, 0x1000); //global, page 1
+ _mt7620_mii_write(gsw, 1, 17, 0xe7f8);
}
- _mt7620_mii_write(gsw, 1, 31, 0x1000); //global, page 1
- _mt7620_mii_write(gsw, 1, 17, 0xe7f8);
_mt7620_mii_write(gsw, 1, 31, 0x8000); //local, page 0
_mt7620_mii_write(gsw, 0, 30, 0xa000);