kernel: bring ssb in sync with upstream (as of current wireless-testing)

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@21269 3c298f89-4303-0410-b956-a3cf2f4a3e73

18 files changed, 3478 insertions, 288 deletions

diff --git a/target/linux/brcm47xx/patches-2.6.32/150-cpu_fixes.patch b/target/linux/brcm47xx/patches-2.6.32/150-cpu_fixes.patch
index 9e33093070..e6ac4c8e8a 100644
--- a/target/linux/brcm47xx/patches-2.6.32/150-cpu_fixes.patch
+++ b/target/linux/brcm47xx/patches-2.6.32/150-cpu_fixes.patch
@@ -345,7 +345,7 @@
  }
 --- a/arch/mips/mm/tlbex.c
 +++ b/arch/mips/mm/tlbex.c
-@@ -739,6 +739,9 @@ static void __cpuinit build_r4000_tlb_re
+@@ -733,6 +733,9 @@ static void __cpuinit build_r4000_tlb_re
  		/* No need for uasm_i_nop */
  	}
  
@@ -355,7 +355,7 @@
  #ifdef CONFIG_64BIT
  	build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
  #else
-@@ -1193,6 +1196,9 @@ build_r4000_tlbchange_handler_head(u32 *
+@@ -1185,6 +1188,9 @@ build_r4000_tlbchange_handler_head(u32 *
  				   struct uasm_reloc **r, unsigned int pte,
  				   unsigned int ptr)
  {
diff --git a/target/linux/brcm47xx/patches-2.6.32/180-ssb_extif_interrupt.patch b/target/linux/brcm47xx/patches-2.6.32/180-ssb_extif_interrupt.patch
deleted file mode 100644
index d89531cda1..0000000000
--- a/target/linux/brcm47xx/patches-2.6.32/180-ssb_extif_interrupt.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 83e34f03ee9b86b49bde4707a1fe03a1837e29be Mon Sep 17 00:00:00 2001
-From: Jochen Friedrich <jochen@scram.de>
-Date: Wed, 3 Feb 2010 21:28:11 +0100
-Subject: [PATCH 1/1] ssb: fix interrupt assignment
-
-Explicitely enable shared interrupt 2 for any core that didn't get a dedicated IRQ
-anymore (fallthrough case) and for EXTIF cores to make gpio interrupts work.
-Also remove a bogus comment.
-
-Signed-off-by: Jochen Friedrich <jochen@scram.de>
-Signed-off-by: John W. Linville <linville@tuxdriver.com>
----
- drivers/ssb/driver_mipscore.c |    5 ++++-
- 1 files changed, 4 insertions(+), 1 deletions(-)
-
---- a/drivers/ssb/driver_mipscore.c
-+++ b/drivers/ssb/driver_mipscore.c
-@@ -270,7 +270,6 @@ void ssb_mipscore_init(struct ssb_mipsco
- 				set_irq(dev, irq++);
- 			}
- 			break;
--			/* fallthrough */
- 		case SSB_DEV_PCI:
- 		case SSB_DEV_ETHERNET:
- 		case SSB_DEV_ETHERNET_GBIT:
-@@ -281,6 +280,10 @@ void ssb_mipscore_init(struct ssb_mipsco
- 				set_irq(dev, irq++);
- 				break;
- 			}
-+			/* fallthrough */
-+		case SSB_DEV_EXTIF:
-+			set_irq(dev, 0);
-+			break;
- 		}
- 	}
- 	ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
diff --git a/target/linux/brcm47xx/patches-2.6.32/220-bcm5354.patch b/target/linux/brcm47xx/patches-2.6.32/220-bcm5354.patch
index 360751a7ad..1d75e171d3 100644
--- a/target/linux/brcm47xx/patches-2.6.32/220-bcm5354.patch
+++ b/target/linux/brcm47xx/patches-2.6.32/220-bcm5354.patch
@@ -1,6 +1,6 @@
 --- a/drivers/ssb/driver_chipcommon.c
 +++ b/drivers/ssb/driver_chipcommon.c
-@@ -258,6 +258,8 @@ void ssb_chipco_resume(struct ssb_chipco
+@@ -260,6 +260,8 @@ void ssb_chipco_resume(struct ssb_chipco
  void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
                               u32 *plltype, u32 *n, u32 *m)
  {
@@ -9,7 +9,7 @@
  	*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
  	*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
  	switch (*plltype) {
-@@ -281,6 +283,8 @@ void ssb_chipco_get_clockcpu(struct ssb_
+@@ -283,6 +285,8 @@ void ssb_chipco_get_clockcpu(struct ssb_
  void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
  				 u32 *plltype, u32 *n, u32 *m)
  {
@@ -31,7 +31,7 @@
  	}
 --- a/drivers/ssb/main.c
 +++ b/drivers/ssb/main.c
-@@ -1066,6 +1066,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
+@@ -1073,6 +1073,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
  
  	if (bus->chip_id == 0x5365) {
  		rate = 100000000;
diff --git a/target/linux/brcm47xx/patches-2.6.32/700-ssb-gigabit-ethernet-driver.patch b/target/linux/brcm47xx/patches-2.6.32/700-ssb-gigabit-ethernet-driver.patch
index de25019506..dce689f199 100644
--- a/target/linux/brcm47xx/patches-2.6.32/700-ssb-gigabit-ethernet-driver.patch
+++ b/target/linux/brcm47xx/patches-2.6.32/700-ssb-gigabit-ethernet-driver.patch
@@ -102,7 +102,7 @@
  		tg3_readphy(tp, MII_BMSR, &tmp);
  		if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
  		    (tmp & BMSR_LSTATUS))
-@@ -6264,6 +6289,11 @@ static int tg3_poll_fw(struct tg3 *tp)
+@@ -6273,6 +6298,11 @@ static int tg3_poll_fw(struct tg3 *tp)
  	int i;
  	u32 val;
  
@@ -114,7 +114,7 @@
  	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  		/* Wait up to 20ms for init done. */
  		for (i = 0; i < 200; i++) {
-@@ -6541,6 +6571,14 @@ static int tg3_chip_reset(struct tg3 *tp
+@@ -6550,6 +6580,14 @@ static int tg3_chip_reset(struct tg3 *tp
  		tw32(0x5000, 0x400);
  	}
  
@@ -129,7 +129,7 @@
  	tw32(GRC_MODE, tp->grc_mode);
  
  	if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
-@@ -6695,9 +6733,12 @@ static int tg3_halt_cpu(struct tg3 *tp, 
+@@ -6704,9 +6742,12 @@ static int tg3_halt_cpu(struct tg3 *tp, 
  		return -ENODEV;
  	}
  
@@ -145,7 +145,7 @@
  	return 0;
  }
  
-@@ -6760,6 +6801,11 @@ static int tg3_load_5701_a0_firmware_fix
+@@ -6769,6 +6810,11 @@ static int tg3_load_5701_a0_firmware_fix
  	const __be32 *fw_data;
  	int err, i;
  
@@ -157,7 +157,7 @@
  	fw_data = (void *)tp->fw->data;
  
  	/* Firmware blob starts with version numbers, followed by
-@@ -6819,6 +6865,11 @@ static int tg3_load_tso_firmware(struct 
+@@ -6828,6 +6874,11 @@ static int tg3_load_tso_firmware(struct 
  	unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
  	int err, i;
  
@@ -169,7 +169,7 @@
  	if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
  		return 0;
  
-@@ -7906,6 +7957,11 @@ static void tg3_timer(unsigned long __op
+@@ -7915,6 +7966,11 @@ static void tg3_timer(unsigned long __op
  
  	spin_lock(&tp->lock);
  
@@ -181,7 +181,7 @@
  	if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
  		/* All of this garbage is because when using non-tagged
  		 * IRQ status the mailbox/status_block protocol the chip
-@@ -9791,6 +9847,11 @@ static int tg3_test_nvram(struct tg3 *tp
+@@ -9800,6 +9856,11 @@ static int tg3_test_nvram(struct tg3 *tp
  	if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
  		return 0;
  
@@ -193,7 +193,7 @@
  	if (tg3_nvram_read(tp, 0, &magic) != 0)
  		return -EIO;
  
-@@ -10585,7 +10646,7 @@ static int tg3_ioctl(struct net_device *
+@@ -10594,7 +10655,7 @@ static int tg3_ioctl(struct net_device *
  			return -EAGAIN;
  
  		spin_lock_bh(&tp->lock);
@@ -202,7 +202,7 @@
  		spin_unlock_bh(&tp->lock);
  
  		data->val_out = mii_regval;
-@@ -10601,7 +10662,7 @@ static int tg3_ioctl(struct net_device *
+@@ -10610,7 +10671,7 @@ static int tg3_ioctl(struct net_device *
  			return -EAGAIN;
  
  		spin_lock_bh(&tp->lock);
@@ -211,7 +211,7 @@
  		spin_unlock_bh(&tp->lock);
  
  		return err;
-@@ -11246,6 +11307,12 @@ static void __devinit tg3_get_5717_nvram
+@@ -11255,6 +11316,12 @@ static void __devinit tg3_get_5717_nvram
  /* Chips other than 5700/5701 use the NVRAM for fetching info. */
  static void __devinit tg3_nvram_init(struct tg3 *tp)
  {
@@ -224,7 +224,7 @@
  	tw32_f(GRC_EEPROM_ADDR,
  	     (EEPROM_ADDR_FSM_RESET |
  	      (EEPROM_DEFAULT_CLOCK_PERIOD <<
-@@ -11506,6 +11573,9 @@ static int tg3_nvram_write_block(struct 
+@@ -11515,6 +11582,9 @@ static int tg3_nvram_write_block(struct 
  {
  	int ret;
  
@@ -234,7 +234,7 @@
  	if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
  		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
  		       ~GRC_LCLCTRL_GPIO_OUTPUT1);
-@@ -12788,6 +12858,11 @@ static int __devinit tg3_get_invariants(
+@@ -12800,6 +12870,11 @@ static int __devinit tg3_get_invariants(
  	      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
  		tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
  
@@ -246,7 +246,7 @@
  	/* Get eeprom hw config before calling tg3_set_power_state().
  	 * In particular, the TG3_FLG2_IS_NIC flag must be
  	 * determined before calling tg3_set_power_state() so that
-@@ -13177,6 +13252,10 @@ static int __devinit tg3_get_device_addr
+@@ -13189,6 +13264,10 @@ static int __devinit tg3_get_device_addr
  	}
  
  	if (!is_valid_ether_addr(&dev->dev_addr[0])) {
@@ -257,7 +257,7 @@
  #ifdef CONFIG_SPARC
  		if (!tg3_get_default_macaddr_sparc(tp))
  			return 0;
-@@ -13669,6 +13748,7 @@ static char * __devinit tg3_phy_string(s
+@@ -13681,6 +13760,7 @@ static char * __devinit tg3_phy_string(s
  	case PHY_ID_BCM5704:	return "5704";
  	case PHY_ID_BCM5705:	return "5705";
  	case PHY_ID_BCM5750:	return "5750";
@@ -265,7 +265,7 @@
  	case PHY_ID_BCM5752:	return "5752";
  	case PHY_ID_BCM5714:	return "5714";
  	case PHY_ID_BCM5780:	return "5780";
-@@ -13880,6 +13960,13 @@ static int __devinit tg3_init_one(struct
+@@ -13892,6 +13972,13 @@ static int __devinit tg3_init_one(struct
  		tp->msg_enable = tg3_debug;
  	else
  		tp->msg_enable = TG3_DEF_MSG_ENABLE;
@@ -291,7 +291,7 @@
  
  #define NIC_SRAM_RX_MINI_BUFFER_DESC	0x00001000
  
-@@ -2821,6 +2824,7 @@ struct tg3 {
+@@ -2824,6 +2827,7 @@ struct tg3 {
  #define PHY_ID_BCM5714			0x60008340
  #define PHY_ID_BCM5780			0x60008350
  #define PHY_ID_BCM5755			0xbc050cc0
@@ -299,7 +299,7 @@
  #define PHY_ID_BCM5787			0xbc050ce0
  #define PHY_ID_BCM5756			0xbc050ed0
  #define PHY_ID_BCM5784			0xbc050fa0
-@@ -2865,7 +2869,7 @@ struct tg3 {
+@@ -2868,7 +2872,7 @@ struct tg3 {
  	 (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
  	 (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
  	 (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \
diff --git a/target/linux/brcm47xx/patches-2.6.32/813-use_netdev_alloc_skb.patch b/target/linux/brcm47xx/patches-2.6.32/813-use_netdev_alloc_skb.patch
index c431e40967..a9b2db586a 100644
--- a/target/linux/brcm47xx/patches-2.6.32/813-use_netdev_alloc_skb.patch
+++ b/target/linux/brcm47xx/patches-2.6.32/813-use_netdev_alloc_skb.patch
@@ -1,6 +1,6 @@
 --- a/drivers/net/b44.c
 +++ b/drivers/net/b44.c
-@@ -815,7 +815,7 @@ static int b44_rx(struct b44 *bp, int bu
+@@ -848,7 +848,7 @@ static int b44_rx(struct b44 *bp, int bu
  			struct sk_buff *copy_skb;
  
  			b44_recycle_rx(bp, cons, bp->rx_prod);
diff --git a/target/linux/brcm47xx/patches-2.6.32/920-cache-wround.patch b/target/linux/brcm47xx/patches-2.6.32/920-cache-wround.patch
index 3a527df251..688d3e1389 100644
--- a/target/linux/brcm47xx/patches-2.6.32/920-cache-wround.patch
+++ b/target/linux/brcm47xx/patches-2.6.32/920-cache-wround.patch
@@ -31,7 +31,7 @@
  
 --- a/arch/mips/mm/tlbex.c
 +++ b/arch/mips/mm/tlbex.c
-@@ -601,6 +601,9 @@ build_get_pgde32(u32 **p, unsigned int t
+@@ -595,6 +595,9 @@ build_get_pgde32(u32 **p, unsigned int t
  #endif
  	uasm_i_addu(p, ptr, tmp, ptr);
  #else
@@ -41,7 +41,7 @@
  	UASM_i_LA_mostly(p, ptr, pgdc);
  #endif
  	uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
-@@ -739,12 +742,12 @@ static void __cpuinit build_r4000_tlb_re
+@@ -733,12 +736,12 @@ static void __cpuinit build_r4000_tlb_re
  		/* No need for uasm_i_nop */
  	}
  
@@ -57,7 +57,7 @@
  	build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
  #endif
  
-@@ -756,6 +759,9 @@ static void __cpuinit build_r4000_tlb_re
+@@ -750,6 +753,9 @@ static void __cpuinit build_r4000_tlb_re
  	build_update_entries(&p, K0, K1);
  	build_tlb_write_entry(&p, &l, &r, tlb_random);
  	uasm_l_leave(&l, p);
@@ -67,7 +67,7 @@
  	uasm_i_eret(&p); /* return from trap */
  
  #ifdef CONFIG_HUGETLB_PAGE
-@@ -1196,12 +1202,12 @@ build_r4000_tlbchange_handler_head(u32 *
+@@ -1188,12 +1194,12 @@ build_r4000_tlbchange_handler_head(u32 *
  				   struct uasm_reloc **r, unsigned int pte,
  				   unsigned int ptr)
  {
@@ -83,7 +83,7 @@
  	build_get_pgde32(p, pte, ptr); /* get pgd in ptr */
  #endif
  
-@@ -1238,6 +1244,9 @@ build_r4000_tlbchange_handler_tail(u32 *
+@@ -1230,6 +1236,9 @@ build_r4000_tlbchange_handler_tail(u32 *
  	build_update_entries(p, tmp, ptr);
  	build_tlb_write_entry(p, l, r, tlb_indexed);
  	uasm_l_leave(l, *p);
diff --git a/target/linux/brcm47xx/patches-2.6.32/930-bcm47xx-pci-iomem.patch b/target/linux/brcm47xx/patches-2.6.32/930-bcm47xx-pci-iomem.patch
deleted file mode 100644
index 4f47a3c52d..0000000000
--- a/target/linux/brcm47xx/patches-2.6.32/930-bcm47xx-pci-iomem.patch
+++ /dev/null
@@ -1,51 +0,0 @@
---- a/drivers/ssb/driver_pcicore.c
-+++ b/drivers/ssb/driver_pcicore.c
-@@ -246,20 +246,12 @@ static struct pci_controller ssb_pcicore
- 	.pci_ops	= &ssb_pcicore_pciops,
- 	.io_resource	= &ssb_pcicore_io_resource,
- 	.mem_resource	= &ssb_pcicore_mem_resource,
--	.mem_offset	= 0x24000000,
- };
- 
--static u32 ssb_pcicore_pcibus_iobase = 0x100;
--static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
--
- /* This function is called when doing a pci_enable_device().
-  * We must first check if the device is a device on the PCI-core bridge. */
- int ssb_pcicore_plat_dev_init(struct pci_dev *d)
- {
--	struct resource *res;
--	int pos, size;
--	u32 *base;
--
- 	if (d->bus->ops != &ssb_pcicore_pciops) {
- 		/* This is not a device on the PCI-core bridge. */
- 		return -ENODEV;
-@@ -268,27 +260,6 @@ int ssb_pcicore_plat_dev_init(struct pci
- 	ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
- 		   pci_name(d));
- 
--	/* Fix up resource bases */
--	for (pos = 0; pos < 6; pos++) {
--		res = &d->resource[pos];
--		if (res->flags & IORESOURCE_IO)
--			base = &ssb_pcicore_pcibus_iobase;
--		else
--			base = &ssb_pcicore_pcibus_membase;
--		res->flags |= IORESOURCE_PCI_FIXED;
--		if (res->end) {
--			size = res->end - res->start + 1;
--			if (*base & (size - 1))
--				*base = (*base + size) & ~(size - 1);
--			res->start = *base;
--			res->end = res->start + size - 1;
--			*base += size;
--			pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
--		}
--		/* Fix up PCI bridge BAR0 only */
--		if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
--			break;
--	}
- 	/* Fix up interrupt lines */
- 	d->irq = ssb_mips_irq(extpci_core->dev) + 2;
- 	pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
diff --git a/target/linux/brcm47xx/patches-2.6.32/951-brcm4716-defines.patch b/target/linux/brcm47xx/patches-2.6.32/951-brcm4716-defines.patch
index 5cc51100f8..482dbad02e 100644
--- a/target/linux/brcm47xx/patches-2.6.32/951-brcm4716-defines.patch
+++ b/target/linux/brcm47xx/patches-2.6.32/951-brcm4716-defines.patch
@@ -60,7 +60,7 @@
  
  /* Enumeration space constants */
  #define SSB_CORE_SIZE		0x1000	/* Size of a core MMIO area */
-@@ -452,5 +454,41 @@ enum {
+@@ -453,5 +455,41 @@ enum {
  #define SSB_ADM_BASE2			0xFFFF0000	/* Type2 base address for the core */
  #define SSB_ADM_BASE2_SHIFT		16
  
diff --git a/target/linux/brcm47xx/patches-2.6.33/180-ssb_extif_interrupt.patch b/target/linux/brcm47xx/patches-2.6.33/180-ssb_extif_interrupt.patch
deleted file mode 100644
index d89531cda1..0000000000
--- a/target/linux/brcm47xx/patches-2.6.33/180-ssb_extif_interrupt.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 83e34f03ee9b86b49bde4707a1fe03a1837e29be Mon Sep 17 00:00:00 2001
-From: Jochen Friedrich <jochen@scram.de>
-Date: Wed, 3 Feb 2010 21:28:11 +0100
-Subject: [PATCH 1/1] ssb: fix interrupt assignment
-
-Explicitely enable shared interrupt 2 for any core that didn't get a dedicated IRQ
-anymore (fallthrough case) and for EXTIF cores to make gpio interrupts work.
-Also remove a bogus comment.
-
-Signed-off-by: Jochen Friedrich <jochen@scram.de>
-Signed-off-by: John W. Linville <linville@tuxdriver.com>
----
- drivers/ssb/driver_mipscore.c |    5 ++++-
- 1 files changed, 4 insertions(+), 1 deletions(-)
-
---- a/drivers/ssb/driver_mipscore.c
-+++ b/drivers/ssb/driver_mipscore.c
-@@ -270,7 +270,6 @@ void ssb_mipscore_init(struct ssb_mipsco
- 				set_irq(dev, irq++);
- 			}
- 			break;
--			/* fallthrough */
- 		case SSB_DEV_PCI:
- 		case SSB_DEV_ETHERNET:
- 		case SSB_DEV_ETHERNET_GBIT:
-@@ -281,6 +280,10 @@ void ssb_mipscore_init(struct ssb_mipsco
- 				set_irq(dev, irq++);
- 				break;
- 			}
-+			/* fallthrough */
-+		case SSB_DEV_EXTIF:
-+			set_irq(dev, 0);
-+			break;
- 		}
- 	}
- 	ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
diff --git a/target/linux/brcm47xx/patches-2.6.33/220-bcm5354.patch b/target/linux/brcm47xx/patches-2.6.33/220-bcm5354.patch
index f396ca745a..a6ab0292ba 100644
--- a/target/linux/brcm47xx/patches-2.6.33/220-bcm5354.patch
+++ b/target/linux/brcm47xx/patches-2.6.33/220-bcm5354.patch
@@ -1,6 +1,6 @@
 --- a/drivers/ssb/driver_chipcommon.c
 +++ b/drivers/ssb/driver_chipcommon.c
-@@ -258,6 +258,8 @@ void ssb_chipco_resume(struct ssb_chipco
+@@ -260,6 +260,8 @@ void ssb_chipco_resume(struct ssb_chipco
  void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
                               u32 *plltype, u32 *n, u32 *m)
  {
@@ -9,7 +9,7 @@
  	*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
  	*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
  	switch (*plltype) {
-@@ -281,6 +283,8 @@ void ssb_chipco_get_clockcpu(struct ssb_
+@@ -283,6 +285,8 @@ void ssb_chipco_get_clockcpu(struct ssb_
  void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
  				 u32 *plltype, u32 *n, u32 *m)
  {
@@ -31,7 +31,7 @@
  	}
 --- a/drivers/ssb/main.c
 +++ b/drivers/ssb/main.c
-@@ -1069,6 +1069,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
+@@ -1072,6 +1072,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
  
  	if (bus->chip_id == 0x5365) {
  		rate = 100000000;
diff --git a/target/linux/brcm47xx/patches-2.6.33/930-bcm47xx-pci-iomem.patch b/target/linux/brcm47xx/patches-2.6.33/930-bcm47xx-pci-iomem.patch
deleted file mode 100644
index 4f47a3c52d..0000000000
--- a/target/linux/brcm47xx/patches-2.6.33/930-bcm47xx-pci-iomem.patch
+++ /dev/null
@@ -1,51 +0,0 @@
---- a/drivers/ssb/driver_pcicore.c
-+++ b/drivers/ssb/driver_pcicore.c
-@@ -246,20 +246,12 @@ static struct pci_controller ssb_pcicore
- 	.pci_ops	= &ssb_pcicore_pciops,
- 	.io_resource	= &ssb_pcicore_io_resource,
- 	.mem_resource	= &ssb_pcicore_mem_resource,
--	.mem_offset	= 0x24000000,
- };
- 
--static u32 ssb_pcicore_pcibus_iobase = 0x100;
--static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
--
- /* This function is called when doing a pci_enable_device().
-  * We must first check if the device is a device on the PCI-core bridge. */
- int ssb_pcicore_plat_dev_init(struct pci_dev *d)
- {
--	struct resource *res;
--	int pos, size;
--	u32 *base;
--
- 	if (d->bus->ops != &ssb_pcicore_pciops) {
- 		/* This is not a device on the PCI-core bridge. */
- 		return -ENODEV;
-@@ -268,27 +260,6 @@ int ssb_pcicore_plat_dev_init(struct pci
- 	ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
- 		   pci_name(d));
- 
--	/* Fix up resource bases */
--	for (pos = 0; pos < 6; pos++) {
--		res = &d->resource[pos];
--		if (res->flags & IORESOURCE_IO)
--			base = &ssb_pcicore_pcibus_iobase;
--		else
--			base = &ssb_pcicore_pcibus_membase;
--		res->flags |= IORESOURCE_PCI_FIXED;
--		if (res->end) {
--			size = res->end - res->start + 1;
--			if (*base & (size - 1))
--				*base = (*base + size) & ~(size - 1);
--			res->start = *base;
--			res->end = res->start + size - 1;
--			*base += size;
--			pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
--		}
--		/* Fix up PCI bridge BAR0 only */
--		if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
--			break;
--	}
- 	/* Fix up interrupt lines */
- 	d->irq = ssb_mips_irq(extpci_core->dev) + 2;
- 	pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
diff --git a/target/linux/brcm47xx/patches-2.6.33/951-brcm4716-defines.patch b/target/linux/brcm47xx/patches-2.6.33/951-brcm4716-defines.patch
index 5cc51100f8..482dbad02e 100644
--- a/target/linux/brcm47xx/patches-2.6.33/951-brcm4716-defines.patch
+++ b/target/linux/brcm47xx/patches-2.6.33/951-brcm4716-defines.patch
@@ -60,7 +60,7 @@
  
  /* Enumeration space constants */
  #define SSB_CORE_SIZE		0x1000	/* Size of a core MMIO area */
-@@ -452,5 +454,41 @@ enum {
+@@ -453,5 +455,41 @@ enum {
  #define SSB_ADM_BASE2			0xFFFF0000	/* Type2 base address for the core */
  #define SSB_ADM_BASE2_SHIFT		16
  
diff --git a/target/linux/brcm47xx/patches-2.6.34/220-bcm5354.patch b/target/linux/brcm47xx/patches-2.6.34/220-bcm5354.patch
index a2691b008d..1d75e171d3 100644
--- a/target/linux/brcm47xx/patches-2.6.34/220-bcm5354.patch
+++ b/target/linux/brcm47xx/patches-2.6.34/220-bcm5354.patch
@@ -1,6 +1,6 @@
 --- a/drivers/ssb/driver_chipcommon.c
 +++ b/drivers/ssb/driver_chipcommon.c
-@@ -258,6 +258,8 @@ void ssb_chipco_resume(struct ssb_chipco
+@@ -260,6 +260,8 @@ void ssb_chipco_resume(struct ssb_chipco
  void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
                               u32 *plltype, u32 *n, u32 *m)
  {
@@ -9,7 +9,7 @@
  	*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
  	*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
  	switch (*plltype) {
-@@ -281,6 +283,8 @@ void ssb_chipco_get_clockcpu(struct ssb_
+@@ -283,6 +285,8 @@ void ssb_chipco_get_clockcpu(struct ssb_
  void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
  				 u32 *plltype, u32 *n, u32 *m)
  {
@@ -31,7 +31,7 @@
  	}
 --- a/drivers/ssb/main.c
 +++ b/drivers/ssb/main.c
-@@ -1070,6 +1070,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
+@@ -1073,6 +1073,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
  
  	if (bus->chip_id == 0x5365) {
  		rate = 100000000;
diff --git a/target/linux/brcm47xx/patches-2.6.34/951-brcm4716-defines.patch b/target/linux/brcm47xx/patches-2.6.34/951-brcm4716-defines.patch
index 5cc51100f8..482dbad02e 100644
--- a/target/linux/brcm47xx/patches-2.6.34/951-brcm4716-defines.patch
+++ b/target/linux/brcm47xx/patches-2.6.34/951-brcm4716-defines.patch
@@ -60,7 +60,7 @@
  
  /* Enumeration space constants */
  #define SSB_CORE_SIZE		0x1000	/* Size of a core MMIO area */
-@@ -452,5 +454,41 @@ enum {
+@@ -453,5 +455,41 @@ enum {
  #define SSB_ADM_BASE2			0xFFFF0000	/* Type2 base address for the core */
  #define SSB_ADM_BASE2_SHIFT		16
  
diff --git a/target/linux/generic-2.6/patches-2.6.30/941-ssb_update.patch b/target/linux/generic-2.6/patches-2.6.30/941-ssb_update.patch
index 7fdb3ca26e..8d2d158953 100644
--- a/target/linux/generic-2.6/patches-2.6.30/941-ssb_update.patch
+++ b/target/linux/generic-2.6/patches-2.6.30/941-ssb_update.patch
@@ -22,7 +22,28 @@
  struct pmu0_plltab_entry {
  	u16 freq;	/* Crystal frequency in kHz.*/
  	u8 xf;		/* Crystal frequency value for PMU control */
-@@ -506,3 +521,82 @@ void ssb_pmu_init(struct ssb_chipcommon 
+@@ -317,6 +332,12 @@ static void ssb_pmu_pll_init(struct ssb_
+ 	case 0x5354:
+ 		ssb_pmu0_pllinit_r0(cc, crystalfreq);
+ 		break;
++	case 0x4322:
++		if (cc->pmu.rev == 2) {
++			chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, 0x0000000A);
++			chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
++		}
++		break;
+ 	default:
+ 		ssb_printk(KERN_ERR PFX
+ 			   "ERROR: PLL init unknown for device %04X\n",
+@@ -402,6 +423,7 @@ static void ssb_pmu_resources_init(struc
+ 
+ 	switch (bus->chip_id) {
+ 	case 0x4312:
++	case 0x4322:
+ 		/* We keep the default settings:
+ 		 * min_msk = 0xCBB
+ 		 * max_msk = 0x7FFFF
+@@ -506,3 +528,82 @@ void ssb_pmu_init(struct ssb_chipcommon 
  	ssb_pmu_pll_init(cc);
  	ssb_pmu_resources_init(cc);
  }
@@ -139,9 +160,12 @@
  /* ssb must be initialized after PCI but before the ssb drivers.
 --- a/drivers/ssb/pci.c
 +++ b/drivers/ssb/pci.c
-@@ -169,8 +169,14 @@ err_pci:
+@@ -167,10 +167,16 @@ err_pci:
+ }
+ 
  /* Get the word-offset for a SSB_SPROM_XXX define. */
- #define SPOFF(offset)	(((offset) - SSB_SPROM_BASE) / sizeof(u16))
+-#define SPOFF(offset)	(((offset) - SSB_SPROM_BASE) / sizeof(u16))
++#define SPOFF(offset)	((offset) / sizeof(u16))
  /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
 -#define SPEX(_outvar, _offset, _mask, _shift)	\
 +#define SPEX16(_outvar, _offset, _mask, _shift)	\
@@ -155,6 +179,24 @@
  
  static inline u8 ssb_crc8(u8 crc, u8 data)
  {
+@@ -247,7 +253,7 @@ static int sprom_do_read(struct ssb_bus 
+ 	int i;
+ 
+ 	for (i = 0; i < bus->sprom_size; i++)
+-		sprom[i] = ioread16(bus->mmio + SSB_SPROM_BASE + (i * 2));
++		sprom[i] = ioread16(bus->mmio + bus->sprom_offset + (i * 2));
+ 
+ 	return 0;
+ }
+@@ -278,7 +284,7 @@ static int sprom_do_write(struct ssb_bus
+ 			ssb_printk("75%%");
+ 		else if (i % 2)
+ 			ssb_printk(".");
+-		writew(sprom[i], bus->mmio + SSB_SPROM_BASE + (i * 2));
++		writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
+ 		mmiowb();
+ 		msleep(20);
+ 	}
 @@ -474,12 +480,14 @@ static void sprom_extract_r8(struct ssb_
  
  	/* extract the MAC address */
@@ -235,6 +277,21 @@
  			sprom_extract_r123(out, in);
  		}
  	}
+@@ -568,6 +620,14 @@ static int ssb_pci_sprom_get(struct ssb_
+ 	int err = -ENOMEM;
+ 	u16 *buf;
+ 
++	if (!ssb_is_sprom_available(bus)) {
++		ssb_printk(KERN_ERR PFX "No SPROM available!\n");
++		return -ENODEV;
++	}
++
++	bus->sprom_offset = (bus->chipco.dev->id.revision < 31) ?
++		SSB_SPROM_BASE1 : SSB_SPROM_BASE31;
++
+ 	buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
+ 	if (!buf)
+ 		goto out;
 --- a/drivers/ssb/pcmcia.c
 +++ b/drivers/ssb/pcmcia.c
 @@ -583,7 +583,7 @@ static int ssb_pcmcia_sprom_write_all(st
@@ -255,26 +312,259 @@
  			   "Could not disable SPROM write access.\n");
  		failed = 1;
  	}
-@@ -678,7 +678,8 @@ int ssb_pcmcia_get_invariants(struct ssb
- 			sprom->board_rev = tuple.TupleData[1];
- 			break;
- 		case SSB_PCMCIA_CIS_PA:
+@@ -617,134 +617,140 @@ static int ssb_pcmcia_sprom_check_crc(co
+ 	}						\
+   } while (0)
+ 
+-int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
+-			      struct ssb_init_invariants *iv)
++static int ssb_pcmcia_get_mac(struct pcmcia_device *p_dev,
++			tuple_t *tuple,
++			void *priv)
+ {
+-	tuple_t tuple;
+-	int res;
+-	unsigned char buf[32];
++	struct ssb_sprom *sprom = priv;
++
++	if (tuple->TupleData[0] != CISTPL_FUNCE_LAN_NODE_ID)
++		return -EINVAL;
++	if (tuple->TupleDataLen != ETH_ALEN + 2)
++		return -EINVAL;
++	if (tuple->TupleData[1] != ETH_ALEN)
++		return -EINVAL;
++	memcpy(sprom->il0mac, &tuple->TupleData[2], ETH_ALEN);
++	return 0;
++};
++
++static int ssb_pcmcia_do_get_invariants(struct pcmcia_device *p_dev,
++					tuple_t *tuple,
++					void *priv)
++{
++	struct ssb_init_invariants *iv = priv;
+ 	struct ssb_sprom *sprom = &iv->sprom;
+ 	struct ssb_boardinfo *bi = &iv->boardinfo;
+ 	const char *error_description;
+ 
++	GOTO_ERROR_ON(tuple->TupleDataLen < 1, "VEN tpl < 1");
++	switch (tuple->TupleData[0]) {
++	case SSB_PCMCIA_CIS_ID:
++		GOTO_ERROR_ON((tuple->TupleDataLen != 5) &&
++			      (tuple->TupleDataLen != 7),
++			      "id tpl size");
++		bi->vendor = tuple->TupleData[1] |
++			((u16)tuple->TupleData[2] << 8);
++		break;
++	case SSB_PCMCIA_CIS_BOARDREV:
++		GOTO_ERROR_ON(tuple->TupleDataLen != 2,
++			"boardrev tpl size");
++		sprom->board_rev = tuple->TupleData[1];
++		break;
++	case SSB_PCMCIA_CIS_PA:
++		GOTO_ERROR_ON((tuple->TupleDataLen != 9) &&
++			(tuple->TupleDataLen != 10),
++			"pa tpl size");
++		sprom->pa0b0 = tuple->TupleData[1] |
++			((u16)tuple->TupleData[2] << 8);
++		sprom->pa0b1 = tuple->TupleData[3] |
++			((u16)tuple->TupleData[4] << 8);
++		sprom->pa0b2 = tuple->TupleData[5] |
++			((u16)tuple->TupleData[6] << 8);
++		sprom->itssi_a = tuple->TupleData[7];
++		sprom->itssi_bg = tuple->TupleData[7];
++		sprom->maxpwr_a = tuple->TupleData[8];
++		sprom->maxpwr_bg = tuple->TupleData[8];
++		break;
++	case SSB_PCMCIA_CIS_OEMNAME:
++		/* We ignore this. */
++		break;
++	case SSB_PCMCIA_CIS_CCODE:
++		GOTO_ERROR_ON(tuple->TupleDataLen != 2,
++			"ccode tpl size");
++		sprom->country_code = tuple->TupleData[1];
++		break;
++	case SSB_PCMCIA_CIS_ANTENNA:
++		GOTO_ERROR_ON(tuple->TupleDataLen != 2,
++			"ant tpl size");
++		sprom->ant_available_a = tuple->TupleData[1];
++		sprom->ant_available_bg = tuple->TupleData[1];
++		break;
++	case SSB_PCMCIA_CIS_ANTGAIN:
++		GOTO_ERROR_ON(tuple->TupleDataLen != 2,
++			"antg tpl size");
++		sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
++		sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
++		sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
++		sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
++		sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
++		sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
++		sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
++		sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
++		break;
++	case SSB_PCMCIA_CIS_BFLAGS:
++		GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
++			(tuple->TupleDataLen != 5),
++			"bfl tpl size");
++		sprom->boardflags_lo = tuple->TupleData[1] |
++			((u16)tuple->TupleData[2] << 8);
++		break;
++	case SSB_PCMCIA_CIS_LEDS:
++		GOTO_ERROR_ON(tuple->TupleDataLen != 5,
++			"leds tpl size");
++		sprom->gpio0 = tuple->TupleData[1];
++		sprom->gpio1 = tuple->TupleData[2];
++		sprom->gpio2 = tuple->TupleData[3];
++		sprom->gpio3 = tuple->TupleData[4];
++		break;
++	}
++	return -ENOSPC; /* continue with next entry */
++
++error:
++	ssb_printk(KERN_ERR PFX
++		   "PCMCIA: Failed to fetch device invariants: %s\n",
++		   error_description);
++	return -ENODEV;
++}
++
++
++int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
++			      struct ssb_init_invariants *iv)
++{
++	struct ssb_sprom *sprom = &iv->sprom;
++	int res;
++
+ 	memset(sprom, 0xFF, sizeof(*sprom));
+ 	sprom->revision = 1;
+ 	sprom->boardflags_lo = 0;
+ 	sprom->boardflags_hi = 0;
+ 
+ 	/* First fetch the MAC address. */
+-	memset(&tuple, 0, sizeof(tuple));
+-	tuple.DesiredTuple = CISTPL_FUNCE;
+-	tuple.TupleData = buf;
+-	tuple.TupleDataMax = sizeof(buf);
+-	res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
+-	GOTO_ERROR_ON(res != 0, "MAC first tpl");
+-	res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
+-	GOTO_ERROR_ON(res != 0, "MAC first tpl data");
+-	while (1) {
+-		GOTO_ERROR_ON(tuple.TupleDataLen < 1, "MAC tpl < 1");
+-		if (tuple.TupleData[0] == CISTPL_FUNCE_LAN_NODE_ID)
+-			break;
+-		res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
+-		GOTO_ERROR_ON(res != 0, "MAC next tpl");
+-		res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
+-		GOTO_ERROR_ON(res != 0, "MAC next tpl data");
++	res = pcmcia_loop_tuple(bus->host_pcmcia, CISTPL_FUNCE,
++				ssb_pcmcia_get_mac, sprom);
++	if (res != 0) {
++		ssb_printk(KERN_ERR PFX
++			"PCMCIA: Failed to fetch MAC address\n");
++		return -ENODEV;
+ 	}
+-	GOTO_ERROR_ON(tuple.TupleDataLen != ETH_ALEN + 2, "MAC tpl size");
+-	memcpy(sprom->il0mac, &tuple.TupleData[2], ETH_ALEN);
+ 
+ 	/* Fetch the vendor specific tuples. */
+-	memset(&tuple, 0, sizeof(tuple));
+-	tuple.DesiredTuple = SSB_PCMCIA_CIS;
+-	tuple.TupleData = buf;
+-	tuple.TupleDataMax = sizeof(buf);
+-	res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
+-	GOTO_ERROR_ON(res != 0, "VEN first tpl");
+-	res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
+-	GOTO_ERROR_ON(res != 0, "VEN first tpl data");
+-	while (1) {
+-		GOTO_ERROR_ON(tuple.TupleDataLen < 1, "VEN tpl < 1");
+-		switch (tuple.TupleData[0]) {
+-		case SSB_PCMCIA_CIS_ID:
+-			GOTO_ERROR_ON((tuple.TupleDataLen != 5) &&
+-				      (tuple.TupleDataLen != 7),
+-				      "id tpl size");
+-			bi->vendor = tuple.TupleData[1] |
+-			       ((u16)tuple.TupleData[2] << 8);
+-			break;
+-		case SSB_PCMCIA_CIS_BOARDREV:
+-			GOTO_ERROR_ON(tuple.TupleDataLen != 2,
+-				      "boardrev tpl size");
+-			sprom->board_rev = tuple.TupleData[1];
+-			break;
+-		case SSB_PCMCIA_CIS_PA:
 -			GOTO_ERROR_ON(tuple.TupleDataLen != 9,
-+			GOTO_ERROR_ON((tuple.TupleDataLen != 9) &&
-+				      (tuple.TupleDataLen != 10),
- 				      "pa tpl size");
- 			sprom->pa0b0 = tuple.TupleData[1] |
- 				 ((u16)tuple.TupleData[2] << 8);
-@@ -718,7 +719,8 @@ int ssb_pcmcia_get_invariants(struct ssb
- 			sprom->antenna_gain.ghz5.a3 = tuple.TupleData[1];
- 			break;
- 		case SSB_PCMCIA_CIS_BFLAGS:
+-				      "pa tpl size");
+-			sprom->pa0b0 = tuple.TupleData[1] |
+-				 ((u16)tuple.TupleData[2] << 8);
+-			sprom->pa0b1 = tuple.TupleData[3] |
+-				 ((u16)tuple.TupleData[4] << 8);
+-			sprom->pa0b2 = tuple.TupleData[5] |
+-				 ((u16)tuple.TupleData[6] << 8);
+-			sprom->itssi_a = tuple.TupleData[7];
+-			sprom->itssi_bg = tuple.TupleData[7];
+-			sprom->maxpwr_a = tuple.TupleData[8];
+-			sprom->maxpwr_bg = tuple.TupleData[8];
+-			break;
+-		case SSB_PCMCIA_CIS_OEMNAME:
+-			/* We ignore this. */
+-			break;
+-		case SSB_PCMCIA_CIS_CCODE:
+-			GOTO_ERROR_ON(tuple.TupleDataLen != 2,
+-				      "ccode tpl size");
+-			sprom->country_code = tuple.TupleData[1];
+-			break;
+-		case SSB_PCMCIA_CIS_ANTENNA:
+-			GOTO_ERROR_ON(tuple.TupleDataLen != 2,
+-				      "ant tpl size");
+-			sprom->ant_available_a = tuple.TupleData[1];
+-			sprom->ant_available_bg = tuple.TupleData[1];
+-			break;
+-		case SSB_PCMCIA_CIS_ANTGAIN:
+-			GOTO_ERROR_ON(tuple.TupleDataLen != 2,
+-				      "antg tpl size");
+-			sprom->antenna_gain.ghz24.a0 = tuple.TupleData[1];
+-			sprom->antenna_gain.ghz24.a1 = tuple.TupleData[1];
+-			sprom->antenna_gain.ghz24.a2 = tuple.TupleData[1];
+-			sprom->antenna_gain.ghz24.a3 = tuple.TupleData[1];
+-			sprom->antenna_gain.ghz5.a0 = tuple.TupleData[1];
+-			sprom->antenna_gain.ghz5.a1 = tuple.TupleData[1];
+-			sprom->antenna_gain.ghz5.a2 = tuple.TupleData[1];
+-			sprom->antenna_gain.ghz5.a3 = tuple.TupleData[1];
+-			break;
+-		case SSB_PCMCIA_CIS_BFLAGS:
 -			GOTO_ERROR_ON(tuple.TupleDataLen != 3,
-+			GOTO_ERROR_ON((tuple.TupleDataLen != 3) &&
-+				      (tuple.TupleDataLen != 5),
- 				      "bfl tpl size");
- 			sprom->boardflags_lo = tuple.TupleData[1] |
- 					 ((u16)tuple.TupleData[2] << 8);
+-				      "bfl tpl size");
+-			sprom->boardflags_lo = tuple.TupleData[1] |
+-					 ((u16)tuple.TupleData[2] << 8);
+-			break;
+-		case SSB_PCMCIA_CIS_LEDS:
+-			GOTO_ERROR_ON(tuple.TupleDataLen != 5,
+-				      "leds tpl size");
+-			sprom->gpio0 = tuple.TupleData[1];
+-			sprom->gpio1 = tuple.TupleData[2];
+-			sprom->gpio2 = tuple.TupleData[3];
+-			sprom->gpio3 = tuple.TupleData[4];
+-			break;
+-		}
+-		res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
+-		if (res == -ENOSPC)
+-			break;
+-		GOTO_ERROR_ON(res != 0, "VEN next tpl");
+-		res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
+-		GOTO_ERROR_ON(res != 0, "VEN next tpl data");
+-	}
++	res = pcmcia_loop_tuple(bus->host_pcmcia, SSB_PCMCIA_CIS,
++				ssb_pcmcia_do_get_invariants, sprom);
++	if ((res == 0) || (res == -ENOSPC))
++		return 0;
+ 
+-	return 0;
+-error:
+ 	ssb_printk(KERN_ERR PFX
+-		   "PCMCIA: Failed to fetch device invariants: %s\n",
+-		   error_description);
++			"PCMCIA: Failed to fetch device invariants\n");
+ 	return -ENODEV;
+ }
+ 
 --- a/include/linux/ssb/ssb.h
 +++ b/include/linux/ssb/ssb.h
 @@ -27,24 +27,54 @@ struct ssb_sprom {
@@ -355,9 +645,13 @@
  };
  
  /* board_vendor */
-@@ -240,8 +271,12 @@ struct ssb_bus {
+@@ -238,20 +269,33 @@ struct ssb_bus {
  
- 	/* The core in the basic address register window. (PCI bus only) */
+ 	const struct ssb_bus_ops *ops;
+ 
+-	/* The core in the basic address register window. (PCI bus only) */
++	/* The core currently mapped into the MMIO window.
++	 * Not valid on all host-buses. So don't use outside of SSB. */
  	struct ssb_device *mapped_device;
 -	/* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
 -	u8 mapped_pcmcia_seg;
@@ -370,19 +664,38 @@
  	/* Lock for core and segment switching.
  	 * On PCMCIA-host busses this is used to protect the whole MMIO access. */
  	spinlock_t bar_lock;
-@@ -252,6 +287,11 @@ struct ssb_bus {
- 	struct pci_dev *host_pci;
- 	/* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
- 	struct pcmcia_device *host_pcmcia;
-+	/* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
-+	struct sdio_func *host_sdio;
+ 
+-	/* The bus this backplane is running on. */
++	/* The host-bus this backplane is running on. */
+ 	enum ssb_bustype bustype;
+-	/* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
+-	struct pci_dev *host_pci;
+-	/* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
+-	struct pcmcia_device *host_pcmcia;
++	/* Pointers to the host-bus. Check bustype before using any of these pointers. */
++	union {
++		/* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
++		struct pci_dev *host_pci;
++		/* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
++		struct pcmcia_device *host_pcmcia;
++		/* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
++		struct sdio_func *host_sdio;
++	};
 +
 +	/* See enum ssb_quirks */
 +	unsigned int quirks;
  
  #ifdef CONFIG_SSB_SPROM
  	/* Mutex to protect the SPROM writing. */
-@@ -306,6 +346,11 @@ struct ssb_bus {
+@@ -261,6 +305,7 @@ struct ssb_bus {
+ 	/* ID information about the Chip. */
+ 	u16 chip_id;
+ 	u16 chip_rev;
++	u16 sprom_offset;
+ 	u16 sprom_size;		/* number of words in sprom */
+ 	u8 chip_package;
+ 
+@@ -306,6 +351,11 @@ struct ssb_bus {
  #endif /* DEBUG */
  };
  
@@ -394,7 +707,7 @@
  /* The initialization-invariants. */
  struct ssb_init_invariants {
  	/* Versioning information about the PCB. */
-@@ -336,6 +381,12 @@ extern int ssb_bus_pcmciabus_register(st
+@@ -336,9 +386,18 @@ extern int ssb_bus_pcmciabus_register(st
  				      struct pcmcia_device *pcmcia_dev,
  				      unsigned long baseaddr);
  #endif /* CONFIG_SSB_PCMCIAHOST */
@@ -407,9 +720,58 @@
  
  extern void ssb_bus_unregister(struct ssb_bus *bus);
  
++/* Does the device have an SPROM? */
++extern bool ssb_is_sprom_available(struct ssb_bus *bus);
++
+ /* Set a fallback SPROM.
+  * See kdoc at the function definition for complete documentation. */
+ extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
 --- a/include/linux/ssb/ssb_driver_chipcommon.h
 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
-@@ -629,5 +629,15 @@ extern int ssb_chipco_serial_init(struct
+@@ -53,6 +53,7 @@
+ #define  SSB_CHIPCO_CAP_64BIT		0x08000000	/* 64-bit Backplane */
+ #define  SSB_CHIPCO_CAP_PMU		0x10000000	/* PMU available (rev >= 20) */
+ #define  SSB_CHIPCO_CAP_ECI		0x20000000	/* ECI available (rev >= 20) */
++#define  SSB_CHIPCO_CAP_SPROM		0x40000000	/* SPROM present */
+ #define SSB_CHIPCO_CORECTL		0x0008
+ #define  SSB_CHIPCO_CORECTL_UARTCLK0	0x00000001	/* Drive UART with internal clock */
+ #define	 SSB_CHIPCO_CORECTL_SE		0x00000002	/* sync clk out enable (corerev >= 3) */
+@@ -385,6 +386,7 @@
+ 
+ 
+ /** Chip specific Chip-Status register contents. */
++#define SSB_CHIPCO_CHST_4322_SPROM_EXISTS	0x00000040 /* SPROM present */
+ #define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL	0x00000003
+ #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL		0 /* OTP is powered up, use def. CIS, no SPROM */
+ #define SSB_CHIPCO_CHST_4325_SPROM_SEL		1 /* OTP is powered up, SPROM is present */
+@@ -398,6 +400,18 @@
+ #define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT	4
+ #define SSB_CHIPCO_CHST_4325_PMUTOP_2B 		0x00000200 /* 1 for 2b, 0 for to 2a */
+ 
++/** Macros to determine SPROM presence based on Chip-Status register. */
++#define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) \
++	((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
++		SSB_CHIPCO_CHST_4325_OTP_SEL)
++#define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) \
++	(status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS)
++#define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) \
++	(((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
++		SSB_CHIPCO_CHST_4325_DEFCIS_SEL) && \
++	 ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
++		SSB_CHIPCO_CHST_4325_OTP_SEL))
++
+ 
+ 
+ /** Clockcontrol masks and values **/
+@@ -564,6 +578,7 @@ struct ssb_chipcommon_pmu {
+ struct ssb_chipcommon {
+ 	struct ssb_device *dev;
+ 	u32 capabilities;
++	u32 status;
+ 	/* Fast Powerup Delay constant */
+ 	u16 fast_pwrup_delay;
+ 	struct ssb_chipcommon_pmu pmu;
+@@ -629,5 +644,15 @@ extern int ssb_chipco_serial_init(struct
  /* PMU support */
  extern void ssb_pmu_init(struct ssb_chipcommon *cc);
  
@@ -436,27 +798,289 @@
   */
  #define SSB_SPROMSIZE_WORDS		64
  #define SSB_SPROMSIZE_BYTES		(SSB_SPROMSIZE_WORDS * sizeof(u16))
-@@ -327,8 +327,11 @@
+@@ -170,26 +170,27 @@
+ #define SSB_SPROMSIZE_WORDS_R4		220
+ #define SSB_SPROMSIZE_BYTES_R123	(SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
+ #define SSB_SPROMSIZE_BYTES_R4		(SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
+-#define SSB_SPROM_BASE			0x1000
+-#define SSB_SPROM_REVISION		0x107E
++#define SSB_SPROM_BASE1			0x1000
++#define SSB_SPROM_BASE31		0x0800
++#define SSB_SPROM_REVISION		0x007E
+ #define  SSB_SPROM_REVISION_REV		0x00FF	/* SPROM Revision number */
+ #define  SSB_SPROM_REVISION_CRC		0xFF00	/* SPROM CRC8 value */
+ #define  SSB_SPROM_REVISION_CRC_SHIFT	8
+ 
+ /* SPROM Revision 1 */
+-#define SSB_SPROM1_SPID			0x1004	/* Subsystem Product ID for PCI */
+-#define SSB_SPROM1_SVID			0x1006	/* Subsystem Vendor ID for PCI */
+-#define SSB_SPROM1_PID			0x1008	/* Product ID for PCI */
+-#define SSB_SPROM1_IL0MAC		0x1048	/* 6 bytes MAC address for 802.11b/g */
+-#define SSB_SPROM1_ET0MAC		0x104E	/* 6 bytes MAC address for Ethernet */
+-#define SSB_SPROM1_ET1MAC		0x1054	/* 6 bytes MAC address for 802.11a */
+-#define SSB_SPROM1_ETHPHY		0x105A	/* Ethernet PHY settings */
++#define SSB_SPROM1_SPID			0x0004	/* Subsystem Product ID for PCI */
++#define SSB_SPROM1_SVID			0x0006	/* Subsystem Vendor ID for PCI */
++#define SSB_SPROM1_PID			0x0008	/* Product ID for PCI */
++#define SSB_SPROM1_IL0MAC		0x0048	/* 6 bytes MAC address for 802.11b/g */
++#define SSB_SPROM1_ET0MAC		0x004E	/* 6 bytes MAC address for Ethernet */
++#define SSB_SPROM1_ET1MAC		0x0054	/* 6 bytes MAC address for 802.11a */
++#define SSB_SPROM1_ETHPHY		0x005A	/* Ethernet PHY settings */
+ #define  SSB_SPROM1_ETHPHY_ET0A		0x001F	/* MII Address for enet0 */
+ #define  SSB_SPROM1_ETHPHY_ET1A		0x03E0	/* MII Address for enet1 */
+ #define  SSB_SPROM1_ETHPHY_ET1A_SHIFT	5
+ #define  SSB_SPROM1_ETHPHY_ET0M		(1<<14)	/* MDIO for enet0 */
+ #define  SSB_SPROM1_ETHPHY_ET1M		(1<<15)	/* MDIO for enet1 */
+-#define SSB_SPROM1_BINF			0x105C	/* Board info */
++#define SSB_SPROM1_BINF			0x005C	/* Board info */
+ #define  SSB_SPROM1_BINF_BREV		0x00FF	/* Board Revision */
+ #define  SSB_SPROM1_BINF_CCODE		0x0F00	/* Country Code */
+ #define  SSB_SPROM1_BINF_CCODE_SHIFT	8
+@@ -197,63 +198,63 @@
+ #define  SSB_SPROM1_BINF_ANTBG_SHIFT	12
+ #define  SSB_SPROM1_BINF_ANTA		0xC000	/* Available A-PHY antennas */
+ #define  SSB_SPROM1_BINF_ANTA_SHIFT	14
+-#define SSB_SPROM1_PA0B0		0x105E
+-#define SSB_SPROM1_PA0B1		0x1060
+-#define SSB_SPROM1_PA0B2		0x1062
+-#define SSB_SPROM1_GPIOA		0x1064	/* General Purpose IO pins 0 and 1 */
++#define SSB_SPROM1_PA0B0		0x005E
++#define SSB_SPROM1_PA0B1		0x0060
++#define SSB_SPROM1_PA0B2		0x0062
++#define SSB_SPROM1_GPIOA		0x0064	/* General Purpose IO pins 0 and 1 */
+ #define  SSB_SPROM1_GPIOA_P0		0x00FF	/* Pin 0 */
+ #define  SSB_SPROM1_GPIOA_P1		0xFF00	/* Pin 1 */
+ #define  SSB_SPROM1_GPIOA_P1_SHIFT	8
+-#define SSB_SPROM1_GPIOB		0x1066	/* General Purpuse IO pins 2 and 3 */
++#define SSB_SPROM1_GPIOB		0x0066	/* General Purpuse IO pins 2 and 3 */
+ #define  SSB_SPROM1_GPIOB_P2		0x00FF	/* Pin 2 */
+ #define  SSB_SPROM1_GPIOB_P3		0xFF00	/* Pin 3 */
+ #define  SSB_SPROM1_GPIOB_P3_SHIFT	8
+-#define SSB_SPROM1_MAXPWR		0x1068	/* Power Amplifier Max Power */
++#define SSB_SPROM1_MAXPWR		0x0068	/* Power Amplifier Max Power */
+ #define  SSB_SPROM1_MAXPWR_BG		0x00FF	/* B-PHY and G-PHY (in dBm Q5.2) */
+ #define  SSB_SPROM1_MAXPWR_A		0xFF00	/* A-PHY (in dBm Q5.2) */
+ #define  SSB_SPROM1_MAXPWR_A_SHIFT	8
+-#define SSB_SPROM1_PA1B0		0x106A
+-#define SSB_SPROM1_PA1B1		0x106C
+-#define SSB_SPROM1_PA1B2		0x106E
+-#define SSB_SPROM1_ITSSI		0x1070	/* Idle TSSI Target */
++#define SSB_SPROM1_PA1B0		0x006A
++#define SSB_SPROM1_PA1B1		0x006C
++#define SSB_SPROM1_PA1B2		0x006E
++#define SSB_SPROM1_ITSSI		0x0070	/* Idle TSSI Target */
+ #define  SSB_SPROM1_ITSSI_BG		0x00FF	/* B-PHY and G-PHY*/
+ #define  SSB_SPROM1_ITSSI_A		0xFF00	/* A-PHY */
+ #define  SSB_SPROM1_ITSSI_A_SHIFT	8
+-#define SSB_SPROM1_BFLLO		0x1072	/* Boardflags (low 16 bits) */
+-#define SSB_SPROM1_AGAIN		0x1074	/* Antenna Gain (in dBm Q5.2) */
++#define SSB_SPROM1_BFLLO		0x0072	/* Boardflags (low 16 bits) */
++#define SSB_SPROM1_AGAIN		0x0074	/* Antenna Gain (in dBm Q5.2) */
+ #define  SSB_SPROM1_AGAIN_BG		0x00FF	/* B-PHY and G-PHY */
+ #define  SSB_SPROM1_AGAIN_BG_SHIFT	0
+ #define  SSB_SPROM1_AGAIN_A		0xFF00	/* A-PHY */
+ #define  SSB_SPROM1_AGAIN_A_SHIFT	8
+ 
+ /* SPROM Revision 2 (inherits from rev 1) */
+-#define SSB_SPROM2_BFLHI		0x1038	/* Boardflags (high 16 bits) */
+-#define SSB_SPROM2_MAXP_A		0x103A	/* A-PHY Max Power */
++#define SSB_SPROM2_BFLHI		0x0038	/* Boardflags (high 16 bits) */
++#define SSB_SPROM2_MAXP_A		0x003A	/* A-PHY Max Power */
+ #define  SSB_SPROM2_MAXP_A_HI		0x00FF	/* Max Power High */
+ #define  SSB_SPROM2_MAXP_A_LO		0xFF00	/* Max Power Low */
+ #define  SSB_SPROM2_MAXP_A_LO_SHIFT	8
+-#define SSB_SPROM2_PA1LOB0		0x103C	/* A-PHY PowerAmplifier Low Settings */
+-#define SSB_SPROM2_PA1LOB1		0x103E	/* A-PHY PowerAmplifier Low Settings */
+-#define SSB_SPROM2_PA1LOB2		0x1040	/* A-PHY PowerAmplifier Low Settings */
+-#define SSB_SPROM2_PA1HIB0		0x1042	/* A-PHY PowerAmplifier High Settings */
+-#define SSB_SPROM2_PA1HIB1		0x1044	/* A-PHY PowerAmplifier High Settings */
+-#define SSB_SPROM2_PA1HIB2		0x1046	/* A-PHY PowerAmplifier High Settings */
+-#define SSB_SPROM2_OPO			0x1078	/* OFDM Power Offset from CCK Level */
++#define SSB_SPROM2_PA1LOB0		0x003C	/* A-PHY PowerAmplifier Low Settings */
++#define SSB_SPROM2_PA1LOB1		0x003E	/* A-PHY PowerAmplifier Low Settings */
++#define SSB_SPROM2_PA1LOB2		0x0040	/* A-PHY PowerAmplifier Low Settings */
++#define SSB_SPROM2_PA1HIB0		0x0042	/* A-PHY PowerAmplifier High Settings */
++#define SSB_SPROM2_PA1HIB1		0x0044	/* A-PHY PowerAmplifier High Settings */
++#define SSB_SPROM2_PA1HIB2		0x0046	/* A-PHY PowerAmplifier High Settings */
++#define SSB_SPROM2_OPO			0x0078	/* OFDM Power Offset from CCK Level */
+ #define  SSB_SPROM2_OPO_VALUE		0x00FF
+ #define  SSB_SPROM2_OPO_UNUSED		0xFF00
+-#define SSB_SPROM2_CCODE		0x107C	/* Two char Country Code */
++#define SSB_SPROM2_CCODE		0x007C	/* Two char Country Code */
+ 
+ /* SPROM Revision 3 (inherits most data from rev 2) */
+-#define SSB_SPROM3_IL0MAC		0x104A	/* 6 bytes MAC address for 802.11b/g */
+-#define SSB_SPROM3_OFDMAPO		0x102C	/* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
+-#define SSB_SPROM3_OFDMALPO		0x1030	/* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
+-#define SSB_SPROM3_OFDMAHPO		0x1034	/* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
+-#define SSB_SPROM3_GPIOLDC		0x1042	/* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
++#define SSB_SPROM3_OFDMAPO		0x002C	/* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
++#define SSB_SPROM3_OFDMALPO		0x0030	/* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
++#define SSB_SPROM3_OFDMAHPO		0x0034	/* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
++#define SSB_SPROM3_GPIOLDC		0x0042	/* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
+ #define  SSB_SPROM3_GPIOLDC_OFF		0x0000FF00	/* Off Count */
+ #define  SSB_SPROM3_GPIOLDC_OFF_SHIFT	8
+ #define  SSB_SPROM3_GPIOLDC_ON		0x00FF0000	/* On Count */
+ #define  SSB_SPROM3_GPIOLDC_ON_SHIFT	16
+-#define SSB_SPROM3_CCKPO		0x1078	/* CCK Power Offset */
++#define SSB_SPROM3_IL0MAC		0x004A	/* 6 bytes MAC address for 802.11b/g */
++#define SSB_SPROM3_CCKPO		0x0078	/* CCK Power Offset */
+ #define  SSB_SPROM3_CCKPO_1M		0x000F	/* 1M Rate PO */
+ #define  SSB_SPROM3_CCKPO_2M		0x00F0	/* 2M Rate PO */
+ #define  SSB_SPROM3_CCKPO_2M_SHIFT	4
+@@ -264,104 +265,156 @@
+ #define  SSB_SPROM3_OFDMGPO		0x107A	/* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
+ 
+ /* SPROM Revision 4 */
+-#define SSB_SPROM4_IL0MAC		0x104C	/* 6 byte MAC address for a/b/g/n */
+-#define SSB_SPROM4_ETHPHY		0x105A	/* Ethernet PHY settings ?? */
++#define SSB_SPROM4_BFLLO		0x0044	/* Boardflags (low 16 bits) */
++#define SSB_SPROM4_BFLHI		0x0046  /* Board Flags Hi */
++#define SSB_SPROM4_IL0MAC		0x004C	/* 6 byte MAC address for a/b/g/n */
++#define SSB_SPROM4_CCODE		0x0052	/* Country Code (2 bytes) */
++#define SSB_SPROM4_GPIOA		0x0056	/* Gen. Purpose IO # 0 and 1 */
++#define  SSB_SPROM4_GPIOA_P0		0x00FF	/* Pin 0 */
++#define  SSB_SPROM4_GPIOA_P1		0xFF00	/* Pin 1 */
++#define  SSB_SPROM4_GPIOA_P1_SHIFT	8
++#define SSB_SPROM4_GPIOB		0x0058	/* Gen. Purpose IO # 2 and 3 */
++#define  SSB_SPROM4_GPIOB_P2		0x00FF	/* Pin 2 */
++#define  SSB_SPROM4_GPIOB_P3		0xFF00	/* Pin 3 */
++#define  SSB_SPROM4_GPIOB_P3_SHIFT	8
++#define SSB_SPROM4_ETHPHY		0x005A	/* Ethernet PHY settings ?? */
+ #define  SSB_SPROM4_ETHPHY_ET0A		0x001F	/* MII Address for enet0 */
+ #define  SSB_SPROM4_ETHPHY_ET1A		0x03E0	/* MII Address for enet1 */
+ #define  SSB_SPROM4_ETHPHY_ET1A_SHIFT	5
+ #define  SSB_SPROM4_ETHPHY_ET0M		(1<<14)	/* MDIO for enet0 */
+ #define  SSB_SPROM4_ETHPHY_ET1M		(1<<15)	/* MDIO for enet1 */
+-#define SSB_SPROM4_CCODE		0x1052	/* Country Code (2 bytes) */
+-#define SSB_SPROM4_ANTAVAIL		0x105D  /* Antenna available bitfields */
+-#define SSB_SPROM4_ANTAVAIL_A		0x00FF	/* A-PHY bitfield */
+-#define SSB_SPROM4_ANTAVAIL_A_SHIFT	0
+-#define SSB_SPROM4_ANTAVAIL_BG		0xFF00	/* B-PHY and G-PHY bitfield */
+-#define SSB_SPROM4_ANTAVAIL_BG_SHIFT	8
+-#define SSB_SPROM4_BFLLO		0x1044	/* Boardflags (low 16 bits) */
+-#define SSB_SPROM4_AGAIN01		0x105E	/* Antenna Gain (in dBm Q5.2) */
++#define SSB_SPROM4_ANTAVAIL		0x005D  /* Antenna available bitfields */
++#define  SSB_SPROM4_ANTAVAIL_A		0x00FF	/* A-PHY bitfield */
++#define  SSB_SPROM4_ANTAVAIL_A_SHIFT	0
++#define  SSB_SPROM4_ANTAVAIL_BG		0xFF00	/* B-PHY and G-PHY bitfield */
++#define  SSB_SPROM4_ANTAVAIL_BG_SHIFT	8
++#define SSB_SPROM4_AGAIN01		0x005E	/* Antenna Gain (in dBm Q5.2) */
+ #define  SSB_SPROM4_AGAIN0		0x00FF	/* Antenna 0 */
+ #define  SSB_SPROM4_AGAIN0_SHIFT	0
+ #define  SSB_SPROM4_AGAIN1		0xFF00	/* Antenna 1 */
+ #define  SSB_SPROM4_AGAIN1_SHIFT	8
+-#define SSB_SPROM4_AGAIN23		0x1060
++#define SSB_SPROM4_AGAIN23		0x0060
+ #define  SSB_SPROM4_AGAIN2		0x00FF	/* Antenna 2 */
+ #define  SSB_SPROM4_AGAIN2_SHIFT	0
+ #define  SSB_SPROM4_AGAIN3		0xFF00	/* Antenna 3 */
+ #define  SSB_SPROM4_AGAIN3_SHIFT	8
+-#define SSB_SPROM4_BFLHI		0x1046  /* Board Flags Hi */
+-#define SSB_SPROM4_MAXP_BG		0x1080  /* Max Power BG in path 1 */
++#define SSB_SPROM4_MAXP_BG		0x0080  /* Max Power BG in path 1 */
+ #define  SSB_SPROM4_MAXP_BG_MASK	0x00FF  /* Mask for Max Power BG */
+ #define  SSB_SPROM4_ITSSI_BG		0xFF00	/* Mask for path 1 itssi_bg */
+ #define  SSB_SPROM4_ITSSI_BG_SHIFT	8
+-#define SSB_SPROM4_MAXP_A		0x108A  /* Max Power A in path 1 */
++#define SSB_SPROM4_MAXP_A		0x008A  /* Max Power A in path 1 */
+ #define  SSB_SPROM4_MAXP_A_MASK		0x00FF  /* Mask for Max Power A */
+ #define  SSB_SPROM4_ITSSI_A		0xFF00	/* Mask for path 1 itssi_a */
+ #define  SSB_SPROM4_ITSSI_A_SHIFT	8
+-#define SSB_SPROM4_GPIOA		0x1056	/* Gen. Purpose IO # 0 and 1 */
+-#define  SSB_SPROM4_GPIOA_P0		0x00FF	/* Pin 0 */
+-#define  SSB_SPROM4_GPIOA_P1		0xFF00	/* Pin 1 */
+-#define  SSB_SPROM4_GPIOA_P1_SHIFT	8
+-#define SSB_SPROM4_GPIOB		0x1058	/* Gen. Purpose IO # 2 and 3 */
+-#define  SSB_SPROM4_GPIOB_P2		0x00FF	/* Pin 2 */
+-#define  SSB_SPROM4_GPIOB_P3		0xFF00	/* Pin 3 */
+-#define  SSB_SPROM4_GPIOB_P3_SHIFT	8
+-#define SSB_SPROM4_PA0B0		0x1082	/* The paXbY locations are */
+-#define SSB_SPROM4_PA0B1		0x1084	/*   only guesses */
+-#define SSB_SPROM4_PA0B2		0x1086
+-#define SSB_SPROM4_PA1B0		0x108E
+-#define SSB_SPROM4_PA1B1		0x1090
+-#define SSB_SPROM4_PA1B2		0x1092
++#define SSB_SPROM4_PA0B0		0x0082	/* The paXbY locations are */
++#define SSB_SPROM4_PA0B1		0x0084	/*   only guesses */
++#define SSB_SPROM4_PA0B2		0x0086
++#define SSB_SPROM4_PA1B0		0x008E
++#define SSB_SPROM4_PA1B1		0x0090
++#define SSB_SPROM4_PA1B2		0x0092
+ 
+ /* SPROM Revision 5 (inherits most data from rev 4) */
+-#define SSB_SPROM5_BFLLO		0x104A	/* Boardflags (low 16 bits) */
+-#define SSB_SPROM5_BFLHI		0x104C  /* Board Flags Hi */
+-#define SSB_SPROM5_IL0MAC		0x1052	/* 6 byte MAC address for a/b/g/n */
+-#define SSB_SPROM5_CCODE		0x1044	/* Country Code (2 bytes) */
+-#define SSB_SPROM5_GPIOA		0x1076	/* Gen. Purpose IO # 0 and 1 */
++#define SSB_SPROM5_CCODE		0x0044	/* Country Code (2 bytes) */
++#define SSB_SPROM5_BFLLO		0x004A	/* Boardflags (low 16 bits) */
++#define SSB_SPROM5_BFLHI		0x004C  /* Board Flags Hi */
++#define SSB_SPROM5_IL0MAC		0x0052	/* 6 byte MAC address for a/b/g/n */
++#define SSB_SPROM5_GPIOA		0x0076	/* Gen. Purpose IO # 0 and 1 */
+ #define  SSB_SPROM5_GPIOA_P0		0x00FF	/* Pin 0 */
+ #define  SSB_SPROM5_GPIOA_P1		0xFF00	/* Pin 1 */
+ #define  SSB_SPROM5_GPIOA_P1_SHIFT	8
+-#define SSB_SPROM5_GPIOB		0x1078	/* Gen. Purpose IO # 2 and 3 */
++#define SSB_SPROM5_GPIOB		0x0078	/* Gen. Purpose IO # 2 and 3 */
+ #define  SSB_SPROM5_GPIOB_P2		0x00FF	/* Pin 2 */
+ #define  SSB_SPROM5_GPIOB_P3		0xFF00	/* Pin 3 */
  #define  SSB_SPROM5_GPIOB_P3_SHIFT	8
  
  /* SPROM Revision 8 */
 -#define SSB_SPROM8_BFLLO		0x1084	/* Boardflags (low 16 bits) */
 -#define SSB_SPROM8_BFLHI		0x1086	/* Boardflags Hi */
-+#define SSB_SPROM8_BOARDREV		0x1082	/* Board revision */
-+#define SSB_SPROM8_BFLLO		0x1084	/* Board flags (bits 0-15) */
-+#define SSB_SPROM8_BFLHI		0x1086	/* Board flags (bits 16-31) */
-+#define SSB_SPROM8_BFL2LO		0x1088	/* Board flags (bits 32-47) */
-+#define SSB_SPROM8_BFL2HI		0x108A	/* Board flags (bits 48-63) */
- #define SSB_SPROM8_IL0MAC		0x108C	/* 6 byte MAC address */
- #define SSB_SPROM8_CCODE		0x1092	/* 2 byte country code */
- #define SSB_SPROM8_ANTAVAIL		0x109C  /* Antenna available bitfields*/
-@@ -354,14 +357,63 @@
- #define  SSB_SPROM8_GPIOB_P2		0x00FF	/* Pin 2 */
- #define  SSB_SPROM8_GPIOB_P3		0xFF00	/* Pin 3 */
- #define  SSB_SPROM8_GPIOB_P3_SHIFT	8
+-#define SSB_SPROM8_IL0MAC		0x108C	/* 6 byte MAC address */
+-#define SSB_SPROM8_CCODE		0x1092	/* 2 byte country code */
+-#define SSB_SPROM8_ANTAVAIL		0x109C  /* Antenna available bitfields*/
+-#define SSB_SPROM8_ANTAVAIL_A		0xFF00	/* A-PHY bitfield */
+-#define SSB_SPROM8_ANTAVAIL_A_SHIFT	8
+-#define SSB_SPROM8_ANTAVAIL_BG		0x00FF	/* B-PHY and G-PHY bitfield */
+-#define SSB_SPROM8_ANTAVAIL_BG_SHIFT	0
+-#define SSB_SPROM8_AGAIN01		0x109E	/* Antenna Gain (in dBm Q5.2) */
++#define SSB_SPROM8_BOARDREV		0x0082	/* Board revision */
++#define SSB_SPROM8_BFLLO		0x0084	/* Board flags (bits 0-15) */
++#define SSB_SPROM8_BFLHI		0x0086	/* Board flags (bits 16-31) */
++#define SSB_SPROM8_BFL2LO		0x0088	/* Board flags (bits 32-47) */
++#define SSB_SPROM8_BFL2HI		0x008A	/* Board flags (bits 48-63) */
++#define SSB_SPROM8_IL0MAC		0x008C	/* 6 byte MAC address */
++#define SSB_SPROM8_CCODE		0x0092	/* 2 byte country code */
++#define SSB_SPROM8_GPIOA		0x0096	/*Gen. Purpose IO # 0 and 1 */
++#define  SSB_SPROM8_GPIOA_P0		0x00FF	/* Pin 0 */
++#define  SSB_SPROM8_GPIOA_P1		0xFF00	/* Pin 1 */
++#define  SSB_SPROM8_GPIOA_P1_SHIFT	8
++#define SSB_SPROM8_GPIOB		0x0098	/* Gen. Purpose IO # 2 and 3 */
++#define  SSB_SPROM8_GPIOB_P2		0x00FF	/* Pin 2 */
++#define  SSB_SPROM8_GPIOB_P3		0xFF00	/* Pin 3 */
++#define  SSB_SPROM8_GPIOB_P3_SHIFT	8
++#define SSB_SPROM8_ANTAVAIL		0x009C  /* Antenna available bitfields*/
++#define  SSB_SPROM8_ANTAVAIL_A		0xFF00	/* A-PHY bitfield */
++#define  SSB_SPROM8_ANTAVAIL_A_SHIFT	8
++#define  SSB_SPROM8_ANTAVAIL_BG		0x00FF	/* B-PHY and G-PHY bitfield */
++#define  SSB_SPROM8_ANTAVAIL_BG_SHIFT	0
++#define SSB_SPROM8_AGAIN01		0x009E	/* Antenna Gain (in dBm Q5.2) */
+ #define  SSB_SPROM8_AGAIN0		0x00FF	/* Antenna 0 */
+ #define  SSB_SPROM8_AGAIN0_SHIFT	0
+ #define  SSB_SPROM8_AGAIN1		0xFF00	/* Antenna 1 */
+ #define  SSB_SPROM8_AGAIN1_SHIFT	8
+-#define SSB_SPROM8_AGAIN23		0x10A0
++#define SSB_SPROM8_AGAIN23		0x00A0
+ #define  SSB_SPROM8_AGAIN2		0x00FF	/* Antenna 2 */
+ #define  SSB_SPROM8_AGAIN2_SHIFT	0
+ #define  SSB_SPROM8_AGAIN3		0xFF00	/* Antenna 3 */
+ #define  SSB_SPROM8_AGAIN3_SHIFT	8
+-#define SSB_SPROM8_GPIOA		0x1096	/*Gen. Purpose IO # 0 and 1 */
+-#define  SSB_SPROM8_GPIOA_P0		0x00FF	/* Pin 0 */
+-#define  SSB_SPROM8_GPIOA_P1		0xFF00	/* Pin 1 */
+-#define  SSB_SPROM8_GPIOA_P1_SHIFT	8
+-#define SSB_SPROM8_GPIOB		0x1098	/* Gen. Purpose IO # 2 and 3 */
+-#define  SSB_SPROM8_GPIOB_P2		0x00FF	/* Pin 2 */
+-#define  SSB_SPROM8_GPIOB_P3		0xFF00	/* Pin 3 */
+-#define  SSB_SPROM8_GPIOB_P3_SHIFT	8
 -#define SSB_SPROM8_MAXP_BG		0x10C0  /* Max Power BG in path 1 */
 -#define  SSB_SPROM8_MAXP_BG_MASK	0x00FF  /* Mask for Max Power BG */
-+#define SSB_SPROM8_RSSIPARM2G		0x10A4	/* RSSI params for 2GHz */
++#define SSB_SPROM8_RSSIPARM2G		0x00A4	/* RSSI params for 2GHz */
 +#define  SSB_SPROM8_RSSISMF2G		0x000F
 +#define  SSB_SPROM8_RSSISMC2G		0x00F0
 +#define  SSB_SPROM8_RSSISMC2G_SHIFT	4
@@ -464,7 +1088,7 @@
 +#define  SSB_SPROM8_RSSISAV2G_SHIFT	8
 +#define  SSB_SPROM8_BXA2G		0x1800
 +#define  SSB_SPROM8_BXA2G_SHIFT		11
-+#define SSB_SPROM8_RSSIPARM5G		0x10A6	/* RSSI params for 5GHz */
++#define SSB_SPROM8_RSSIPARM5G		0x00A6	/* RSSI params for 5GHz */
 +#define  SSB_SPROM8_RSSISMF5G		0x000F
 +#define  SSB_SPROM8_RSSISMC5G		0x00F0
 +#define  SSB_SPROM8_RSSISMC5G_SHIFT	4
@@ -472,64 +1096,75 @@
 +#define  SSB_SPROM8_RSSISAV5G_SHIFT	8
 +#define  SSB_SPROM8_BXA5G		0x1800
 +#define  SSB_SPROM8_BXA5G_SHIFT		11
-+#define SSB_SPROM8_TRI25G		0x10A8	/* TX isolation 2.4&5.3GHz */
++#define SSB_SPROM8_TRI25G		0x00A8	/* TX isolation 2.4&5.3GHz */
 +#define  SSB_SPROM8_TRI2G		0x00FF	/* TX isolation 2.4GHz */
 +#define  SSB_SPROM8_TRI5G		0xFF00	/* TX isolation 5.3GHz */
 +#define  SSB_SPROM8_TRI5G_SHIFT		8
-+#define SSB_SPROM8_TRI5GHL		0x10AA	/* TX isolation 5.2/5.8GHz */
++#define SSB_SPROM8_TRI5GHL		0x00AA	/* TX isolation 5.2/5.8GHz */
 +#define  SSB_SPROM8_TRI5GL		0x00FF	/* TX isolation 5.2GHz */
 +#define  SSB_SPROM8_TRI5GH		0xFF00	/* TX isolation 5.8GHz */
 +#define  SSB_SPROM8_TRI5GH_SHIFT	8
-+#define SSB_SPROM8_RXPO			0x10AC  /* RX power offsets */
++#define SSB_SPROM8_RXPO			0x00AC  /* RX power offsets */
 +#define  SSB_SPROM8_RXPO2G		0x00FF	/* 2GHz RX power offset */
 +#define  SSB_SPROM8_RXPO5G		0xFF00	/* 5GHz RX power offset */
 +#define  SSB_SPROM8_RXPO5G_SHIFT	8
-+#define SSB_SPROM8_MAXP_BG		0x10C0  /* Max Power 2GHz in path 1 */
++#define SSB_SPROM8_MAXP_BG		0x00C0  /* Max Power 2GHz in path 1 */
 +#define  SSB_SPROM8_MAXP_BG_MASK	0x00FF  /* Mask for Max Power 2GHz */
  #define  SSB_SPROM8_ITSSI_BG		0xFF00	/* Mask for path 1 itssi_bg */
  #define  SSB_SPROM8_ITSSI_BG_SHIFT	8
 -#define SSB_SPROM8_MAXP_A		0x10C8  /* Max Power A in path 1 */
 -#define  SSB_SPROM8_MAXP_A_MASK		0x00FF  /* Mask for Max Power A */
-+#define SSB_SPROM8_PA0B0		0x10C2	/* 2GHz power amp settings */
-+#define SSB_SPROM8_PA0B1		0x10C4
-+#define SSB_SPROM8_PA0B2		0x10C6
-+#define SSB_SPROM8_MAXP_A		0x10C8  /* Max Power 5.3GHz */
++#define SSB_SPROM8_PA0B0		0x00C2	/* 2GHz power amp settings */
++#define SSB_SPROM8_PA0B1		0x00C4
++#define SSB_SPROM8_PA0B2		0x00C6
++#define SSB_SPROM8_MAXP_A		0x00C8  /* Max Power 5.3GHz */
 +#define  SSB_SPROM8_MAXP_A_MASK		0x00FF  /* Mask for Max Power 5.3GHz */
  #define  SSB_SPROM8_ITSSI_A		0xFF00	/* Mask for path 1 itssi_a */
  #define  SSB_SPROM8_ITSSI_A_SHIFT	8
-+#define SSB_SPROM8_MAXP_AHL		0x10CA  /* Max Power 5.2/5.8GHz */
++#define SSB_SPROM8_MAXP_AHL		0x00CA  /* Max Power 5.2/5.8GHz */
 +#define  SSB_SPROM8_MAXP_AH_MASK	0x00FF  /* Mask for Max Power 5.8GHz */
 +#define  SSB_SPROM8_MAXP_AL_MASK	0xFF00  /* Mask for Max Power 5.2GHz */
 +#define  SSB_SPROM8_MAXP_AL_SHIFT	8
-+#define SSB_SPROM8_PA1B0		0x10CC	/* 5.3GHz power amp settings */
-+#define SSB_SPROM8_PA1B1		0x10CE
-+#define SSB_SPROM8_PA1B2		0x10D0
-+#define SSB_SPROM8_PA1LOB0		0x10D2	/* 5.2GHz power amp settings */
-+#define SSB_SPROM8_PA1LOB1		0x10D4
-+#define SSB_SPROM8_PA1LOB2		0x10D6
-+#define SSB_SPROM8_PA1HIB0		0x10D8	/* 5.8GHz power amp settings */
-+#define SSB_SPROM8_PA1HIB1		0x10DA
-+#define SSB_SPROM8_PA1HIB2		0x10DC
-+#define SSB_SPROM8_CCK2GPO		0x1140	/* CCK power offset */
-+#define SSB_SPROM8_OFDM2GPO		0x1142	/* 2.4GHz OFDM power offset */
-+#define SSB_SPROM8_OFDM5GPO		0x1146	/* 5.3GHz OFDM power offset */
-+#define SSB_SPROM8_OFDM5GLPO		0x114A	/* 5.2GHz OFDM power offset */
-+#define SSB_SPROM8_OFDM5GHPO		0x114E	/* 5.8GHz OFDM power offset */
++#define SSB_SPROM8_PA1B0		0x00CC	/* 5.3GHz power amp settings */
++#define SSB_SPROM8_PA1B1		0x00CE
++#define SSB_SPROM8_PA1B2		0x00D0
++#define SSB_SPROM8_PA1LOB0		0x00D2	/* 5.2GHz power amp settings */
++#define SSB_SPROM8_PA1LOB1		0x00D4
++#define SSB_SPROM8_PA1LOB2		0x00D6
++#define SSB_SPROM8_PA1HIB0		0x00D8	/* 5.8GHz power amp settings */
++#define SSB_SPROM8_PA1HIB1		0x00DA
++#define SSB_SPROM8_PA1HIB2		0x00DC
++#define SSB_SPROM8_CCK2GPO		0x0140	/* CCK power offset */
++#define SSB_SPROM8_OFDM2GPO		0x0142	/* 2.4GHz OFDM power offset */
++#define SSB_SPROM8_OFDM5GPO		0x0146	/* 5.3GHz OFDM power offset */
++#define SSB_SPROM8_OFDM5GLPO		0x014A	/* 5.2GHz OFDM power offset */
++#define SSB_SPROM8_OFDM5GHPO		0x014E	/* 5.8GHz OFDM power offset */
  
  /* Values for SSB_SPROM1_BINF_CCODE */
  enum {
 --- a/drivers/ssb/scan.c
 +++ b/drivers/ssb/scan.c
-@@ -175,6 +175,8 @@ static u32 scan_read32(struct ssb_bus *b
+@@ -162,6 +162,8 @@ static u8 chipid_to_nrcores(u16 chipid)
+ static u32 scan_read32(struct ssb_bus *bus, u8 current_coreidx,
+ 		       u16 offset)
+ {
++	u32 lo, hi;
++
+ 	switch (bus->bustype) {
+ 	case SSB_BUSTYPE_SSB:
+ 		offset += current_coreidx * SSB_CORE_SIZE;
+@@ -174,6 +176,10 @@ static u32 scan_read32(struct ssb_bus *b
+ 			offset -= 0x800;
  		} else
  			ssb_pcmcia_switch_segment(bus, 0);
- 		break;
++		lo = readw(bus->mmio + offset);
++		hi = readw(bus->mmio + offset + 2);
++		return lo | (hi << 16);
 +	default:
-+		break;
+ 		break;
  	}
  	return readl(bus->mmio + offset);
- }
-@@ -188,6 +190,8 @@ static int scan_switchcore(struct ssb_bu
+@@ -188,6 +194,8 @@ static int scan_switchcore(struct ssb_bu
  		return ssb_pci_switch_coreidx(bus, coreidx);
  	case SSB_BUSTYPE_PCMCIA:
  		return ssb_pcmcia_switch_coreidx(bus, coreidx);
@@ -538,7 +1173,7 @@
  	}
  	return 0;
  }
-@@ -206,6 +210,8 @@ void ssb_iounmap(struct ssb_bus *bus)
+@@ -206,6 +214,8 @@ void ssb_iounmap(struct ssb_bus *bus)
  		SSB_BUG_ON(1); /* Can't reach this code. */
  #endif
  		break;
@@ -547,7 +1182,7 @@
  	}
  	bus->mmio = NULL;
  	bus->mapped_device = NULL;
-@@ -230,6 +236,8 @@ static void __iomem *ssb_ioremap(struct 
+@@ -230,6 +240,8 @@ static void __iomem *ssb_ioremap(struct 
  		SSB_BUG_ON(1); /* Can't reach this code. */
  #endif
  		break;
@@ -556,3 +1191,327 @@
  	}
  
  	return mmio;
+@@ -339,7 +351,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
+ 		dev->bus = bus;
+ 		dev->ops = bus->ops;
+ 
+-		ssb_dprintk(KERN_INFO PFX
++		printk(KERN_DEBUG PFX
+ 			    "Core %d found: %s "
+ 			    "(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n",
+ 			    i, ssb_core_name(dev->id.coreid),
+--- a/drivers/ssb/driver_chipcommon.c
++++ b/drivers/ssb/driver_chipcommon.c
+@@ -233,6 +233,8 @@ void ssb_chipcommon_init(struct ssb_chip
+ {
+ 	if (!cc->dev)
+ 		return; /* We don't have a ChipCommon */
++	if (cc->dev->id.revision >= 11)
++		cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
+ 	ssb_pmu_init(cc);
+ 	chipco_powercontrol_init(cc);
+ 	ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
+@@ -370,6 +372,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c
+ {
+ 	return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
+ }
++EXPORT_SYMBOL(ssb_chipco_gpio_control);
+ 
+ u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
+ {
+--- a/drivers/ssb/driver_mipscore.c
++++ b/drivers/ssb/driver_mipscore.c
+@@ -49,29 +49,54 @@ static const u32 ipsflag_irq_shift[] = {
+ 
+ static inline u32 ssb_irqflag(struct ssb_device *dev)
+ {
+-	return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
++	u32 tpsflag = ssb_read32(dev, SSB_TPSFLAG);
++	if (tpsflag)
++		return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
++	else
++		/* not irq supported */
++		return 0x3f;
++}
++
++static struct ssb_device *find_device(struct ssb_device *rdev, int irqflag)
++{
++	struct ssb_bus *bus = rdev->bus;
++	int i;
++	for (i = 0; i < bus->nr_devices; i++) {
++		struct ssb_device *dev;
++		dev = &(bus->devices[i]);
++		if (ssb_irqflag(dev) == irqflag)
++			return dev;
++	}
++	return NULL;
+ }
+ 
+ /* Get the MIPS IRQ assignment for a specified device.
+  * If unassigned, 0 is returned.
++ * If disabled, 5 is returned.
++ * If not supported, 6 is returned.
+  */
+ unsigned int ssb_mips_irq(struct ssb_device *dev)
+ {
+ 	struct ssb_bus *bus = dev->bus;
++	struct ssb_device *mdev = bus->mipscore.dev;
+ 	u32 irqflag;
+ 	u32 ipsflag;
+ 	u32 tmp;
+ 	unsigned int irq;
+ 
+ 	irqflag = ssb_irqflag(dev);
++	if (irqflag == 0x3f)
++		return 6;
+ 	ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG);
+ 	for (irq = 1; irq <= 4; irq++) {
+ 		tmp = ((ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]);
+ 		if (tmp == irqflag)
+ 			break;
+ 	}
+-	if (irq	== 5)
+-		irq = 0;
++	if (irq	== 5) {
++		if ((1 << irqflag) & ssb_read32(mdev, SSB_INTVEC))
++			irq = 0;
++	}
+ 
+ 	return irq;
+ }
+@@ -97,25 +122,56 @@ static void set_irq(struct ssb_device *d
+ 	struct ssb_device *mdev = bus->mipscore.dev;
+ 	u32 irqflag = ssb_irqflag(dev);
+ 
++	BUG_ON(oldirq == 6);
++
+ 	dev->irq = irq + 2;
+ 
+-	ssb_dprintk(KERN_INFO PFX
+-		    "set_irq: core 0x%04x, irq %d => %d\n",
+-		    dev->id.coreid, oldirq, irq);
+ 	/* clear the old irq */
+ 	if (oldirq == 0)
+ 		ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
+-	else
++	else if (oldirq != 5)
+ 		clear_irq(bus, oldirq);
+ 
+ 	/* assign the new one */
+ 	if (irq == 0) {
+ 		ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) | ssb_read32(mdev, SSB_INTVEC)));
+ 	} else {
++		u32 ipsflag = ssb_read32(mdev, SSB_IPSFLAG);
++		if ((ipsflag & ipsflag_irq_mask[irq]) != ipsflag_irq_mask[irq]) {
++			u32 oldipsflag = (ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq];
++			struct ssb_device *olddev = find_device(dev, oldipsflag);
++			if (olddev)
++				set_irq(olddev, 0);
++		}
+ 		irqflag <<= ipsflag_irq_shift[irq];
+-		irqflag |= (ssb_read32(mdev, SSB_IPSFLAG) & ~ipsflag_irq_mask[irq]);
++		irqflag |= (ipsflag & ~ipsflag_irq_mask[irq]);
+ 		ssb_write32(mdev, SSB_IPSFLAG, irqflag);
+ 	}
++	ssb_dprintk(KERN_INFO PFX
++		    "set_irq: core 0x%04x, irq %d => %d\n",
++		    dev->id.coreid, oldirq+2, irq+2);
++}
++
++static void print_irq(struct ssb_device *dev, unsigned int irq)
++{
++	int i;
++	static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
++	ssb_dprintk(KERN_INFO PFX
++		"core 0x%04x, irq :", dev->id.coreid);
++	for (i = 0; i <= 6; i++) {
++		ssb_dprintk(" %s%s", irq_name[i], i==irq?"*":" ");
++	}
++	ssb_dprintk("\n");
++}
++
++static void dump_irq(struct ssb_bus *bus)
++{
++	int i;
++	for (i = 0; i < bus->nr_devices; i++) {
++		struct ssb_device *dev;
++		dev = &(bus->devices[i]);
++		print_irq(dev, ssb_mips_irq(dev));
++	}
+ }
+ 
+ static void ssb_mips_serial_init(struct ssb_mipscore *mcore)
+@@ -197,17 +253,23 @@ void ssb_mipscore_init(struct ssb_mipsco
+ 
+ 	/* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
+ 	for (irq = 2, i = 0; i < bus->nr_devices; i++) {
++		int mips_irq;
+ 		dev = &(bus->devices[i]);
+-		dev->irq = ssb_mips_irq(dev) + 2;
++		mips_irq = ssb_mips_irq(dev);
++		if (mips_irq > 4)
++			dev->irq = 0;
++		else
++			dev->irq = mips_irq + 2;
++		if (dev->irq > 5)
++			continue;
+ 		switch (dev->id.coreid) {
+ 		case SSB_DEV_USB11_HOST:
+ 			/* shouldn't need a separate irq line for non-4710, most of them have a proper
+ 			 * external usb controller on the pci */
+ 			if ((bus->chip_id == 0x4710) && (irq <= 4)) {
+ 				set_irq(dev, irq++);
+-				break;
+ 			}
+-			/* fallthrough */
++			break;
+ 		case SSB_DEV_PCI:
+ 		case SSB_DEV_ETHERNET:
+ 		case SSB_DEV_ETHERNET_GBIT:
+@@ -218,8 +280,14 @@ void ssb_mipscore_init(struct ssb_mipsco
+ 				set_irq(dev, irq++);
+ 				break;
+ 			}
++			/* fallthrough */
++		case SSB_DEV_EXTIF:
++			set_irq(dev, 0);
++			break;
+ 		}
+ 	}
++	ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
++	dump_irq(bus);
+ 
+ 	ssb_mips_serial_init(mcore);
+ 	ssb_mips_flash_detect(mcore);
+--- a/drivers/ssb/sprom.c
++++ b/drivers/ssb/sprom.c
+@@ -13,6 +13,9 @@
+ 
+ #include "ssb_private.h"
+ 
++#include <linux/ctype.h>
++#include <linux/slab.h>
++
+ 
+ static const struct ssb_sprom *fallback_sprom;
+ 
+@@ -33,17 +36,27 @@ static int sprom2hex(const u16 *sprom, c
+ static int hex2sprom(u16 *sprom, const char *dump, size_t len,
+ 		     size_t sprom_size_words)
+ {
+-	char tmp[5] = { 0 };
+-	int cnt = 0;
++	char c, tmp[5] = { 0 };
++	int err, cnt = 0;
+ 	unsigned long parsed;
+ 
+-	if (len < sprom_size_words * 2)
++	/* Strip whitespace at the end. */
++	while (len) {
++		c = dump[len - 1];
++		if (!isspace(c) && c != '\0')
++			break;
++		len--;
++	}
++	/* Length must match exactly. */
++	if (len != sprom_size_words * 4)
+ 		return -EINVAL;
+ 
+ 	while (cnt < sprom_size_words) {
+ 		memcpy(tmp, dump, 4);
+ 		dump += 4;
+-		parsed = simple_strtoul(tmp, NULL, 16);
++		err = strict_strtoul(tmp, 16, &parsed);
++		if (err)
++			return err;
+ 		sprom[cnt++] = swab16((u16)parsed);
+ 	}
+ 
+@@ -90,6 +103,7 @@ ssize_t ssb_attr_sprom_store(struct ssb_
+ 	u16 *sprom;
+ 	int res = 0, err = -ENOMEM;
+ 	size_t sprom_size_words = bus->sprom_size;
++	struct ssb_freeze_context freeze;
+ 
+ 	sprom = kcalloc(bus->sprom_size, sizeof(u16), GFP_KERNEL);
+ 	if (!sprom)
+@@ -111,18 +125,13 @@ ssize_t ssb_attr_sprom_store(struct ssb_
+ 	err = -ERESTARTSYS;
+ 	if (mutex_lock_interruptible(&bus->sprom_mutex))
+ 		goto out_kfree;
+-	err = ssb_devices_freeze(bus);
+-	if (err == -EOPNOTSUPP) {
+-		ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze devices. "
+-			   "No suspend support. Is CONFIG_PM enabled?\n");
+-		goto out_unlock;
+-	}
++	err = ssb_devices_freeze(bus, &freeze);
+ 	if (err) {
+ 		ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n");
+ 		goto out_unlock;
+ 	}
+ 	res = sprom_write(bus, sprom);
+-	err = ssb_devices_thaw(bus);
++	err = ssb_devices_thaw(&freeze);
+ 	if (err)
+ 		ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n");
+ out_unlock:
+@@ -167,3 +176,17 @@ const struct ssb_sprom *ssb_get_fallback
+ {
+ 	return fallback_sprom;
+ }
++
++/* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
++bool ssb_is_sprom_available(struct ssb_bus *bus)
++{
++	/* status register only exists on chipcomon rev >= 11 and we need check
++	   for >= 31 only */
++	/* this routine differs from specs as we do not access SPROM directly
++	   on PCMCIA */
++	if (bus->bustype == SSB_BUSTYPE_PCI &&
++	    bus->chipco.dev->id.revision >= 31)
++		return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
++
++	return true;
++}
+--- a/drivers/ssb/ssb_private.h
++++ b/drivers/ssb/ssb_private.h
+@@ -136,19 +136,27 @@ extern const struct ssb_sprom *ssb_get_f
+ 
+ /* core.c */
+ extern u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m);
+-extern int ssb_devices_freeze(struct ssb_bus *bus);
+-extern int ssb_devices_thaw(struct ssb_bus *bus);
+ extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev);
+ int ssb_for_each_bus_call(unsigned long data,
+ 			  int (*func)(struct ssb_bus *bus, unsigned long data));
+ extern struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev);
+ 
++struct ssb_freeze_context {
++	/* Pointer to the bus */
++	struct ssb_bus *bus;
++	/* Boolean list to indicate whether a device is frozen on this bus. */
++	bool device_frozen[SSB_MAX_NR_CORES];
++};
++extern int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx);
++extern int ssb_devices_thaw(struct ssb_freeze_context *ctx);
++
++
+ 
+ /* b43_pci_bridge.c */
+ #ifdef CONFIG_SSB_B43_PCI_BRIDGE
+ extern int __init b43_pci_ssb_bridge_init(void);
+ extern void __exit b43_pci_ssb_bridge_exit(void);
+-#else /* CONFIG_SSB_B43_PCI_BRIDGR */
++#else /* CONFIG_SSB_B43_PCI_BRIDGE */
+ static inline int b43_pci_ssb_bridge_init(void)
+ {
+ 	return 0;
+@@ -156,6 +164,6 @@ static inline int b43_pci_ssb_bridge_ini
+ static inline void b43_pci_ssb_bridge_exit(void)
+ {
+ }
+-#endif /* CONFIG_SSB_PCIHOST */
++#endif /* CONFIG_SSB_B43_PCI_BRIDGE */
+ 
+ #endif /* LINUX_SSB_PRIVATE_H_ */
diff --git a/target/linux/generic-2.6/patches-2.6.32/975-ssb_update.patch b/target/linux/generic-2.6/patches-2.6.32/975-ssb_update.patch
new file mode 100644
index 0000000000..f48c58052f
--- /dev/null
+++ b/target/linux/generic-2.6/patches-2.6.32/975-ssb_update.patch
@@ -0,0 +1,1231 @@
+--- a/drivers/ssb/driver_chipcommon.c
++++ b/drivers/ssb/driver_chipcommon.c
+@@ -233,6 +233,8 @@ void ssb_chipcommon_init(struct ssb_chip
+ {
+ 	if (!cc->dev)
+ 		return; /* We don't have a ChipCommon */
++	if (cc->dev->id.revision >= 11)
++		cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
+ 	ssb_pmu_init(cc);
+ 	chipco_powercontrol_init(cc);
+ 	ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
+@@ -370,6 +372,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c
+ {
+ 	return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
+ }
++EXPORT_SYMBOL(ssb_chipco_gpio_control);
+ 
+ u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
+ {
+--- a/drivers/ssb/driver_chipcommon_pmu.c
++++ b/drivers/ssb/driver_chipcommon_pmu.c
+@@ -332,6 +332,12 @@ static void ssb_pmu_pll_init(struct ssb_
+ 	case 0x5354:
+ 		ssb_pmu0_pllinit_r0(cc, crystalfreq);
+ 		break;
++	case 0x4322:
++		if (cc->pmu.rev == 2) {
++			chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, 0x0000000A);
++			chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
++		}
++		break;
+ 	default:
+ 		ssb_printk(KERN_ERR PFX
+ 			   "ERROR: PLL init unknown for device %04X\n",
+@@ -417,6 +423,7 @@ static void ssb_pmu_resources_init(struc
+ 
+ 	switch (bus->chip_id) {
+ 	case 0x4312:
++	case 0x4322:
+ 		/* We keep the default settings:
+ 		 * min_msk = 0xCBB
+ 		 * max_msk = 0x7FFFF
+--- a/drivers/ssb/driver_gige.c
++++ b/drivers/ssb/driver_gige.c
+@@ -12,6 +12,7 @@
+ #include <linux/ssb/ssb_driver_gige.h>
+ #include <linux/pci.h>
+ #include <linux/pci_regs.h>
++#include <linux/slab.h>
+ 
+ 
+ /*
+--- a/drivers/ssb/driver_mipscore.c
++++ b/drivers/ssb/driver_mipscore.c
+@@ -270,7 +270,6 @@ void ssb_mipscore_init(struct ssb_mipsco
+ 				set_irq(dev, irq++);
+ 			}
+ 			break;
+-			/* fallthrough */
+ 		case SSB_DEV_PCI:
+ 		case SSB_DEV_ETHERNET:
+ 		case SSB_DEV_ETHERNET_GBIT:
+@@ -281,6 +280,10 @@ void ssb_mipscore_init(struct ssb_mipsco
+ 				set_irq(dev, irq++);
+ 				break;
+ 			}
++			/* fallthrough */
++		case SSB_DEV_EXTIF:
++			set_irq(dev, 0);
++			break;
+ 		}
+ 	}
+ 	ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
+--- a/drivers/ssb/driver_pcicore.c
++++ b/drivers/ssb/driver_pcicore.c
+@@ -246,20 +246,12 @@ static struct pci_controller ssb_pcicore
+ 	.pci_ops	= &ssb_pcicore_pciops,
+ 	.io_resource	= &ssb_pcicore_io_resource,
+ 	.mem_resource	= &ssb_pcicore_mem_resource,
+-	.mem_offset	= 0x24000000,
+ };
+ 
+-static u32 ssb_pcicore_pcibus_iobase = 0x100;
+-static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
+-
+ /* This function is called when doing a pci_enable_device().
+  * We must first check if the device is a device on the PCI-core bridge. */
+ int ssb_pcicore_plat_dev_init(struct pci_dev *d)
+ {
+-	struct resource *res;
+-	int pos, size;
+-	u32 *base;
+-
+ 	if (d->bus->ops != &ssb_pcicore_pciops) {
+ 		/* This is not a device on the PCI-core bridge. */
+ 		return -ENODEV;
+@@ -268,27 +260,6 @@ int ssb_pcicore_plat_dev_init(struct pci
+ 	ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
+ 		   pci_name(d));
+ 
+-	/* Fix up resource bases */
+-	for (pos = 0; pos < 6; pos++) {
+-		res = &d->resource[pos];
+-		if (res->flags & IORESOURCE_IO)
+-			base = &ssb_pcicore_pcibus_iobase;
+-		else
+-			base = &ssb_pcicore_pcibus_membase;
+-		res->flags |= IORESOURCE_PCI_FIXED;
+-		if (res->end) {
+-			size = res->end - res->start + 1;
+-			if (*base & (size - 1))
+-				*base = (*base + size) & ~(size - 1);
+-			res->start = *base;
+-			res->end = res->start + size - 1;
+-			*base += size;
+-			pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
+-		}
+-		/* Fix up PCI bridge BAR0 only */
+-		if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
+-			break;
+-	}
+ 	/* Fix up interrupt lines */
+ 	d->irq = ssb_mips_irq(extpci_core->dev) + 2;
+ 	pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
+@@ -551,13 +522,13 @@ int ssb_pcicore_dev_irqvecs_enable(struc
+ 	might_sleep_if(pdev->id.coreid != SSB_DEV_PCI);
+ 
+ 	/* Enable interrupts for this device. */
+-	if (bus->host_pci &&
+-	    ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) {
++	if ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE)) {
+ 		u32 coremask;
+ 
+ 		/* Calculate the "coremask" for the device. */
+ 		coremask = (1 << dev->core_index);
+ 
++		SSB_WARN_ON(bus->bustype != SSB_BUSTYPE_PCI);
+ 		err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
+ 		if (err)
+ 			goto out;
+--- a/drivers/ssb/main.c
++++ b/drivers/ssb/main.c
+@@ -18,6 +18,7 @@
+ #include <linux/dma-mapping.h>
+ #include <linux/pci.h>
+ #include <linux/mmc/sdio_func.h>
++#include <linux/slab.h>
+ 
+ #include <pcmcia/cs_types.h>
+ #include <pcmcia/cs.h>
+@@ -140,6 +141,19 @@ static void ssb_device_put(struct ssb_de
+ 		put_device(dev->dev);
+ }
+ 
++static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
++{
++	if (drv)
++		get_driver(&drv->drv);
++	return drv;
++}
++
++static inline void ssb_driver_put(struct ssb_driver *drv)
++{
++	if (drv)
++		put_driver(&drv->drv);
++}
++
+ static int ssb_device_resume(struct device *dev)
+ {
+ 	struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
+@@ -210,90 +224,81 @@ int ssb_bus_suspend(struct ssb_bus *bus)
+ EXPORT_SYMBOL(ssb_bus_suspend);
+ 
+ #ifdef CONFIG_SSB_SPROM
+-int ssb_devices_freeze(struct ssb_bus *bus)
++/** ssb_devices_freeze - Freeze all devices on the bus.
++ *
++ * After freezing no device driver will be handling a device
++ * on this bus anymore. ssb_devices_thaw() must be called after
++ * a successful freeze to reactivate the devices.
++ *
++ * @bus: The bus.
++ * @ctx: Context structure. Pass this to ssb_devices_thaw().
++ */
++int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
+ {
+-	struct ssb_device *dev;
+-	struct ssb_driver *drv;
+-	int err = 0;
+-	int i;
+-	pm_message_t state = PMSG_FREEZE;
++	struct ssb_device *sdev;
++	struct ssb_driver *sdrv;
++	unsigned int i;
++
++	memset(ctx, 0, sizeof(*ctx));
++	ctx->bus = bus;
++	SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
+ 
+-	/* First check that we are capable to freeze all devices. */
+ 	for (i = 0; i < bus->nr_devices; i++) {
+-		dev = &(bus->devices[i]);
+-		if (!dev->dev ||
+-		    !dev->dev->driver ||
+-		    !device_is_registered(dev->dev))
+-			continue;
+-		drv = drv_to_ssb_drv(dev->dev->driver);
+-		if (!drv)
++		sdev = ssb_device_get(&bus->devices[i]);
++
++		if (!sdev->dev || !sdev->dev->driver ||
++		    !device_is_registered(sdev->dev)) {
++			ssb_device_put(sdev);
+ 			continue;
+-		if (!drv->suspend) {
+-			/* Nope, can't suspend this one. */
+-			return -EOPNOTSUPP;
+ 		}
+-	}
+-	/* Now suspend all devices */
+-	for (i = 0; i < bus->nr_devices; i++) {
+-		dev = &(bus->devices[i]);
+-		if (!dev->dev ||
+-		    !dev->dev->driver ||
+-		    !device_is_registered(dev->dev))
++		sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
++		if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
++			ssb_device_put(sdev);
+ 			continue;
+-		drv = drv_to_ssb_drv(dev->dev->driver);
+-		if (!drv)
+-			continue;
+-		err = drv->suspend(dev, state);
+-		if (err) {
+-			ssb_printk(KERN_ERR PFX "Failed to freeze device %s\n",
+-				   dev_name(dev->dev));
+-			goto err_unwind;
+ 		}
++		sdrv->remove(sdev);
++		ctx->device_frozen[i] = 1;
+ 	}
+ 
+ 	return 0;
+-err_unwind:
+-	for (i--; i >= 0; i--) {
+-		dev = &(bus->devices[i]);
+-		if (!dev->dev ||
+-		    !dev->dev->driver ||
+-		    !device_is_registered(dev->dev))
+-			continue;
+-		drv = drv_to_ssb_drv(dev->dev->driver);
+-		if (!drv)
+-			continue;
+-		if (drv->resume)
+-			drv->resume(dev);
+-	}
+-	return err;
+ }
+ 
+-int ssb_devices_thaw(struct ssb_bus *bus)
++/** ssb_devices_thaw - Unfreeze all devices on the bus.
++ *
++ * This will re-attach the device drivers and re-init the devices.
++ *
++ * @ctx: The context structure from ssb_devices_freeze()
++ */
++int ssb_devices_thaw(struct ssb_freeze_context *ctx)
+ {
+-	struct ssb_device *dev;
+-	struct ssb_driver *drv;
+-	int err;
+-	int i;
++	struct ssb_bus *bus = ctx->bus;
++	struct ssb_device *sdev;
++	struct ssb_driver *sdrv;
++	unsigned int i;
++	int err, result = 0;
+ 
+ 	for (i = 0; i < bus->nr_devices; i++) {
+-		dev = &(bus->devices[i]);
+-		if (!dev->dev ||
+-		    !dev->dev->driver ||
+-		    !device_is_registered(dev->dev))
++		if (!ctx->device_frozen[i])
+ 			continue;
+-		drv = drv_to_ssb_drv(dev->dev->driver);
+-		if (!drv)
++		sdev = &bus->devices[i];
++
++		if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver))
+ 			continue;
+-		if (SSB_WARN_ON(!drv->resume))
++		sdrv = drv_to_ssb_drv(sdev->dev->driver);
++		if (SSB_WARN_ON(!sdrv || !sdrv->probe))
+ 			continue;
+-		err = drv->resume(dev);
++
++		err = sdrv->probe(sdev, &sdev->id);
+ 		if (err) {
+ 			ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
+-				   dev_name(dev->dev));
++				   dev_name(sdev->dev));
++			result = err;
+ 		}
++		ssb_driver_put(sdrv);
++		ssb_device_put(sdev);
+ 	}
+ 
+-	return 0;
++	return result;
+ }
+ #endif /* CONFIG_SSB_SPROM */
+ 
+@@ -490,8 +495,7 @@ static int ssb_devices_register(struct s
+ #endif
+ 			break;
+ 		case SSB_BUSTYPE_SDIO:
+-#ifdef CONFIG_SSB_SDIO
+-			sdev->irq = bus->host_sdio->dev.irq;
++#ifdef CONFIG_SSB_SDIOHOST
+ 			dev->parent = &bus->host_sdio->dev;
+ #endif
+ 			break;
+@@ -830,6 +834,9 @@ int ssb_bus_pcibus_register(struct ssb_b
+ 	if (!err) {
+ 		ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
+ 			   "PCI device %s\n", dev_name(&host_pci->dev));
++	} else {
++		ssb_printk(KERN_ERR PFX "Failed to register PCI version"
++			   " of SSB with error %d\n", err);
+ 	}
+ 
+ 	return err;
+--- a/drivers/ssb/pci.c
++++ b/drivers/ssb/pci.c
+@@ -17,6 +17,7 @@
+ 
+ #include <linux/ssb/ssb.h>
+ #include <linux/ssb/ssb_regs.h>
++#include <linux/slab.h>
+ #include <linux/pci.h>
+ #include <linux/delay.h>
+ 
+@@ -167,7 +168,7 @@ err_pci:
+ }
+ 
+ /* Get the word-offset for a SSB_SPROM_XXX define. */
+-#define SPOFF(offset)	(((offset) - SSB_SPROM_BASE) / sizeof(u16))
++#define SPOFF(offset)	((offset) / sizeof(u16))
+ /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
+ #define SPEX16(_outvar, _offset, _mask, _shift)	\
+ 	out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
+@@ -253,7 +254,7 @@ static int sprom_do_read(struct ssb_bus 
+ 	int i;
+ 
+ 	for (i = 0; i < bus->sprom_size; i++)
+-		sprom[i] = ioread16(bus->mmio + SSB_SPROM_BASE + (i * 2));
++		sprom[i] = ioread16(bus->mmio + bus->sprom_offset + (i * 2));
+ 
+ 	return 0;
+ }
+@@ -284,7 +285,7 @@ static int sprom_do_write(struct ssb_bus
+ 			ssb_printk("75%%");
+ 		else if (i % 2)
+ 			ssb_printk(".");
+-		writew(sprom[i], bus->mmio + SSB_SPROM_BASE + (i * 2));
++		writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
+ 		mmiowb();
+ 		msleep(20);
+ 	}
+@@ -620,6 +621,14 @@ static int ssb_pci_sprom_get(struct ssb_
+ 	int err = -ENOMEM;
+ 	u16 *buf;
+ 
++	if (!ssb_is_sprom_available(bus)) {
++		ssb_printk(KERN_ERR PFX "No SPROM available!\n");
++		return -ENODEV;
++	}
++
++	bus->sprom_offset = (bus->chipco.dev->id.revision < 31) ?
++		SSB_SPROM_BASE1 : SSB_SPROM_BASE31;
++
+ 	buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
+ 	if (!buf)
+ 		goto out;
+--- a/drivers/ssb/pcihost_wrapper.c
++++ b/drivers/ssb/pcihost_wrapper.c
+@@ -12,6 +12,7 @@
+  */
+ 
+ #include <linux/pci.h>
++#include <linux/slab.h>
+ #include <linux/ssb/ssb.h>
+ 
+ 
+--- a/drivers/ssb/pcmcia.c
++++ b/drivers/ssb/pcmcia.c
+@@ -617,136 +617,140 @@ static int ssb_pcmcia_sprom_check_crc(co
+ 	}						\
+   } while (0)
+ 
+-int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
+-			      struct ssb_init_invariants *iv)
++static int ssb_pcmcia_get_mac(struct pcmcia_device *p_dev,
++			tuple_t *tuple,
++			void *priv)
++{
++	struct ssb_sprom *sprom = priv;
++
++	if (tuple->TupleData[0] != CISTPL_FUNCE_LAN_NODE_ID)
++		return -EINVAL;
++	if (tuple->TupleDataLen != ETH_ALEN + 2)
++		return -EINVAL;
++	if (tuple->TupleData[1] != ETH_ALEN)
++		return -EINVAL;
++	memcpy(sprom->il0mac, &tuple->TupleData[2], ETH_ALEN);
++	return 0;
++};
++
++static int ssb_pcmcia_do_get_invariants(struct pcmcia_device *p_dev,
++					tuple_t *tuple,
++					void *priv)
+ {
+-	tuple_t tuple;
+-	int res;
+-	unsigned char buf[32];
++	struct ssb_init_invariants *iv = priv;
+ 	struct ssb_sprom *sprom = &iv->sprom;
+ 	struct ssb_boardinfo *bi = &iv->boardinfo;
+ 	const char *error_description;
+ 
++	GOTO_ERROR_ON(tuple->TupleDataLen < 1, "VEN tpl < 1");
++	switch (tuple->TupleData[0]) {
++	case SSB_PCMCIA_CIS_ID:
++		GOTO_ERROR_ON((tuple->TupleDataLen != 5) &&
++			      (tuple->TupleDataLen != 7),
++			      "id tpl size");
++		bi->vendor = tuple->TupleData[1] |
++			((u16)tuple->TupleData[2] << 8);
++		break;
++	case SSB_PCMCIA_CIS_BOARDREV:
++		GOTO_ERROR_ON(tuple->TupleDataLen != 2,
++			"boardrev tpl size");
++		sprom->board_rev = tuple->TupleData[1];
++		break;
++	case SSB_PCMCIA_CIS_PA:
++		GOTO_ERROR_ON((tuple->TupleDataLen != 9) &&
++			(tuple->TupleDataLen != 10),
++			"pa tpl size");
++		sprom->pa0b0 = tuple->TupleData[1] |
++			((u16)tuple->TupleData[2] << 8);
++		sprom->pa0b1 = tuple->TupleData[3] |
++			((u16)tuple->TupleData[4] << 8);
++		sprom->pa0b2 = tuple->TupleData[5] |
++			((u16)tuple->TupleData[6] << 8);
++		sprom->itssi_a = tuple->TupleData[7];
++		sprom->itssi_bg = tuple->TupleData[7];
++		sprom->maxpwr_a = tuple->TupleData[8];
++		sprom->maxpwr_bg = tuple->TupleData[8];
++		break;
++	case SSB_PCMCIA_CIS_OEMNAME:
++		/* We ignore this. */
++		break;
++	case SSB_PCMCIA_CIS_CCODE:
++		GOTO_ERROR_ON(tuple->TupleDataLen != 2,
++			"ccode tpl size");
++		sprom->country_code = tuple->TupleData[1];
++		break;
++	case SSB_PCMCIA_CIS_ANTENNA:
++		GOTO_ERROR_ON(tuple->TupleDataLen != 2,
++			"ant tpl size");
++		sprom->ant_available_a = tuple->TupleData[1];
++		sprom->ant_available_bg = tuple->TupleData[1];
++		break;
++	case SSB_PCMCIA_CIS_ANTGAIN:
++		GOTO_ERROR_ON(tuple->TupleDataLen != 2,
++			"antg tpl size");
++		sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
++		sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
++		sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
++		sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
++		sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
++		sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
++		sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
++		sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
++		break;
++	case SSB_PCMCIA_CIS_BFLAGS:
++		GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
++			(tuple->TupleDataLen != 5),
++			"bfl tpl size");
++		sprom->boardflags_lo = tuple->TupleData[1] |
++			((u16)tuple->TupleData[2] << 8);
++		break;
++	case SSB_PCMCIA_CIS_LEDS:
++		GOTO_ERROR_ON(tuple->TupleDataLen != 5,
++			"leds tpl size");
++		sprom->gpio0 = tuple->TupleData[1];
++		sprom->gpio1 = tuple->TupleData[2];
++		sprom->gpio2 = tuple->TupleData[3];
++		sprom->gpio3 = tuple->TupleData[4];
++		break;
++	}
++	return -ENOSPC; /* continue with next entry */
++
++error:
++	ssb_printk(KERN_ERR PFX
++		   "PCMCIA: Failed to fetch device invariants: %s\n",
++		   error_description);
++	return -ENODEV;
++}
++
++
++int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
++			      struct ssb_init_invariants *iv)
++{
++	struct ssb_sprom *sprom = &iv->sprom;
++	int res;
++
+ 	memset(sprom, 0xFF, sizeof(*sprom));
+ 	sprom->revision = 1;
+ 	sprom->boardflags_lo = 0;
+ 	sprom->boardflags_hi = 0;
+ 
+ 	/* First fetch the MAC address. */
+-	memset(&tuple, 0, sizeof(tuple));
+-	tuple.DesiredTuple = CISTPL_FUNCE;
+-	tuple.TupleData = buf;
+-	tuple.TupleDataMax = sizeof(buf);
+-	res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
+-	GOTO_ERROR_ON(res != 0, "MAC first tpl");
+-	res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
+-	GOTO_ERROR_ON(res != 0, "MAC first tpl data");
+-	while (1) {
+-		GOTO_ERROR_ON(tuple.TupleDataLen < 1, "MAC tpl < 1");
+-		if (tuple.TupleData[0] == CISTPL_FUNCE_LAN_NODE_ID)
+-			break;
+-		res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
+-		GOTO_ERROR_ON(res != 0, "MAC next tpl");
+-		res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
+-		GOTO_ERROR_ON(res != 0, "MAC next tpl data");
++	res = pcmcia_loop_tuple(bus->host_pcmcia, CISTPL_FUNCE,
++				ssb_pcmcia_get_mac, sprom);
++	if (res != 0) {
++		ssb_printk(KERN_ERR PFX
++			"PCMCIA: Failed to fetch MAC address\n");
++		return -ENODEV;
+ 	}
+-	GOTO_ERROR_ON(tuple.TupleDataLen != ETH_ALEN + 2, "MAC tpl size");
+-	memcpy(sprom->il0mac, &tuple.TupleData[2], ETH_ALEN);
+ 
+ 	/* Fetch the vendor specific tuples. */
+-	memset(&tuple, 0, sizeof(tuple));
+-	tuple.DesiredTuple = SSB_PCMCIA_CIS;
+-	tuple.TupleData = buf;
+-	tuple.TupleDataMax = sizeof(buf);
+-	res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
+-	GOTO_ERROR_ON(res != 0, "VEN first tpl");
+-	res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
+-	GOTO_ERROR_ON(res != 0, "VEN first tpl data");
+-	while (1) {
+-		GOTO_ERROR_ON(tuple.TupleDataLen < 1, "VEN tpl < 1");
+-		switch (tuple.TupleData[0]) {
+-		case SSB_PCMCIA_CIS_ID:
+-			GOTO_ERROR_ON((tuple.TupleDataLen != 5) &&
+-				      (tuple.TupleDataLen != 7),
+-				      "id tpl size");
+-			bi->vendor = tuple.TupleData[1] |
+-			       ((u16)tuple.TupleData[2] << 8);
+-			break;
+-		case SSB_PCMCIA_CIS_BOARDREV:
+-			GOTO_ERROR_ON(tuple.TupleDataLen != 2,
+-				      "boardrev tpl size");
+-			sprom->board_rev = tuple.TupleData[1];
+-			break;
+-		case SSB_PCMCIA_CIS_PA:
+-			GOTO_ERROR_ON((tuple.TupleDataLen != 9) &&
+-				      (tuple.TupleDataLen != 10),
+-				      "pa tpl size");
+-			sprom->pa0b0 = tuple.TupleData[1] |
+-				 ((u16)tuple.TupleData[2] << 8);
+-			sprom->pa0b1 = tuple.TupleData[3] |
+-				 ((u16)tuple.TupleData[4] << 8);
+-			sprom->pa0b2 = tuple.TupleData[5] |
+-				 ((u16)tuple.TupleData[6] << 8);
+-			sprom->itssi_a = tuple.TupleData[7];
+-			sprom->itssi_bg = tuple.TupleData[7];
+-			sprom->maxpwr_a = tuple.TupleData[8];
+-			sprom->maxpwr_bg = tuple.TupleData[8];
+-			break;
+-		case SSB_PCMCIA_CIS_OEMNAME:
+-			/* We ignore this. */
+-			break;
+-		case SSB_PCMCIA_CIS_CCODE:
+-			GOTO_ERROR_ON(tuple.TupleDataLen != 2,
+-				      "ccode tpl size");
+-			sprom->country_code = tuple.TupleData[1];
+-			break;
+-		case SSB_PCMCIA_CIS_ANTENNA:
+-			GOTO_ERROR_ON(tuple.TupleDataLen != 2,
+-				      "ant tpl size");
+-			sprom->ant_available_a = tuple.TupleData[1];
+-			sprom->ant_available_bg = tuple.TupleData[1];
+-			break;
+-		case SSB_PCMCIA_CIS_ANTGAIN:
+-			GOTO_ERROR_ON(tuple.TupleDataLen != 2,
+-				      "antg tpl size");
+-			sprom->antenna_gain.ghz24.a0 = tuple.TupleData[1];
+-			sprom->antenna_gain.ghz24.a1 = tuple.TupleData[1];
+-			sprom->antenna_gain.ghz24.a2 = tuple.TupleData[1];
+-			sprom->antenna_gain.ghz24.a3 = tuple.TupleData[1];
+-			sprom->antenna_gain.ghz5.a0 = tuple.TupleData[1];
+-			sprom->antenna_gain.ghz5.a1 = tuple.TupleData[1];
+-			sprom->antenna_gain.ghz5.a2 = tuple.TupleData[1];
+-			sprom->antenna_gain.ghz5.a3 = tuple.TupleData[1];
+-			break;
+-		case SSB_PCMCIA_CIS_BFLAGS:
+-			GOTO_ERROR_ON((tuple.TupleDataLen != 3) &&
+-				      (tuple.TupleDataLen != 5),
+-				      "bfl tpl size");
+-			sprom->boardflags_lo = tuple.TupleData[1] |
+-					 ((u16)tuple.TupleData[2] << 8);
+-			break;
+-		case SSB_PCMCIA_CIS_LEDS:
+-			GOTO_ERROR_ON(tuple.TupleDataLen != 5,
+-				      "leds tpl size");
+-			sprom->gpio0 = tuple.TupleData[1];
+-			sprom->gpio1 = tuple.TupleData[2];
+-			sprom->gpio2 = tuple.TupleData[3];
+-			sprom->gpio3 = tuple.TupleData[4];
+-			break;
+-		}
+-		res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
+-		if (res == -ENOSPC)
+-			break;
+-		GOTO_ERROR_ON(res != 0, "VEN next tpl");
+-		res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
+-		GOTO_ERROR_ON(res != 0, "VEN next tpl data");
+-	}
++	res = pcmcia_loop_tuple(bus->host_pcmcia, SSB_PCMCIA_CIS,
++				ssb_pcmcia_do_get_invariants, sprom);
++	if ((res == 0) || (res == -ENOSPC))
++		return 0;
+ 
+-	return 0;
+-error:
+ 	ssb_printk(KERN_ERR PFX
+-		   "PCMCIA: Failed to fetch device invariants: %s\n",
+-		   error_description);
++			"PCMCIA: Failed to fetch device invariants\n");
+ 	return -ENODEV;
+ }
+ 
+--- a/drivers/ssb/scan.c
++++ b/drivers/ssb/scan.c
+@@ -354,7 +354,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
+ 		dev->bus = bus;
+ 		dev->ops = bus->ops;
+ 
+-		ssb_dprintk(KERN_INFO PFX
++		printk(KERN_DEBUG PFX
+ 			    "Core %d found: %s "
+ 			    "(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n",
+ 			    i, ssb_core_name(dev->id.coreid),
+--- a/drivers/ssb/sprom.c
++++ b/drivers/ssb/sprom.c
+@@ -14,6 +14,7 @@
+ #include "ssb_private.h"
+ 
+ #include <linux/ctype.h>
++#include <linux/slab.h>
+ 
+ 
+ static const struct ssb_sprom *fallback_sprom;
+@@ -102,6 +103,7 @@ ssize_t ssb_attr_sprom_store(struct ssb_
+ 	u16 *sprom;
+ 	int res = 0, err = -ENOMEM;
+ 	size_t sprom_size_words = bus->sprom_size;
++	struct ssb_freeze_context freeze;
+ 
+ 	sprom = kcalloc(bus->sprom_size, sizeof(u16), GFP_KERNEL);
+ 	if (!sprom)
+@@ -123,18 +125,13 @@ ssize_t ssb_attr_sprom_store(struct ssb_
+ 	err = -ERESTARTSYS;
+ 	if (mutex_lock_interruptible(&bus->sprom_mutex))
+ 		goto out_kfree;
+-	err = ssb_devices_freeze(bus);
+-	if (err == -EOPNOTSUPP) {
+-		ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze devices. "
+-			   "No suspend support. Is CONFIG_PM enabled?\n");
+-		goto out_unlock;
+-	}
++	err = ssb_devices_freeze(bus, &freeze);
+ 	if (err) {
+ 		ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n");
+ 		goto out_unlock;
+ 	}
+ 	res = sprom_write(bus, sprom);
+-	err = ssb_devices_thaw(bus);
++	err = ssb_devices_thaw(&freeze);
+ 	if (err)
+ 		ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n");
+ out_unlock:
+@@ -179,3 +176,17 @@ const struct ssb_sprom *ssb_get_fallback
+ {
+ 	return fallback_sprom;
+ }
++
++/* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
++bool ssb_is_sprom_available(struct ssb_bus *bus)
++{
++	/* status register only exists on chipcomon rev >= 11 and we need check
++	   for >= 31 only */
++	/* this routine differs from specs as we do not access SPROM directly
++	   on PCMCIA */
++	if (bus->bustype == SSB_BUSTYPE_PCI &&
++	    bus->chipco.dev->id.revision >= 31)
++		return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
++
++	return true;
++}
+--- a/drivers/ssb/ssb_private.h
++++ b/drivers/ssb/ssb_private.h
+@@ -176,19 +176,27 @@ extern const struct ssb_sprom *ssb_get_f
+ 
+ /* core.c */
+ extern u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m);
+-extern int ssb_devices_freeze(struct ssb_bus *bus);
+-extern int ssb_devices_thaw(struct ssb_bus *bus);
+ extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev);
+ int ssb_for_each_bus_call(unsigned long data,
+ 			  int (*func)(struct ssb_bus *bus, unsigned long data));
+ extern struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev);
+ 
++struct ssb_freeze_context {
++	/* Pointer to the bus */
++	struct ssb_bus *bus;
++	/* Boolean list to indicate whether a device is frozen on this bus. */
++	bool device_frozen[SSB_MAX_NR_CORES];
++};
++extern int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx);
++extern int ssb_devices_thaw(struct ssb_freeze_context *ctx);
++
++
+ 
+ /* b43_pci_bridge.c */
+ #ifdef CONFIG_SSB_B43_PCI_BRIDGE
+ extern int __init b43_pci_ssb_bridge_init(void);
+ extern void __exit b43_pci_ssb_bridge_exit(void);
+-#else /* CONFIG_SSB_B43_PCI_BRIDGR */
++#else /* CONFIG_SSB_B43_PCI_BRIDGE */
+ static inline int b43_pci_ssb_bridge_init(void)
+ {
+ 	return 0;
+@@ -196,6 +204,6 @@ static inline int b43_pci_ssb_bridge_ini
+ static inline void b43_pci_ssb_bridge_exit(void)
+ {
+ }
+-#endif /* CONFIG_SSB_PCIHOST */
++#endif /* CONFIG_SSB_B43_PCI_BRIDGE */
+ 
+ #endif /* LINUX_SSB_PRIVATE_H_ */
+--- a/include/linux/ssb/ssb.h
++++ b/include/linux/ssb/ssb.h
+@@ -269,7 +269,8 @@ struct ssb_bus {
+ 
+ 	const struct ssb_bus_ops *ops;
+ 
+-	/* The core in the basic address register window. (PCI bus only) */
++	/* The core currently mapped into the MMIO window.
++	 * Not valid on all host-buses. So don't use outside of SSB. */
+ 	struct ssb_device *mapped_device;
+ 	union {
+ 		/* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
+@@ -281,14 +282,17 @@ struct ssb_bus {
+ 	 * On PCMCIA-host busses this is used to protect the whole MMIO access. */
+ 	spinlock_t bar_lock;
+ 
+-	/* The bus this backplane is running on. */
++	/* The host-bus this backplane is running on. */
+ 	enum ssb_bustype bustype;
+-	/* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
+-	struct pci_dev *host_pci;
+-	/* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
+-	struct pcmcia_device *host_pcmcia;
+-	/* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
+-	struct sdio_func *host_sdio;
++	/* Pointers to the host-bus. Check bustype before using any of these pointers. */
++	union {
++		/* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
++		struct pci_dev *host_pci;
++		/* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
++		struct pcmcia_device *host_pcmcia;
++		/* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
++		struct sdio_func *host_sdio;
++	};
+ 
+ 	/* See enum ssb_quirks */
+ 	unsigned int quirks;
+@@ -301,6 +305,7 @@ struct ssb_bus {
+ 	/* ID information about the Chip. */
+ 	u16 chip_id;
+ 	u16 chip_rev;
++	u16 sprom_offset;
+ 	u16 sprom_size;		/* number of words in sprom */
+ 	u8 chip_package;
+ 
+@@ -390,6 +395,9 @@ extern int ssb_bus_sdiobus_register(stru
+ 
+ extern void ssb_bus_unregister(struct ssb_bus *bus);
+ 
++/* Does the device have an SPROM? */
++extern bool ssb_is_sprom_available(struct ssb_bus *bus);
++
+ /* Set a fallback SPROM.
+  * See kdoc at the function definition for complete documentation. */
+ extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
+--- a/include/linux/ssb/ssb_driver_chipcommon.h
++++ b/include/linux/ssb/ssb_driver_chipcommon.h
+@@ -53,6 +53,7 @@
+ #define  SSB_CHIPCO_CAP_64BIT		0x08000000	/* 64-bit Backplane */
+ #define  SSB_CHIPCO_CAP_PMU		0x10000000	/* PMU available (rev >= 20) */
+ #define  SSB_CHIPCO_CAP_ECI		0x20000000	/* ECI available (rev >= 20) */
++#define  SSB_CHIPCO_CAP_SPROM		0x40000000	/* SPROM present */
+ #define SSB_CHIPCO_CORECTL		0x0008
+ #define  SSB_CHIPCO_CORECTL_UARTCLK0	0x00000001	/* Drive UART with internal clock */
+ #define	 SSB_CHIPCO_CORECTL_SE		0x00000002	/* sync clk out enable (corerev >= 3) */
+@@ -385,6 +386,7 @@
+ 
+ 
+ /** Chip specific Chip-Status register contents. */
++#define SSB_CHIPCO_CHST_4322_SPROM_EXISTS	0x00000040 /* SPROM present */
+ #define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL	0x00000003
+ #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL		0 /* OTP is powered up, use def. CIS, no SPROM */
+ #define SSB_CHIPCO_CHST_4325_SPROM_SEL		1 /* OTP is powered up, SPROM is present */
+@@ -398,6 +400,18 @@
+ #define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT	4
+ #define SSB_CHIPCO_CHST_4325_PMUTOP_2B 		0x00000200 /* 1 for 2b, 0 for to 2a */
+ 
++/** Macros to determine SPROM presence based on Chip-Status register. */
++#define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) \
++	((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
++		SSB_CHIPCO_CHST_4325_OTP_SEL)
++#define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) \
++	(status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS)
++#define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) \
++	(((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
++		SSB_CHIPCO_CHST_4325_DEFCIS_SEL) && \
++	 ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
++		SSB_CHIPCO_CHST_4325_OTP_SEL))
++
+ 
+ 
+ /** Clockcontrol masks and values **/
+@@ -564,6 +578,7 @@ struct ssb_chipcommon_pmu {
+ struct ssb_chipcommon {
+ 	struct ssb_device *dev;
+ 	u32 capabilities;
++	u32 status;
+ 	/* Fast Powerup Delay constant */
+ 	u16 fast_pwrup_delay;
+ 	struct ssb_chipcommon_pmu pmu;
+--- a/include/linux/ssb/ssb_regs.h
++++ b/include/linux/ssb/ssb_regs.h
+@@ -170,26 +170,27 @@
+ #define SSB_SPROMSIZE_WORDS_R4		220
+ #define SSB_SPROMSIZE_BYTES_R123	(SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
+ #define SSB_SPROMSIZE_BYTES_R4		(SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
+-#define SSB_SPROM_BASE			0x1000
+-#define SSB_SPROM_REVISION		0x107E
++#define SSB_SPROM_BASE1			0x1000
++#define SSB_SPROM_BASE31		0x0800
++#define SSB_SPROM_REVISION		0x007E
+ #define  SSB_SPROM_REVISION_REV		0x00FF	/* SPROM Revision number */
+ #define  SSB_SPROM_REVISION_CRC		0xFF00	/* SPROM CRC8 value */
+ #define  SSB_SPROM_REVISION_CRC_SHIFT	8
+ 
+ /* SPROM Revision 1 */
+-#define SSB_SPROM1_SPID			0x1004	/* Subsystem Product ID for PCI */
+-#define SSB_SPROM1_SVID			0x1006	/* Subsystem Vendor ID for PCI */
+-#define SSB_SPROM1_PID			0x1008	/* Product ID for PCI */
+-#define SSB_SPROM1_IL0MAC		0x1048	/* 6 bytes MAC address for 802.11b/g */
+-#define SSB_SPROM1_ET0MAC		0x104E	/* 6 bytes MAC address for Ethernet */
+-#define SSB_SPROM1_ET1MAC		0x1054	/* 6 bytes MAC address for 802.11a */
+-#define SSB_SPROM1_ETHPHY		0x105A	/* Ethernet PHY settings */
++#define SSB_SPROM1_SPID			0x0004	/* Subsystem Product ID for PCI */
++#define SSB_SPROM1_SVID			0x0006	/* Subsystem Vendor ID for PCI */
++#define SSB_SPROM1_PID			0x0008	/* Product ID for PCI */
++#define SSB_SPROM1_IL0MAC		0x0048	/* 6 bytes MAC address for 802.11b/g */
++#define SSB_SPROM1_ET0MAC		0x004E	/* 6 bytes MAC address for Ethernet */
++#define SSB_SPROM1_ET1MAC		0x0054	/* 6 bytes MAC address for 802.11a */
++#define SSB_SPROM1_ETHPHY		0x005A	/* Ethernet PHY settings */
+ #define  SSB_SPROM1_ETHPHY_ET0A		0x001F	/* MII Address for enet0 */
+ #define  SSB_SPROM1_ETHPHY_ET1A		0x03E0	/* MII Address for enet1 */
+ #define  SSB_SPROM1_ETHPHY_ET1A_SHIFT	5
+ #define  SSB_SPROM1_ETHPHY_ET0M		(1<<14)	/* MDIO for enet0 */
+ #define  SSB_SPROM1_ETHPHY_ET1M		(1<<15)	/* MDIO for enet1 */
+-#define SSB_SPROM1_BINF			0x105C	/* Board info */
++#define SSB_SPROM1_BINF			0x005C	/* Board info */
+ #define  SSB_SPROM1_BINF_BREV		0x00FF	/* Board Revision */
+ #define  SSB_SPROM1_BINF_CCODE		0x0F00	/* Country Code */
+ #define  SSB_SPROM1_BINF_CCODE_SHIFT	8
+@@ -197,63 +198,63 @@
+ #define  SSB_SPROM1_BINF_ANTBG_SHIFT	12
+ #define  SSB_SPROM1_BINF_ANTA		0xC000	/* Available A-PHY antennas */
+ #define  SSB_SPROM1_BINF_ANTA_SHIFT	14
+-#define SSB_SPROM1_PA0B0		0x105E
+-#define SSB_SPROM1_PA0B1		0x1060
+-#define SSB_SPROM1_PA0B2		0x1062
+-#define SSB_SPROM1_GPIOA		0x1064	/* General Purpose IO pins 0 and 1 */
++#define SSB_SPROM1_PA0B0		0x005E
++#define SSB_SPROM1_PA0B1		0x0060
++#define SSB_SPROM1_PA0B2		0x0062
++#define SSB_SPROM1_GPIOA		0x0064	/* General Purpose IO pins 0 and 1 */
+ #define  SSB_SPROM1_GPIOA_P0		0x00FF	/* Pin 0 */
+ #define  SSB_SPROM1_GPIOA_P1		0xFF00	/* Pin 1 */
+ #define  SSB_SPROM1_GPIOA_P1_SHIFT	8
+-#define SSB_SPROM1_GPIOB		0x1066	/* General Purpuse IO pins 2 and 3 */
++#define SSB_SPROM1_GPIOB		0x0066	/* General Purpuse IO pins 2 and 3 */
+ #define  SSB_SPROM1_GPIOB_P2		0x00FF	/* Pin 2 */
+ #define  SSB_SPROM1_GPIOB_P3		0xFF00	/* Pin 3 */
+ #define  SSB_SPROM1_GPIOB_P3_SHIFT	8
+-#define SSB_SPROM1_MAXPWR		0x1068	/* Power Amplifier Max Power */
++#define SSB_SPROM1_MAXPWR		0x0068	/* Power Amplifier Max Power */
+ #define  SSB_SPROM1_MAXPWR_BG		0x00FF	/* B-PHY and G-PHY (in dBm Q5.2) */
+ #define  SSB_SPROM1_MAXPWR_A		0xFF00	/* A-PHY (in dBm Q5.2) */
+ #define  SSB_SPROM1_MAXPWR_A_SHIFT	8
+-#define SSB_SPROM1_PA1B0		0x106A
+-#define SSB_SPROM1_PA1B1		0x106C
+-#define SSB_SPROM1_PA1B2		0x106E
+-#define SSB_SPROM1_ITSSI		0x1070	/* Idle TSSI Target */
++#define SSB_SPROM1_PA1B0		0x006A
++#define SSB_SPROM1_PA1B1		0x006C
++#define SSB_SPROM1_PA1B2		0x006E
++#define SSB_SPROM1_ITSSI		0x0070	/* Idle TSSI Target */
+ #define  SSB_SPROM1_ITSSI_BG		0x00FF	/* B-PHY and G-PHY*/
+ #define  SSB_SPROM1_ITSSI_A		0xFF00	/* A-PHY */
+ #define  SSB_SPROM1_ITSSI_A_SHIFT	8
+-#define SSB_SPROM1_BFLLO		0x1072	/* Boardflags (low 16 bits) */
+-#define SSB_SPROM1_AGAIN		0x1074	/* Antenna Gain (in dBm Q5.2) */
++#define SSB_SPROM1_BFLLO		0x0072	/* Boardflags (low 16 bits) */
++#define SSB_SPROM1_AGAIN		0x0074	/* Antenna Gain (in dBm Q5.2) */
+ #define  SSB_SPROM1_AGAIN_BG		0x00FF	/* B-PHY and G-PHY */
+ #define  SSB_SPROM1_AGAIN_BG_SHIFT	0
+ #define  SSB_SPROM1_AGAIN_A		0xFF00	/* A-PHY */
+ #define  SSB_SPROM1_AGAIN_A_SHIFT	8
+ 
+ /* SPROM Revision 2 (inherits from rev 1) */
+-#define SSB_SPROM2_BFLHI		0x1038	/* Boardflags (high 16 bits) */
+-#define SSB_SPROM2_MAXP_A		0x103A	/* A-PHY Max Power */
++#define SSB_SPROM2_BFLHI		0x0038	/* Boardflags (high 16 bits) */
++#define SSB_SPROM2_MAXP_A		0x003A	/* A-PHY Max Power */
+ #define  SSB_SPROM2_MAXP_A_HI		0x00FF	/* Max Power High */
+ #define  SSB_SPROM2_MAXP_A_LO		0xFF00	/* Max Power Low */
+ #define  SSB_SPROM2_MAXP_A_LO_SHIFT	8
+-#define SSB_SPROM2_PA1LOB0		0x103C	/* A-PHY PowerAmplifier Low Settings */
+-#define SSB_SPROM2_PA1LOB1		0x103E	/* A-PHY PowerAmplifier Low Settings */
+-#define SSB_SPROM2_PA1LOB2		0x1040	/* A-PHY PowerAmplifier Low Settings */
+-#define SSB_SPROM2_PA1HIB0		0x1042	/* A-PHY PowerAmplifier High Settings */
+-#define SSB_SPROM2_PA1HIB1		0x1044	/* A-PHY PowerAmplifier High Settings */
+-#define SSB_SPROM2_PA1HIB2		0x1046	/* A-PHY PowerAmplifier High Settings */
+-#define SSB_SPROM2_OPO			0x1078	/* OFDM Power Offset from CCK Level */
++#define SSB_SPROM2_PA1LOB0		0x003C	/* A-PHY PowerAmplifier Low Settings */
++#define SSB_SPROM2_PA1LOB1		0x003E	/* A-PHY PowerAmplifier Low Settings */
++#define SSB_SPROM2_PA1LOB2		0x0040	/* A-PHY PowerAmplifier Low Settings */
++#define SSB_SPROM2_PA1HIB0		0x0042	/* A-PHY PowerAmplifier High Settings */
++#define SSB_SPROM2_PA1HIB1		0x0044	/* A-PHY PowerAmplifier High Settings */
++#define SSB_SPROM2_PA1HIB2		0x0046	/* A-PHY PowerAmplifier High Settings */
++#define SSB_SPROM2_OPO			0x0078	/* OFDM Power Offset from CCK Level */
+ #define  SSB_SPROM2_OPO_VALUE		0x00FF
+ #define  SSB_SPROM2_OPO_UNUSED		0xFF00
+-#define SSB_SPROM2_CCODE		0x107C	/* Two char Country Code */
++#define SSB_SPROM2_CCODE		0x007C	/* Two char Country Code */
+ 
+ /* SPROM Revision 3 (inherits most data from rev 2) */
+-#define SSB_SPROM3_IL0MAC		0x104A	/* 6 bytes MAC address for 802.11b/g */
+-#define SSB_SPROM3_OFDMAPO		0x102C	/* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
+-#define SSB_SPROM3_OFDMALPO		0x1030	/* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
+-#define SSB_SPROM3_OFDMAHPO		0x1034	/* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
+-#define SSB_SPROM3_GPIOLDC		0x1042	/* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
++#define SSB_SPROM3_OFDMAPO		0x002C	/* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
++#define SSB_SPROM3_OFDMALPO		0x0030	/* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
++#define SSB_SPROM3_OFDMAHPO		0x0034	/* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
++#define SSB_SPROM3_GPIOLDC		0x0042	/* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
+ #define  SSB_SPROM3_GPIOLDC_OFF		0x0000FF00	/* Off Count */
+ #define  SSB_SPROM3_GPIOLDC_OFF_SHIFT	8
+ #define  SSB_SPROM3_GPIOLDC_ON		0x00FF0000	/* On Count */
+ #define  SSB_SPROM3_GPIOLDC_ON_SHIFT	16
+-#define SSB_SPROM3_CCKPO		0x1078	/* CCK Power Offset */
++#define SSB_SPROM3_IL0MAC		0x004A	/* 6 bytes MAC address for 802.11b/g */
++#define SSB_SPROM3_CCKPO		0x0078	/* CCK Power Offset */
+ #define  SSB_SPROM3_CCKPO_1M		0x000F	/* 1M Rate PO */
+ #define  SSB_SPROM3_CCKPO_2M		0x00F0	/* 2M Rate PO */
+ #define  SSB_SPROM3_CCKPO_2M_SHIFT	4
+@@ -264,100 +265,100 @@
+ #define  SSB_SPROM3_OFDMGPO		0x107A	/* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
+ 
+ /* SPROM Revision 4 */
+-#define SSB_SPROM4_IL0MAC		0x104C	/* 6 byte MAC address for a/b/g/n */
+-#define SSB_SPROM4_ETHPHY		0x105A	/* Ethernet PHY settings ?? */
++#define SSB_SPROM4_BFLLO		0x0044	/* Boardflags (low 16 bits) */
++#define SSB_SPROM4_BFLHI		0x0046  /* Board Flags Hi */
++#define SSB_SPROM4_IL0MAC		0x004C	/* 6 byte MAC address for a/b/g/n */
++#define SSB_SPROM4_CCODE		0x0052	/* Country Code (2 bytes) */
++#define SSB_SPROM4_GPIOA		0x0056	/* Gen. Purpose IO # 0 and 1 */
++#define  SSB_SPROM4_GPIOA_P0		0x00FF	/* Pin 0 */
++#define  SSB_SPROM4_GPIOA_P1		0xFF00	/* Pin 1 */
++#define  SSB_SPROM4_GPIOA_P1_SHIFT	8
++#define SSB_SPROM4_GPIOB		0x0058	/* Gen. Purpose IO # 2 and 3 */
++#define  SSB_SPROM4_GPIOB_P2		0x00FF	/* Pin 2 */
++#define  SSB_SPROM4_GPIOB_P3		0xFF00	/* Pin 3 */
++#define  SSB_SPROM4_GPIOB_P3_SHIFT	8
++#define SSB_SPROM4_ETHPHY		0x005A	/* Ethernet PHY settings ?? */
+ #define  SSB_SPROM4_ETHPHY_ET0A		0x001F	/* MII Address for enet0 */
+ #define  SSB_SPROM4_ETHPHY_ET1A		0x03E0	/* MII Address for enet1 */
+ #define  SSB_SPROM4_ETHPHY_ET1A_SHIFT	5
+ #define  SSB_SPROM4_ETHPHY_ET0M		(1<<14)	/* MDIO for enet0 */
+ #define  SSB_SPROM4_ETHPHY_ET1M		(1<<15)	/* MDIO for enet1 */
+-#define SSB_SPROM4_CCODE		0x1052	/* Country Code (2 bytes) */
+-#define SSB_SPROM4_ANTAVAIL		0x105D  /* Antenna available bitfields */
+-#define SSB_SPROM4_ANTAVAIL_A		0x00FF	/* A-PHY bitfield */
+-#define SSB_SPROM4_ANTAVAIL_A_SHIFT	0
+-#define SSB_SPROM4_ANTAVAIL_BG		0xFF00	/* B-PHY and G-PHY bitfield */
+-#define SSB_SPROM4_ANTAVAIL_BG_SHIFT	8
+-#define SSB_SPROM4_BFLLO		0x1044	/* Boardflags (low 16 bits) */
+-#define SSB_SPROM4_AGAIN01		0x105E	/* Antenna Gain (in dBm Q5.2) */
++#define SSB_SPROM4_ANTAVAIL		0x005D  /* Antenna available bitfields */
++#define  SSB_SPROM4_ANTAVAIL_A		0x00FF	/* A-PHY bitfield */
++#define  SSB_SPROM4_ANTAVAIL_A_SHIFT	0
++#define  SSB_SPROM4_ANTAVAIL_BG		0xFF00	/* B-PHY and G-PHY bitfield */
++#define  SSB_SPROM4_ANTAVAIL_BG_SHIFT	8
++#define SSB_SPROM4_AGAIN01		0x005E	/* Antenna Gain (in dBm Q5.2) */
+ #define  SSB_SPROM4_AGAIN0		0x00FF	/* Antenna 0 */
+ #define  SSB_SPROM4_AGAIN0_SHIFT	0
+ #define  SSB_SPROM4_AGAIN1		0xFF00	/* Antenna 1 */
+ #define  SSB_SPROM4_AGAIN1_SHIFT	8
+-#define SSB_SPROM4_AGAIN23		0x1060
++#define SSB_SPROM4_AGAIN23		0x0060
+ #define  SSB_SPROM4_AGAIN2		0x00FF	/* Antenna 2 */
+ #define  SSB_SPROM4_AGAIN2_SHIFT	0
+ #define  SSB_SPROM4_AGAIN3		0xFF00	/* Antenna 3 */
+ #define  SSB_SPROM4_AGAIN3_SHIFT	8
+-#define SSB_SPROM4_BFLHI		0x1046  /* Board Flags Hi */
+-#define SSB_SPROM4_MAXP_BG		0x1080  /* Max Power BG in path 1 */
++#define SSB_SPROM4_MAXP_BG		0x0080  /* Max Power BG in path 1 */
+ #define  SSB_SPROM4_MAXP_BG_MASK	0x00FF  /* Mask for Max Power BG */
+ #define  SSB_SPROM4_ITSSI_BG		0xFF00	/* Mask for path 1 itssi_bg */
+ #define  SSB_SPROM4_ITSSI_BG_SHIFT	8
+-#define SSB_SPROM4_MAXP_A		0x108A  /* Max Power A in path 1 */
++#define SSB_SPROM4_MAXP_A		0x008A  /* Max Power A in path 1 */
+ #define  SSB_SPROM4_MAXP_A_MASK		0x00FF  /* Mask for Max Power A */
+ #define  SSB_SPROM4_ITSSI_A		0xFF00	/* Mask for path 1 itssi_a */
+ #define  SSB_SPROM4_ITSSI_A_SHIFT	8
+-#define SSB_SPROM4_GPIOA		0x1056	/* Gen. Purpose IO # 0 and 1 */
+-#define  SSB_SPROM4_GPIOA_P0		0x00FF	/* Pin 0 */
+-#define  SSB_SPROM4_GPIOA_P1		0xFF00	/* Pin 1 */
+-#define  SSB_SPROM4_GPIOA_P1_SHIFT	8
+-#define SSB_SPROM4_GPIOB		0x1058	/* Gen. Purpose IO # 2 and 3 */
+-#define  SSB_SPROM4_GPIOB_P2		0x00FF	/* Pin 2 */
+-#define  SSB_SPROM4_GPIOB_P3		0xFF00	/* Pin 3 */
+-#define  SSB_SPROM4_GPIOB_P3_SHIFT	8
+-#define SSB_SPROM4_PA0B0		0x1082	/* The paXbY locations are */
+-#define SSB_SPROM4_PA0B1		0x1084	/*   only guesses */
+-#define SSB_SPROM4_PA0B2		0x1086
+-#define SSB_SPROM4_PA1B0		0x108E
+-#define SSB_SPROM4_PA1B1		0x1090
+-#define SSB_SPROM4_PA1B2		0x1092
++#define SSB_SPROM4_PA0B0		0x0082	/* The paXbY locations are */
++#define SSB_SPROM4_PA0B1		0x0084	/*   only guesses */
++#define SSB_SPROM4_PA0B2		0x0086
++#define SSB_SPROM4_PA1B0		0x008E
++#define SSB_SPROM4_PA1B1		0x0090
++#define SSB_SPROM4_PA1B2		0x0092
+ 
+ /* SPROM Revision 5 (inherits most data from rev 4) */
+-#define SSB_SPROM5_BFLLO		0x104A	/* Boardflags (low 16 bits) */
+-#define SSB_SPROM5_BFLHI		0x104C  /* Board Flags Hi */
+-#define SSB_SPROM5_IL0MAC		0x1052	/* 6 byte MAC address for a/b/g/n */
+-#define SSB_SPROM5_CCODE		0x1044	/* Country Code (2 bytes) */
+-#define SSB_SPROM5_GPIOA		0x1076	/* Gen. Purpose IO # 0 and 1 */
++#define SSB_SPROM5_CCODE		0x0044	/* Country Code (2 bytes) */
++#define SSB_SPROM5_BFLLO		0x004A	/* Boardflags (low 16 bits) */
++#define SSB_SPROM5_BFLHI		0x004C  /* Board Flags Hi */
++#define SSB_SPROM5_IL0MAC		0x0052	/* 6 byte MAC address for a/b/g/n */
++#define SSB_SPROM5_GPIOA		0x0076	/* Gen. Purpose IO # 0 and 1 */
+ #define  SSB_SPROM5_GPIOA_P0		0x00FF	/* Pin 0 */
+ #define  SSB_SPROM5_GPIOA_P1		0xFF00	/* Pin 1 */
+ #define  SSB_SPROM5_GPIOA_P1_SHIFT	8
+-#define SSB_SPROM5_GPIOB		0x1078	/* Gen. Purpose IO # 2 and 3 */
++#define SSB_SPROM5_GPIOB		0x0078	/* Gen. Purpose IO # 2 and 3 */
+ #define  SSB_SPROM5_GPIOB_P2		0x00FF	/* Pin 2 */
+ #define  SSB_SPROM5_GPIOB_P3		0xFF00	/* Pin 3 */
+ #define  SSB_SPROM5_GPIOB_P3_SHIFT	8
+ 
+ /* SPROM Revision 8 */
+-#define SSB_SPROM8_BOARDREV		0x1082	/* Board revision */
+-#define SSB_SPROM8_BFLLO		0x1084	/* Board flags (bits 0-15) */
+-#define SSB_SPROM8_BFLHI		0x1086	/* Board flags (bits 16-31) */
+-#define SSB_SPROM8_BFL2LO		0x1088	/* Board flags (bits 32-47) */
+-#define SSB_SPROM8_BFL2HI		0x108A	/* Board flags (bits 48-63) */
+-#define SSB_SPROM8_IL0MAC		0x108C	/* 6 byte MAC address */
+-#define SSB_SPROM8_CCODE		0x1092	/* 2 byte country code */
+-#define SSB_SPROM8_ANTAVAIL		0x109C  /* Antenna available bitfields*/
+-#define SSB_SPROM8_ANTAVAIL_A		0xFF00	/* A-PHY bitfield */
+-#define SSB_SPROM8_ANTAVAIL_A_SHIFT	8
+-#define SSB_SPROM8_ANTAVAIL_BG		0x00FF	/* B-PHY and G-PHY bitfield */
+-#define SSB_SPROM8_ANTAVAIL_BG_SHIFT	0
+-#define SSB_SPROM8_AGAIN01		0x109E	/* Antenna Gain (in dBm Q5.2) */
++#define SSB_SPROM8_BOARDREV		0x0082	/* Board revision */
++#define SSB_SPROM8_BFLLO		0x0084	/* Board flags (bits 0-15) */
++#define SSB_SPROM8_BFLHI		0x0086	/* Board flags (bits 16-31) */
++#define SSB_SPROM8_BFL2LO		0x0088	/* Board flags (bits 32-47) */
++#define SSB_SPROM8_BFL2HI		0x008A	/* Board flags (bits 48-63) */
++#define SSB_SPROM8_IL0MAC		0x008C	/* 6 byte MAC address */
++#define SSB_SPROM8_CCODE		0x0092	/* 2 byte country code */
++#define SSB_SPROM8_GPIOA		0x0096	/*Gen. Purpose IO # 0 and 1 */
++#define  SSB_SPROM8_GPIOA_P0		0x00FF	/* Pin 0 */
++#define  SSB_SPROM8_GPIOA_P1		0xFF00	/* Pin 1 */
++#define  SSB_SPROM8_GPIOA_P1_SHIFT	8
++#define SSB_SPROM8_GPIOB		0x0098	/* Gen. Purpose IO # 2 and 3 */
++#define  SSB_SPROM8_GPIOB_P2		0x00FF	/* Pin 2 */
++#define  SSB_SPROM8_GPIOB_P3		0xFF00	/* Pin 3 */
++#define  SSB_SPROM8_GPIOB_P3_SHIFT	8
++#define SSB_SPROM8_ANTAVAIL		0x009C  /* Antenna available bitfields*/
++#define  SSB_SPROM8_ANTAVAIL_A		0xFF00	/* A-PHY bitfield */
++#define  SSB_SPROM8_ANTAVAIL_A_SHIFT	8
++#define  SSB_SPROM8_ANTAVAIL_BG		0x00FF	/* B-PHY and G-PHY bitfield */
++#define  SSB_SPROM8_ANTAVAIL_BG_SHIFT	0
++#define SSB_SPROM8_AGAIN01		0x009E	/* Antenna Gain (in dBm Q5.2) */
+ #define  SSB_SPROM8_AGAIN0		0x00FF	/* Antenna 0 */
+ #define  SSB_SPROM8_AGAIN0_SHIFT	0
+ #define  SSB_SPROM8_AGAIN1		0xFF00	/* Antenna 1 */
+ #define  SSB_SPROM8_AGAIN1_SHIFT	8
+-#define SSB_SPROM8_AGAIN23		0x10A0
++#define SSB_SPROM8_AGAIN23		0x00A0
+ #define  SSB_SPROM8_AGAIN2		0x00FF	/* Antenna 2 */
+ #define  SSB_SPROM8_AGAIN2_SHIFT	0
+ #define  SSB_SPROM8_AGAIN3		0xFF00	/* Antenna 3 */
+ #define  SSB_SPROM8_AGAIN3_SHIFT	8
+-#define SSB_SPROM8_GPIOA		0x1096	/*Gen. Purpose IO # 0 and 1 */
+-#define  SSB_SPROM8_GPIOA_P0		0x00FF	/* Pin 0 */
+-#define  SSB_SPROM8_GPIOA_P1		0xFF00	/* Pin 1 */
+-#define  SSB_SPROM8_GPIOA_P1_SHIFT	8
+-#define SSB_SPROM8_GPIOB		0x1098	/* Gen. Purpose IO # 2 and 3 */
+-#define  SSB_SPROM8_GPIOB_P2		0x00FF	/* Pin 2 */
+-#define  SSB_SPROM8_GPIOB_P3		0xFF00	/* Pin 3 */
+-#define  SSB_SPROM8_GPIOB_P3_SHIFT	8
+-#define SSB_SPROM8_RSSIPARM2G		0x10A4	/* RSSI params for 2GHz */
++#define SSB_SPROM8_RSSIPARM2G		0x00A4	/* RSSI params for 2GHz */
+ #define  SSB_SPROM8_RSSISMF2G		0x000F
+ #define  SSB_SPROM8_RSSISMC2G		0x00F0
+ #define  SSB_SPROM8_RSSISMC2G_SHIFT	4
+@@ -365,7 +366,7 @@
+ #define  SSB_SPROM8_RSSISAV2G_SHIFT	8
+ #define  SSB_SPROM8_BXA2G		0x1800
+ #define  SSB_SPROM8_BXA2G_SHIFT		11
+-#define SSB_SPROM8_RSSIPARM5G		0x10A6	/* RSSI params for 5GHz */
++#define SSB_SPROM8_RSSIPARM5G		0x00A6	/* RSSI params for 5GHz */
+ #define  SSB_SPROM8_RSSISMF5G		0x000F
+ #define  SSB_SPROM8_RSSISMC5G		0x00F0
+ #define  SSB_SPROM8_RSSISMC5G_SHIFT	4
+@@ -373,47 +374,47 @@
+ #define  SSB_SPROM8_RSSISAV5G_SHIFT	8
+ #define  SSB_SPROM8_BXA5G		0x1800
+ #define  SSB_SPROM8_BXA5G_SHIFT		11
+-#define SSB_SPROM8_TRI25G		0x10A8	/* TX isolation 2.4&5.3GHz */
++#define SSB_SPROM8_TRI25G		0x00A8	/* TX isolation 2.4&5.3GHz */
+ #define  SSB_SPROM8_TRI2G		0x00FF	/* TX isolation 2.4GHz */
+ #define  SSB_SPROM8_TRI5G		0xFF00	/* TX isolation 5.3GHz */
+ #define  SSB_SPROM8_TRI5G_SHIFT		8
+-#define SSB_SPROM8_TRI5GHL		0x10AA	/* TX isolation 5.2/5.8GHz */
++#define SSB_SPROM8_TRI5GHL		0x00AA	/* TX isolation 5.2/5.8GHz */
+ #define  SSB_SPROM8_TRI5GL		0x00FF	/* TX isolation 5.2GHz */
+ #define  SSB_SPROM8_TRI5GH		0xFF00	/* TX isolation 5.8GHz */
+ #define  SSB_SPROM8_TRI5GH_SHIFT	8
+-#define SSB_SPROM8_RXPO			0x10AC  /* RX power offsets */
++#define SSB_SPROM8_RXPO			0x00AC  /* RX power offsets */
+ #define  SSB_SPROM8_RXPO2G		0x00FF	/* 2GHz RX power offset */
+ #define  SSB_SPROM8_RXPO5G		0xFF00	/* 5GHz RX power offset */
+ #define  SSB_SPROM8_RXPO5G_SHIFT	8
+-#define SSB_SPROM8_MAXP_BG		0x10C0  /* Max Power 2GHz in path 1 */
++#define SSB_SPROM8_MAXP_BG		0x00C0  /* Max Power 2GHz in path 1 */
+ #define  SSB_SPROM8_MAXP_BG_MASK	0x00FF  /* Mask for Max Power 2GHz */
+ #define  SSB_SPROM8_ITSSI_BG		0xFF00	/* Mask for path 1 itssi_bg */
+ #define  SSB_SPROM8_ITSSI_BG_SHIFT	8
+-#define SSB_SPROM8_PA0B0		0x10C2	/* 2GHz power amp settings */
+-#define SSB_SPROM8_PA0B1		0x10C4
+-#define SSB_SPROM8_PA0B2		0x10C6
+-#define SSB_SPROM8_MAXP_A		0x10C8  /* Max Power 5.3GHz */
++#define SSB_SPROM8_PA0B0		0x00C2	/* 2GHz power amp settings */
++#define SSB_SPROM8_PA0B1		0x00C4
++#define SSB_SPROM8_PA0B2		0x00C6
++#define SSB_SPROM8_MAXP_A		0x00C8  /* Max Power 5.3GHz */
+ #define  SSB_SPROM8_MAXP_A_MASK		0x00FF  /* Mask for Max Power 5.3GHz */
+ #define  SSB_SPROM8_ITSSI_A		0xFF00	/* Mask for path 1 itssi_a */
+ #define  SSB_SPROM8_ITSSI_A_SHIFT	8
+-#define SSB_SPROM8_MAXP_AHL		0x10CA  /* Max Power 5.2/5.8GHz */
++#define SSB_SPROM8_MAXP_AHL		0x00CA  /* Max Power 5.2/5.8GHz */
+ #define  SSB_SPROM8_MAXP_AH_MASK	0x00FF  /* Mask for Max Power 5.8GHz */
+ #define  SSB_SPROM8_MAXP_AL_MASK	0xFF00  /* Mask for Max Power 5.2GHz */
+ #define  SSB_SPROM8_MAXP_AL_SHIFT	8
+-#define SSB_SPROM8_PA1B0		0x10CC	/* 5.3GHz power amp settings */
+-#define SSB_SPROM8_PA1B1		0x10CE
+-#define SSB_SPROM8_PA1B2		0x10D0
+-#define SSB_SPROM8_PA1LOB0		0x10D2	/* 5.2GHz power amp settings */
+-#define SSB_SPROM8_PA1LOB1		0x10D4
+-#define SSB_SPROM8_PA1LOB2		0x10D6
+-#define SSB_SPROM8_PA1HIB0		0x10D8	/* 5.8GHz power amp settings */
+-#define SSB_SPROM8_PA1HIB1		0x10DA
+-#define SSB_SPROM8_PA1HIB2		0x10DC
+-#define SSB_SPROM8_CCK2GPO		0x1140	/* CCK power offset */
+-#define SSB_SPROM8_OFDM2GPO		0x1142	/* 2.4GHz OFDM power offset */
+-#define SSB_SPROM8_OFDM5GPO		0x1146	/* 5.3GHz OFDM power offset */
+-#define SSB_SPROM8_OFDM5GLPO		0x114A	/* 5.2GHz OFDM power offset */
+-#define SSB_SPROM8_OFDM5GHPO		0x114E	/* 5.8GHz OFDM power offset */
++#define SSB_SPROM8_PA1B0		0x00CC	/* 5.3GHz power amp settings */
++#define SSB_SPROM8_PA1B1		0x00CE
++#define SSB_SPROM8_PA1B2		0x00D0
++#define SSB_SPROM8_PA1LOB0		0x00D2	/* 5.2GHz power amp settings */
++#define SSB_SPROM8_PA1LOB1		0x00D4
++#define SSB_SPROM8_PA1LOB2		0x00D6
++#define SSB_SPROM8_PA1HIB0		0x00D8	/* 5.8GHz power amp settings */
++#define SSB_SPROM8_PA1HIB1		0x00DA
++#define SSB_SPROM8_PA1HIB2		0x00DC
++#define SSB_SPROM8_CCK2GPO		0x0140	/* CCK power offset */
++#define SSB_SPROM8_OFDM2GPO		0x0142	/* 2.4GHz OFDM power offset */
++#define SSB_SPROM8_OFDM5GPO		0x0146	/* 5.3GHz OFDM power offset */
++#define SSB_SPROM8_OFDM5GLPO		0x014A	/* 5.2GHz OFDM power offset */
++#define SSB_SPROM8_OFDM5GHPO		0x014E	/* 5.8GHz OFDM power offset */
+ 
+ /* Values for SSB_SPROM1_BINF_CCODE */
+ enum {
diff --git a/target/linux/generic-2.6/patches-2.6.33/975-ssb_update.patch b/target/linux/generic-2.6/patches-2.6.33/975-ssb_update.patch
new file mode 100644
index 0000000000..fbc8f517b0
--- /dev/null
+++ b/target/linux/generic-2.6/patches-2.6.33/975-ssb_update.patch
@@ -0,0 +1,644 @@
+--- a/drivers/ssb/driver_chipcommon.c
++++ b/drivers/ssb/driver_chipcommon.c
+@@ -233,6 +233,8 @@ void ssb_chipcommon_init(struct ssb_chip
+ {
+ 	if (!cc->dev)
+ 		return; /* We don't have a ChipCommon */
++	if (cc->dev->id.revision >= 11)
++		cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
+ 	ssb_pmu_init(cc);
+ 	chipco_powercontrol_init(cc);
+ 	ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
+@@ -370,6 +372,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c
+ {
+ 	return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
+ }
++EXPORT_SYMBOL(ssb_chipco_gpio_control);
+ 
+ u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
+ {
+--- a/drivers/ssb/driver_chipcommon_pmu.c
++++ b/drivers/ssb/driver_chipcommon_pmu.c
+@@ -332,6 +332,12 @@ static void ssb_pmu_pll_init(struct ssb_
+ 	case 0x5354:
+ 		ssb_pmu0_pllinit_r0(cc, crystalfreq);
+ 		break;
++	case 0x4322:
++		if (cc->pmu.rev == 2) {
++			chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, 0x0000000A);
++			chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
++		}
++		break;
+ 	default:
+ 		ssb_printk(KERN_ERR PFX
+ 			   "ERROR: PLL init unknown for device %04X\n",
+@@ -417,6 +423,7 @@ static void ssb_pmu_resources_init(struc
+ 
+ 	switch (bus->chip_id) {
+ 	case 0x4312:
++	case 0x4322:
+ 		/* We keep the default settings:
+ 		 * min_msk = 0xCBB
+ 		 * max_msk = 0x7FFFF
+--- a/drivers/ssb/driver_mipscore.c
++++ b/drivers/ssb/driver_mipscore.c
+@@ -270,7 +270,6 @@ void ssb_mipscore_init(struct ssb_mipsco
+ 				set_irq(dev, irq++);
+ 			}
+ 			break;
+-			/* fallthrough */
+ 		case SSB_DEV_PCI:
+ 		case SSB_DEV_ETHERNET:
+ 		case SSB_DEV_ETHERNET_GBIT:
+@@ -281,6 +280,10 @@ void ssb_mipscore_init(struct ssb_mipsco
+ 				set_irq(dev, irq++);
+ 				break;
+ 			}
++			/* fallthrough */
++		case SSB_DEV_EXTIF:
++			set_irq(dev, 0);
++			break;
+ 		}
+ 	}
+ 	ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
+--- a/drivers/ssb/driver_pcicore.c
++++ b/drivers/ssb/driver_pcicore.c
+@@ -246,20 +246,12 @@ static struct pci_controller ssb_pcicore
+ 	.pci_ops	= &ssb_pcicore_pciops,
+ 	.io_resource	= &ssb_pcicore_io_resource,
+ 	.mem_resource	= &ssb_pcicore_mem_resource,
+-	.mem_offset	= 0x24000000,
+ };
+ 
+-static u32 ssb_pcicore_pcibus_iobase = 0x100;
+-static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
+-
+ /* This function is called when doing a pci_enable_device().
+  * We must first check if the device is a device on the PCI-core bridge. */
+ int ssb_pcicore_plat_dev_init(struct pci_dev *d)
+ {
+-	struct resource *res;
+-	int pos, size;
+-	u32 *base;
+-
+ 	if (d->bus->ops != &ssb_pcicore_pciops) {
+ 		/* This is not a device on the PCI-core bridge. */
+ 		return -ENODEV;
+@@ -268,27 +260,6 @@ int ssb_pcicore_plat_dev_init(struct pci
+ 	ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
+ 		   pci_name(d));
+ 
+-	/* Fix up resource bases */
+-	for (pos = 0; pos < 6; pos++) {
+-		res = &d->resource[pos];
+-		if (res->flags & IORESOURCE_IO)
+-			base = &ssb_pcicore_pcibus_iobase;
+-		else
+-			base = &ssb_pcicore_pcibus_membase;
+-		res->flags |= IORESOURCE_PCI_FIXED;
+-		if (res->end) {
+-			size = res->end - res->start + 1;
+-			if (*base & (size - 1))
+-				*base = (*base + size) & ~(size - 1);
+-			res->start = *base;
+-			res->end = res->start + size - 1;
+-			*base += size;
+-			pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
+-		}
+-		/* Fix up PCI bridge BAR0 only */
+-		if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
+-			break;
+-	}
+ 	/* Fix up interrupt lines */
+ 	d->irq = ssb_mips_irq(extpci_core->dev) + 2;
+ 	pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
+--- a/drivers/ssb/main.c
++++ b/drivers/ssb/main.c
+@@ -833,6 +833,9 @@ int ssb_bus_pcibus_register(struct ssb_b
+ 	if (!err) {
+ 		ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
+ 			   "PCI device %s\n", dev_name(&host_pci->dev));
++	} else {
++		ssb_printk(KERN_ERR PFX "Failed to register PCI version"
++			   " of SSB with error %d\n", err);
+ 	}
+ 
+ 	return err;
+--- a/drivers/ssb/pci.c
++++ b/drivers/ssb/pci.c
+@@ -167,7 +167,7 @@ err_pci:
+ }
+ 
+ /* Get the word-offset for a SSB_SPROM_XXX define. */
+-#define SPOFF(offset)	(((offset) - SSB_SPROM_BASE) / sizeof(u16))
++#define SPOFF(offset)	((offset) / sizeof(u16))
+ /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
+ #define SPEX16(_outvar, _offset, _mask, _shift)	\
+ 	out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
+@@ -253,7 +253,7 @@ static int sprom_do_read(struct ssb_bus 
+ 	int i;
+ 
+ 	for (i = 0; i < bus->sprom_size; i++)
+-		sprom[i] = ioread16(bus->mmio + SSB_SPROM_BASE + (i * 2));
++		sprom[i] = ioread16(bus->mmio + bus->sprom_offset + (i * 2));
+ 
+ 	return 0;
+ }
+@@ -284,7 +284,7 @@ static int sprom_do_write(struct ssb_bus
+ 			ssb_printk("75%%");
+ 		else if (i % 2)
+ 			ssb_printk(".");
+-		writew(sprom[i], bus->mmio + SSB_SPROM_BASE + (i * 2));
++		writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
+ 		mmiowb();
+ 		msleep(20);
+ 	}
+@@ -620,6 +620,14 @@ static int ssb_pci_sprom_get(struct ssb_
+ 	int err = -ENOMEM;
+ 	u16 *buf;
+ 
++	if (!ssb_is_sprom_available(bus)) {
++		ssb_printk(KERN_ERR PFX "No SPROM available!\n");
++		return -ENODEV;
++	}
++
++	bus->sprom_offset = (bus->chipco.dev->id.revision < 31) ?
++		SSB_SPROM_BASE1 : SSB_SPROM_BASE31;
++
+ 	buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
+ 	if (!buf)
+ 		goto out;
+--- a/drivers/ssb/sprom.c
++++ b/drivers/ssb/sprom.c
+@@ -175,3 +175,17 @@ const struct ssb_sprom *ssb_get_fallback
+ {
+ 	return fallback_sprom;
+ }
++
++/* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
++bool ssb_is_sprom_available(struct ssb_bus *bus)
++{
++	/* status register only exists on chipcomon rev >= 11 and we need check
++	   for >= 31 only */
++	/* this routine differs from specs as we do not access SPROM directly
++	   on PCMCIA */
++	if (bus->bustype == SSB_BUSTYPE_PCI &&
++	    bus->chipco.dev->id.revision >= 31)
++		return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
++
++	return true;
++}
+--- a/drivers/ssb/ssb_private.h
++++ b/drivers/ssb/ssb_private.h
+@@ -196,7 +196,7 @@ extern int ssb_devices_thaw(struct ssb_f
+ #ifdef CONFIG_SSB_B43_PCI_BRIDGE
+ extern int __init b43_pci_ssb_bridge_init(void);
+ extern void __exit b43_pci_ssb_bridge_exit(void);
+-#else /* CONFIG_SSB_B43_PCI_BRIDGR */
++#else /* CONFIG_SSB_B43_PCI_BRIDGE */
+ static inline int b43_pci_ssb_bridge_init(void)
+ {
+ 	return 0;
+@@ -204,6 +204,6 @@ static inline int b43_pci_ssb_bridge_ini
+ static inline void b43_pci_ssb_bridge_exit(void)
+ {
+ }
+-#endif /* CONFIG_SSB_PCIHOST */
++#endif /* CONFIG_SSB_B43_PCI_BRIDGE */
+ 
+ #endif /* LINUX_SSB_PRIVATE_H_ */
+--- a/include/linux/ssb/ssb.h
++++ b/include/linux/ssb/ssb.h
+@@ -305,6 +305,7 @@ struct ssb_bus {
+ 	/* ID information about the Chip. */
+ 	u16 chip_id;
+ 	u16 chip_rev;
++	u16 sprom_offset;
+ 	u16 sprom_size;		/* number of words in sprom */
+ 	u8 chip_package;
+ 
+@@ -394,6 +395,9 @@ extern int ssb_bus_sdiobus_register(stru
+ 
+ extern void ssb_bus_unregister(struct ssb_bus *bus);
+ 
++/* Does the device have an SPROM? */
++extern bool ssb_is_sprom_available(struct ssb_bus *bus);
++
+ /* Set a fallback SPROM.
+  * See kdoc at the function definition for complete documentation. */
+ extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
+--- a/include/linux/ssb/ssb_driver_chipcommon.h
++++ b/include/linux/ssb/ssb_driver_chipcommon.h
+@@ -53,6 +53,7 @@
+ #define  SSB_CHIPCO_CAP_64BIT		0x08000000	/* 64-bit Backplane */
+ #define  SSB_CHIPCO_CAP_PMU		0x10000000	/* PMU available (rev >= 20) */
+ #define  SSB_CHIPCO_CAP_ECI		0x20000000	/* ECI available (rev >= 20) */
++#define  SSB_CHIPCO_CAP_SPROM		0x40000000	/* SPROM present */
+ #define SSB_CHIPCO_CORECTL		0x0008
+ #define  SSB_CHIPCO_CORECTL_UARTCLK0	0x00000001	/* Drive UART with internal clock */
+ #define	 SSB_CHIPCO_CORECTL_SE		0x00000002	/* sync clk out enable (corerev >= 3) */
+@@ -385,6 +386,7 @@
+ 
+ 
+ /** Chip specific Chip-Status register contents. */
++#define SSB_CHIPCO_CHST_4322_SPROM_EXISTS	0x00000040 /* SPROM present */
+ #define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL	0x00000003
+ #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL		0 /* OTP is powered up, use def. CIS, no SPROM */
+ #define SSB_CHIPCO_CHST_4325_SPROM_SEL		1 /* OTP is powered up, SPROM is present */
+@@ -398,6 +400,18 @@
+ #define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT	4
+ #define SSB_CHIPCO_CHST_4325_PMUTOP_2B 		0x00000200 /* 1 for 2b, 0 for to 2a */
+ 
++/** Macros to determine SPROM presence based on Chip-Status register. */
++#define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) \
++	((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
++		SSB_CHIPCO_CHST_4325_OTP_SEL)
++#define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) \
++	(status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS)
++#define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) \
++	(((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
++		SSB_CHIPCO_CHST_4325_DEFCIS_SEL) && \
++	 ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
++		SSB_CHIPCO_CHST_4325_OTP_SEL))
++
+ 
+ 
+ /** Clockcontrol masks and values **/
+@@ -564,6 +578,7 @@ struct ssb_chipcommon_pmu {
+ struct ssb_chipcommon {
+ 	struct ssb_device *dev;
+ 	u32 capabilities;
++	u32 status;
+ 	/* Fast Powerup Delay constant */
+ 	u16 fast_pwrup_delay;
+ 	struct ssb_chipcommon_pmu pmu;
+--- a/include/linux/ssb/ssb_regs.h
++++ b/include/linux/ssb/ssb_regs.h
+@@ -170,26 +170,27 @@
+ #define SSB_SPROMSIZE_WORDS_R4		220
+ #define SSB_SPROMSIZE_BYTES_R123	(SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
+ #define SSB_SPROMSIZE_BYTES_R4		(SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
+-#define SSB_SPROM_BASE			0x1000
+-#define SSB_SPROM_REVISION		0x107E
++#define SSB_SPROM_BASE1			0x1000
++#define SSB_SPROM_BASE31		0x0800
++#define SSB_SPROM_REVISION		0x007E
+ #define  SSB_SPROM_REVISION_REV		0x00FF	/* SPROM Revision number */
+ #define  SSB_SPROM_REVISION_CRC		0xFF00	/* SPROM CRC8 value */
+ #define  SSB_SPROM_REVISION_CRC_SHIFT	8
+ 
+ /* SPROM Revision 1 */
+-#define SSB_SPROM1_SPID			0x1004	/* Subsystem Product ID for PCI */
+-#define SSB_SPROM1_SVID			0x1006	/* Subsystem Vendor ID for PCI */
+-#define SSB_SPROM1_PID			0x1008	/* Product ID for PCI */
+-#define SSB_SPROM1_IL0MAC		0x1048	/* 6 bytes MAC address for 802.11b/g */
+-#define SSB_SPROM1_ET0MAC		0x104E	/* 6 bytes MAC address for Ethernet */
+-#define SSB_SPROM1_ET1MAC		0x1054	/* 6 bytes MAC address for 802.11a */
+-#define SSB_SPROM1_ETHPHY		0x105A	/* Ethernet PHY settings */
++#define SSB_SPROM1_SPID			0x0004	/* Subsystem Product ID for PCI */
++#define SSB_SPROM1_SVID			0x0006	/* Subsystem Vendor ID for PCI */
++#define SSB_SPROM1_PID			0x0008	/* Product ID for PCI */
++#define SSB_SPROM1_IL0MAC		0x0048	/* 6 bytes MAC address for 802.11b/g */
++#define SSB_SPROM1_ET0MAC		0x004E	/* 6 bytes MAC address for Ethernet */
++#define SSB_SPROM1_ET1MAC		0x0054	/* 6 bytes MAC address for 802.11a */
++#define SSB_SPROM1_ETHPHY		0x005A	/* Ethernet PHY settings */
+ #define  SSB_SPROM1_ETHPHY_ET0A		0x001F	/* MII Address for enet0 */
+ #define  SSB_SPROM1_ETHPHY_ET1A		0x03E0	/* MII Address for enet1 */
+ #define  SSB_SPROM1_ETHPHY_ET1A_SHIFT	5
+ #define  SSB_SPROM1_ETHPHY_ET0M		(1<<14)	/* MDIO for enet0 */
+ #define  SSB_SPROM1_ETHPHY_ET1M		(1<<15)	/* MDIO for enet1 */
+-#define SSB_SPROM1_BINF			0x105C	/* Board info */
++#define SSB_SPROM1_BINF			0x005C	/* Board info */
+ #define  SSB_SPROM1_BINF_BREV		0x00FF	/* Board Revision */
+ #define  SSB_SPROM1_BINF_CCODE		0x0F00	/* Country Code */
+ #define  SSB_SPROM1_BINF_CCODE_SHIFT	8
+@@ -197,63 +198,63 @@
+ #define  SSB_SPROM1_BINF_ANTBG_SHIFT	12
+ #define  SSB_SPROM1_BINF_ANTA		0xC000	/* Available A-PHY antennas */
+ #define  SSB_SPROM1_BINF_ANTA_SHIFT	14
+-#define SSB_SPROM1_PA0B0		0x105E
+-#define SSB_SPROM1_PA0B1		0x1060
+-#define SSB_SPROM1_PA0B2		0x1062
+-#define SSB_SPROM1_GPIOA		0x1064	/* General Purpose IO pins 0 and 1 */
++#define SSB_SPROM1_PA0B0		0x005E
++#define SSB_SPROM1_PA0B1		0x0060
++#define SSB_SPROM1_PA0B2		0x0062
++#define SSB_SPROM1_GPIOA		0x0064	/* General Purpose IO pins 0 and 1 */
+ #define  SSB_SPROM1_GPIOA_P0		0x00FF	/* Pin 0 */
+ #define  SSB_SPROM1_GPIOA_P1		0xFF00	/* Pin 1 */
+ #define  SSB_SPROM1_GPIOA_P1_SHIFT	8
+-#define SSB_SPROM1_GPIOB		0x1066	/* General Purpuse IO pins 2 and 3 */
++#define SSB_SPROM1_GPIOB		0x0066	/* General Purpuse IO pins 2 and 3 */
+ #define  SSB_SPROM1_GPIOB_P2		0x00FF	/* Pin 2 */
+ #define  SSB_SPROM1_GPIOB_P3		0xFF00	/* Pin 3 */
+ #define  SSB_SPROM1_GPIOB_P3_SHIFT	8
+-#define SSB_SPROM1_MAXPWR		0x1068	/* Power Amplifier Max Power */
++#define SSB_SPROM1_MAXPWR		0x0068	/* Power Amplifier Max Power */
+ #define  SSB_SPROM1_MAXPWR_BG		0x00FF	/* B-PHY and G-PHY (in dBm Q5.2) */
+ #define  SSB_SPROM1_MAXPWR_A		0xFF00	/* A-PHY (in dBm Q5.2) */
+ #define  SSB_SPROM1_MAXPWR_A_SHIFT	8
+-#define SSB_SPROM1_PA1B0		0x106A
+-#define SSB_SPROM1_PA1B1		0x106C
+-#define SSB_SPROM1_PA1B2		0x106E
+-#define SSB_SPROM1_ITSSI		0x1070	/* Idle TSSI Target */
++#define SSB_SPROM1_PA1B0		0x006A
++#define SSB_SPROM1_PA1B1		0x006C
++#define SSB_SPROM1_PA1B2		0x006E
++#define SSB_SPROM1_ITSSI		0x0070	/* Idle TSSI Target */
+ #define  SSB_SPROM1_ITSSI_BG		0x00FF	/* B-PHY and G-PHY*/
+ #define  SSB_SPROM1_ITSSI_A		0xFF00	/* A-PHY */
+ #define  SSB_SPROM1_ITSSI_A_SHIFT	8
+-#define SSB_SPROM1_BFLLO		0x1072	/* Boardflags (low 16 bits) */
+-#define SSB_SPROM1_AGAIN		0x1074	/* Antenna Gain (in dBm Q5.2) */
++#define SSB_SPROM1_BFLLO		0x0072	/* Boardflags (low 16 bits) */
++#define SSB_SPROM1_AGAIN		0x0074	/* Antenna Gain (in dBm Q5.2) */
+ #define  SSB_SPROM1_AGAIN_BG		0x00FF	/* B-PHY and G-PHY */
+ #define  SSB_SPROM1_AGAIN_BG_SHIFT	0
+ #define  SSB_SPROM1_AGAIN_A		0xFF00	/* A-PHY */
+ #define  SSB_SPROM1_AGAIN_A_SHIFT	8
+ 
+ /* SPROM Revision 2 (inherits from rev 1) */
+-#define SSB_SPROM2_BFLHI		0x1038	/* Boardflags (high 16 bits) */
+-#define SSB_SPROM2_MAXP_A		0x103A	/* A-PHY Max Power */
++#define SSB_SPROM2_BFLHI		0x0038	/* Boardflags (high 16 bits) */
++#define SSB_SPROM2_MAXP_A		0x003A	/* A-PHY Max Power */
+ #define  SSB_SPROM2_MAXP_A_HI		0x00FF	/* Max Power High */
+ #define  SSB_SPROM2_MAXP_A_LO		0xFF00	/* Max Power Low */
+ #define  SSB_SPROM2_MAXP_A_LO_SHIFT	8
+-#define SSB_SPROM2_PA1LOB0		0x103C	/* A-PHY PowerAmplifier Low Settings */
+-#define SSB_SPROM2_PA1LOB1		0x103E	/* A-PHY PowerAmplifier Low Settings */
+-#define SSB_SPROM2_PA1LOB2		0x1040	/* A-PHY PowerAmplifier Low Settings */
+-#define SSB_SPROM2_PA1HIB0		0x1042	/* A-PHY PowerAmplifier High Settings */
+-#define SSB_SPROM2_PA1HIB1		0x1044	/* A-PHY PowerAmplifier High Settings */
+-#define SSB_SPROM2_PA1HIB2		0x1046	/* A-PHY PowerAmplifier High Settings */
+-#define SSB_SPROM2_OPO			0x1078	/* OFDM Power Offset from CCK Level */
++#define SSB_SPROM2_PA1LOB0		0x003C	/* A-PHY PowerAmplifier Low Settings */
++#define SSB_SPROM2_PA1LOB1		0x003E	/* A-PHY PowerAmplifier Low Settings */
++#define SSB_SPROM2_PA1LOB2		0x0040	/* A-PHY PowerAmplifier Low Settings */
++#define SSB_SPROM2_PA1HIB0		0x0042	/* A-PHY PowerAmplifier High Settings */
++#define SSB_SPROM2_PA1HIB1		0x0044	/* A-PHY PowerAmplifier High Settings */
++#define SSB_SPROM2_PA1HIB2		0x0046	/* A-PHY PowerAmplifier High Settings */
++#define SSB_SPROM2_OPO			0x0078	/* OFDM Power Offset from CCK Level */
+ #define  SSB_SPROM2_OPO_VALUE		0x00FF
+ #define  SSB_SPROM2_OPO_UNUSED		0xFF00
+-#define SSB_SPROM2_CCODE		0x107C	/* Two char Country Code */
++#define SSB_SPROM2_CCODE		0x007C	/* Two char Country Code */
+ 
+ /* SPROM Revision 3 (inherits most data from rev 2) */
+-#define SSB_SPROM3_IL0MAC		0x104A	/* 6 bytes MAC address for 802.11b/g */
+-#define SSB_SPROM3_OFDMAPO		0x102C	/* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
+-#define SSB_SPROM3_OFDMALPO		0x1030	/* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
+-#define SSB_SPROM3_OFDMAHPO		0x1034	/* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
+-#define SSB_SPROM3_GPIOLDC		0x1042	/* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
++#define SSB_SPROM3_OFDMAPO		0x002C	/* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
++#define SSB_SPROM3_OFDMALPO		0x0030	/* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
++#define SSB_SPROM3_OFDMAHPO		0x0034	/* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
++#define SSB_SPROM3_GPIOLDC		0x0042	/* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
+ #define  SSB_SPROM3_GPIOLDC_OFF		0x0000FF00	/* Off Count */
+ #define  SSB_SPROM3_GPIOLDC_OFF_SHIFT	8
+ #define  SSB_SPROM3_GPIOLDC_ON		0x00FF0000	/* On Count */
+ #define  SSB_SPROM3_GPIOLDC_ON_SHIFT	16
+-#define SSB_SPROM3_CCKPO		0x1078	/* CCK Power Offset */
++#define SSB_SPROM3_IL0MAC		0x004A	/* 6 bytes MAC address for 802.11b/g */
++#define SSB_SPROM3_CCKPO		0x0078	/* CCK Power Offset */
+ #define  SSB_SPROM3_CCKPO_1M		0x000F	/* 1M Rate PO */
+ #define  SSB_SPROM3_CCKPO_2M		0x00F0	/* 2M Rate PO */
+ #define  SSB_SPROM3_CCKPO_2M_SHIFT	4
+@@ -264,100 +265,100 @@
+ #define  SSB_SPROM3_OFDMGPO		0x107A	/* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
+ 
+ /* SPROM Revision 4 */
+-#define SSB_SPROM4_IL0MAC		0x104C	/* 6 byte MAC address for a/b/g/n */
+-#define SSB_SPROM4_ETHPHY		0x105A	/* Ethernet PHY settings ?? */
++#define SSB_SPROM4_BFLLO		0x0044	/* Boardflags (low 16 bits) */
++#define SSB_SPROM4_BFLHI		0x0046  /* Board Flags Hi */
++#define SSB_SPROM4_IL0MAC		0x004C	/* 6 byte MAC address for a/b/g/n */
++#define SSB_SPROM4_CCODE		0x0052	/* Country Code (2 bytes) */
++#define SSB_SPROM4_GPIOA		0x0056	/* Gen. Purpose IO # 0 and 1 */
++#define  SSB_SPROM4_GPIOA_P0		0x00FF	/* Pin 0 */
++#define  SSB_SPROM4_GPIOA_P1		0xFF00	/* Pin 1 */
++#define  SSB_SPROM4_GPIOA_P1_SHIFT	8
++#define SSB_SPROM4_GPIOB		0x0058	/* Gen. Purpose IO # 2 and 3 */
++#define  SSB_SPROM4_GPIOB_P2		0x00FF	/* Pin 2 */
++#define  SSB_SPROM4_GPIOB_P3		0xFF00	/* Pin 3 */
++#define  SSB_SPROM4_GPIOB_P3_SHIFT	8
++#define SSB_SPROM4_ETHPHY		0x005A	/* Ethernet PHY settings ?? */
+ #define  SSB_SPROM4_ETHPHY_ET0A		0x001F	/* MII Address for enet0 */
+ #define  SSB_SPROM4_ETHPHY_ET1A		0x03E0	/* MII Address for enet1 */
+ #define  SSB_SPROM4_ETHPHY_ET1A_SHIFT	5
+ #define  SSB_SPROM4_ETHPHY_ET0M		(1<<14)	/* MDIO for enet0 */
+ #define  SSB_SPROM4_ETHPHY_ET1M		(1<<15)	/* MDIO for enet1 */
+-#define SSB_SPROM4_CCODE		0x1052	/* Country Code (2 bytes) */
+-#define SSB_SPROM4_ANTAVAIL		0x105D  /* Antenna available bitfields */
+-#define SSB_SPROM4_ANTAVAIL_A		0x00FF	/* A-PHY bitfield */
+-#define SSB_SPROM4_ANTAVAIL_A_SHIFT	0
+-#define SSB_SPROM4_ANTAVAIL_BG		0xFF00	/* B-PHY and G-PHY bitfield */
+-#define SSB_SPROM4_ANTAVAIL_BG_SHIFT	8
+-#define SSB_SPROM4_BFLLO		0x1044	/* Boardflags (low 16 bits) */
+-#define SSB_SPROM4_AGAIN01		0x105E	/* Antenna Gain (in dBm Q5.2) */
++#define SSB_SPROM4_ANTAVAIL		0x005D  /* Antenna available bitfields */
++#define  SSB_SPROM4_ANTAVAIL_A		0x00FF	/* A-PHY bitfield */
++#define  SSB_SPROM4_ANTAVAIL_A_SHIFT	0
++#define  SSB_SPROM4_ANTAVAIL_BG		0xFF00	/* B-PHY and G-PHY bitfield */
++#define  SSB_SPROM4_ANTAVAIL_BG_SHIFT	8
++#define SSB_SPROM4_AGAIN01		0x005E	/* Antenna Gain (in dBm Q5.2) */
+ #define  SSB_SPROM4_AGAIN0		0x00FF	/* Antenna 0 */
+ #define  SSB_SPROM4_AGAIN0_SHIFT	0
+ #define  SSB_SPROM4_AGAIN1		0xFF00	/* Antenna 1 */
+ #define  SSB_SPROM4_AGAIN1_SHIFT	8
+-#define SSB_SPROM4_AGAIN23		0x1060
++#define SSB_SPROM4_AGAIN23		0x0060
+ #define  SSB_SPROM4_AGAIN2		0x00FF	/* Antenna 2 */
+ #define  SSB_SPROM4_AGAIN2_SHIFT	0
+ #define  SSB_SPROM4_AGAIN3		0xFF00	/* Antenna 3 */
+ #define  SSB_SPROM4_AGAIN3_SHIFT	8
+-#define SSB_SPROM4_BFLHI		0x1046  /* Board Flags Hi */
+-#define SSB_SPROM4_MAXP_BG		0x1080  /* Max Power BG in path 1 */
++#define SSB_SPROM4_MAXP_BG		0x0080  /* Max Power BG in path 1 */
+ #define  SSB_SPROM4_MAXP_BG_MASK	0x00FF  /* Mask for Max Power BG */
+ #define  SSB_SPROM4_ITSSI_BG		0xFF00	/* Mask for path 1 itssi_bg */
+ #define  SSB_SPROM4_ITSSI_BG_SHIFT	8
+-#define SSB_SPROM4_MAXP_A		0x108A  /* Max Power A in path 1 */
++#define SSB_SPROM4_MAXP_A		0x008A  /* Max Power A in path 1 */
+ #define  SSB_SPROM4_MAXP_A_MASK		0x00FF  /* Mask for Max Power A */
+ #define  SSB_SPROM4_ITSSI_A		0xFF00	/* Mask for path 1 itssi_a */
+ #define  SSB_SPROM4_ITSSI_A_SHIFT	8
+-#define SSB_SPROM4_GPIOA		0x1056	/* Gen. Purpose IO # 0 and 1 */
+-#define  SSB_SPROM4_GPIOA_P0		0x00FF	/* Pin 0 */
+-#define  SSB_SPROM4_GPIOA_P1		0xFF00	/* Pin 1 */
+-#define  SSB_SPROM4_GPIOA_P1_SHIFT	8
+-#define SSB_SPROM4_GPIOB		0x1058	/* Gen. Purpose IO # 2 and 3 */
+-#define  SSB_SPROM4_GPIOB_P2		0x00FF	/* Pin 2 */
+-#define  SSB_SPROM4_GPIOB_P3		0xFF00	/* Pin 3 */
+-#define  SSB_SPROM4_GPIOB_P3_SHIFT	8
+-#define SSB_SPROM4_PA0B0		0x1082	/* The paXbY locations are */
+-#define SSB_SPROM4_PA0B1		0x1084	/*   only guesses */
+-#define SSB_SPROM4_PA0B2		0x1086
+-#define SSB_SPROM4_PA1B0		0x108E
+-#define SSB_SPROM4_PA1B1		0x1090
+-#define SSB_SPROM4_PA1B2		0x1092
++#define SSB_SPROM4_PA0B0		0x0082	/* The paXbY locations are */
++#define SSB_SPROM4_PA0B1		0x0084	/*   only guesses */
++#define SSB_SPROM4_PA0B2		0x0086
++#define SSB_SPROM4_PA1B0		0x008E
++#define SSB_SPROM4_PA1B1		0x0090
++#define SSB_SPROM4_PA1B2		0x0092
+ 
+ /* SPROM Revision 5 (inherits most data from rev 4) */
+-#define SSB_SPROM5_BFLLO		0x104A	/* Boardflags (low 16 bits) */
+-#define SSB_SPROM5_BFLHI		0x104C  /* Board Flags Hi */
+-#define SSB_SPROM5_IL0MAC		0x1052	/* 6 byte MAC address for a/b/g/n */
+-#define SSB_SPROM5_CCODE		0x1044	/* Country Code (2 bytes) */
+-#define SSB_SPROM5_GPIOA		0x1076	/* Gen. Purpose IO # 0 and 1 */
++#define SSB_SPROM5_CCODE		0x0044	/* Country Code (2 bytes) */
++#define SSB_SPROM5_BFLLO		0x004A	/* Boardflags (low 16 bits) */
++#define SSB_SPROM5_BFLHI		0x004C  /* Board Flags Hi */
++#define SSB_SPROM5_IL0MAC		0x0052	/* 6 byte MAC address for a/b/g/n */
++#define SSB_SPROM5_GPIOA		0x0076	/* Gen. Purpose IO # 0 and 1 */
+ #define  SSB_SPROM5_GPIOA_P0		0x00FF	/* Pin 0 */
+ #define  SSB_SPROM5_GPIOA_P1		0xFF00	/* Pin 1 */
+ #define  SSB_SPROM5_GPIOA_P1_SHIFT	8
+-#define SSB_SPROM5_GPIOB		0x1078	/* Gen. Purpose IO # 2 and 3 */
++#define SSB_SPROM5_GPIOB		0x0078	/* Gen. Purpose IO # 2 and 3 */
+ #define  SSB_SPROM5_GPIOB_P2		0x00FF	/* Pin 2 */
+ #define  SSB_SPROM5_GPIOB_P3		0xFF00	/* Pin 3 */
+ #define  SSB_SPROM5_GPIOB_P3_SHIFT	8
+ 
+ /* SPROM Revision 8 */
+-#define SSB_SPROM8_BOARDREV		0x1082	/* Board revision */
+-#define SSB_SPROM8_BFLLO		0x1084	/* Board flags (bits 0-15) */
+-#define SSB_SPROM8_BFLHI		0x1086	/* Board flags (bits 16-31) */
+-#define SSB_SPROM8_BFL2LO		0x1088	/* Board flags (bits 32-47) */
+-#define SSB_SPROM8_BFL2HI		0x108A	/* Board flags (bits 48-63) */
+-#define SSB_SPROM8_IL0MAC		0x108C	/* 6 byte MAC address */
+-#define SSB_SPROM8_CCODE		0x1092	/* 2 byte country code */
+-#define SSB_SPROM8_ANTAVAIL		0x109C  /* Antenna available bitfields*/
+-#define SSB_SPROM8_ANTAVAIL_A		0xFF00	/* A-PHY bitfield */
+-#define SSB_SPROM8_ANTAVAIL_A_SHIFT	8
+-#define SSB_SPROM8_ANTAVAIL_BG		0x00FF	/* B-PHY and G-PHY bitfield */
+-#define SSB_SPROM8_ANTAVAIL_BG_SHIFT	0
+-#define SSB_SPROM8_AGAIN01		0x109E	/* Antenna Gain (in dBm Q5.2) */
++#define SSB_SPROM8_BOARDREV		0x0082	/* Board revision */
++#define SSB_SPROM8_BFLLO		0x0084	/* Board flags (bits 0-15) */
++#define SSB_SPROM8_BFLHI		0x0086	/* Board flags (bits 16-31) */
++#define SSB_SPROM8_BFL2LO		0x0088	/* Board flags (bits 32-47) */
++#define SSB_SPROM8_BFL2HI		0x008A	/* Board flags (bits 48-63) */
++#define SSB_SPROM8_IL0MAC		0x008C	/* 6 byte MAC address */
++#define SSB_SPROM8_CCODE		0x0092	/* 2 byte country code */
++#define SSB_SPROM8_GPIOA		0x0096	/*Gen. Purpose IO # 0 and 1 */
++#define  SSB_SPROM8_GPIOA_P0		0x00FF	/* Pin 0 */
++#define  SSB_SPROM8_GPIOA_P1		0xFF00	/* Pin 1 */
++#define  SSB_SPROM8_GPIOA_P1_SHIFT	8
++#define SSB_SPROM8_GPIOB		0x0098	/* Gen. Purpose IO # 2 and 3 */
++#define  SSB_SPROM8_GPIOB_P2		0x00FF	/* Pin 2 */
++#define  SSB_SPROM8_GPIOB_P3		0xFF00	/* Pin 3 */
++#define  SSB_SPROM8_GPIOB_P3_SHIFT	8
++#define SSB_SPROM8_ANTAVAIL		0x009C  /* Antenna available bitfields*/
++#define  SSB_SPROM8_ANTAVAIL_A		0xFF00	/* A-PHY bitfield */
++#define  SSB_SPROM8_ANTAVAIL_A_SHIFT	8
++#define  SSB_SPROM8_ANTAVAIL_BG		0x00FF	/* B-PHY and G-PHY bitfield */
++#define  SSB_SPROM8_ANTAVAIL_BG_SHIFT	0
++#define SSB_SPROM8_AGAIN01		0x009E	/* Antenna Gain (in dBm Q5.2) */
+ #define  SSB_SPROM8_AGAIN0		0x00FF	/* Antenna 0 */
+ #define  SSB_SPROM8_AGAIN0_SHIFT	0
+ #define  SSB_SPROM8_AGAIN1		0xFF00	/* Antenna 1 */
+ #define  SSB_SPROM8_AGAIN1_SHIFT	8
+-#define SSB_SPROM8_AGAIN23		0x10A0
++#define SSB_SPROM8_AGAIN23		0x00A0
+ #define  SSB_SPROM8_AGAIN2		0x00FF	/* Antenna 2 */
+ #define  SSB_SPROM8_AGAIN2_SHIFT	0
+ #define  SSB_SPROM8_AGAIN3		0xFF00	/* Antenna 3 */
+ #define  SSB_SPROM8_AGAIN3_SHIFT	8
+-#define SSB_SPROM8_GPIOA		0x1096	/*Gen. Purpose IO # 0 and 1 */
+-#define  SSB_SPROM8_GPIOA_P0		0x00FF	/* Pin 0 */
+-#define  SSB_SPROM8_GPIOA_P1		0xFF00	/* Pin 1 */
+-#define  SSB_SPROM8_GPIOA_P1_SHIFT	8
+-#define SSB_SPROM8_GPIOB		0x1098	/* Gen. Purpose IO # 2 and 3 */
+-#define  SSB_SPROM8_GPIOB_P2		0x00FF	/* Pin 2 */
+-#define  SSB_SPROM8_GPIOB_P3		0xFF00	/* Pin 3 */
+-#define  SSB_SPROM8_GPIOB_P3_SHIFT	8
+-#define SSB_SPROM8_RSSIPARM2G		0x10A4	/* RSSI params for 2GHz */
++#define SSB_SPROM8_RSSIPARM2G		0x00A4	/* RSSI params for 2GHz */
+ #define  SSB_SPROM8_RSSISMF2G		0x000F
+ #define  SSB_SPROM8_RSSISMC2G		0x00F0
+ #define  SSB_SPROM8_RSSISMC2G_SHIFT	4
+@@ -365,7 +366,7 @@
+ #define  SSB_SPROM8_RSSISAV2G_SHIFT	8
+ #define  SSB_SPROM8_BXA2G		0x1800
+ #define  SSB_SPROM8_BXA2G_SHIFT		11
+-#define SSB_SPROM8_RSSIPARM5G		0x10A6	/* RSSI params for 5GHz */
++#define SSB_SPROM8_RSSIPARM5G		0x00A6	/* RSSI params for 5GHz */
+ #define  SSB_SPROM8_RSSISMF5G		0x000F
+ #define  SSB_SPROM8_RSSISMC5G		0x00F0
+ #define  SSB_SPROM8_RSSISMC5G_SHIFT	4
+@@ -373,47 +374,47 @@
+ #define  SSB_SPROM8_RSSISAV5G_SHIFT	8
+ #define  SSB_SPROM8_BXA5G		0x1800
+ #define  SSB_SPROM8_BXA5G_SHIFT		11
+-#define SSB_SPROM8_TRI25G		0x10A8	/* TX isolation 2.4&5.3GHz */
++#define SSB_SPROM8_TRI25G		0x00A8	/* TX isolation 2.4&5.3GHz */
+ #define  SSB_SPROM8_TRI2G		0x00FF	/* TX isolation 2.4GHz */
+ #define  SSB_SPROM8_TRI5G		0xFF00	/* TX isolation 5.3GHz */
+ #define  SSB_SPROM8_TRI5G_SHIFT		8
+-#define SSB_SPROM8_TRI5GHL		0x10AA	/* TX isolation 5.2/5.8GHz */
++#define SSB_SPROM8_TRI5GHL		0x00AA	/* TX isolation 5.2/5.8GHz */
+ #define  SSB_SPROM8_TRI5GL		0x00FF	/* TX isolation 5.2GHz */
+ #define  SSB_SPROM8_TRI5GH		0xFF00	/* TX isolation 5.8GHz */
+ #define  SSB_SPROM8_TRI5GH_SHIFT	8
+-#define SSB_SPROM8_RXPO			0x10AC  /* RX power offsets */
++#define SSB_SPROM8_RXPO			0x00AC  /* RX power offsets */
+ #define  SSB_SPROM8_RXPO2G		0x00FF	/* 2GHz RX power offset */
+ #define  SSB_SPROM8_RXPO5G		0xFF00	/* 5GHz RX power offset */
+ #define  SSB_SPROM8_RXPO5G_SHIFT	8
+-#define SSB_SPROM8_MAXP_BG		0x10C0  /* Max Power 2GHz in path 1 */
++#define SSB_SPROM8_MAXP_BG		0x00C0  /* Max Power 2GHz in path 1 */
+ #define  SSB_SPROM8_MAXP_BG_MASK	0x00FF  /* Mask for Max Power 2GHz */
+ #define  SSB_SPROM8_ITSSI_BG		0xFF00	/* Mask for path 1 itssi_bg */
+ #define  SSB_SPROM8_ITSSI_BG_SHIFT	8
+-#define SSB_SPROM8_PA0B0		0x10C2	/* 2GHz power amp settings */
+-#define SSB_SPROM8_PA0B1		0x10C4
+-#define SSB_SPROM8_PA0B2		0x10C6
+-#define SSB_SPROM8_MAXP_A		0x10C8  /* Max Power 5.3GHz */
++#define SSB_SPROM8_PA0B0		0x00C2	/* 2GHz power amp settings */
++#define SSB_SPROM8_PA0B1		0x00C4
++#define SSB_SPROM8_PA0B2		0x00C6
++#define SSB_SPROM8_MAXP_A		0x00C8  /* Max Power 5.3GHz */
+ #define  SSB_SPROM8_MAXP_A_MASK		0x00FF  /* Mask for Max Power 5.3GHz */
+ #define  SSB_SPROM8_ITSSI_A		0xFF00	/* Mask for path 1 itssi_a */
+ #define  SSB_SPROM8_ITSSI_A_SHIFT	8
+-#define SSB_SPROM8_MAXP_AHL		0x10CA  /* Max Power 5.2/5.8GHz */
++#define SSB_SPROM8_MAXP_AHL		0x00CA  /* Max Power 5.2/5.8GHz */
+ #define  SSB_SPROM8_MAXP_AH_MASK	0x00FF  /* Mask for Max Power 5.8GHz */
+ #define  SSB_SPROM8_MAXP_AL_MASK	0xFF00  /* Mask for Max Power 5.2GHz */
+ #define  SSB_SPROM8_MAXP_AL_SHIFT	8
+-#define SSB_SPROM8_PA1B0		0x10CC	/* 5.3GHz power amp settings */
+-#define SSB_SPROM8_PA1B1		0x10CE
+-#define SSB_SPROM8_PA1B2		0x10D0
+-#define SSB_SPROM8_PA1LOB0		0x10D2	/* 5.2GHz power amp settings */
+-#define SSB_SPROM8_PA1LOB1		0x10D4
+-#define SSB_SPROM8_PA1LOB2		0x10D6
+-#define SSB_SPROM8_PA1HIB0		0x10D8	/* 5.8GHz power amp settings */
+-#define SSB_SPROM8_PA1HIB1		0x10DA
+-#define SSB_SPROM8_PA1HIB2		0x10DC
+-#define SSB_SPROM8_CCK2GPO		0x1140	/* CCK power offset */
+-#define SSB_SPROM8_OFDM2GPO		0x1142	/* 2.4GHz OFDM power offset */
+-#define SSB_SPROM8_OFDM5GPO		0x1146	/* 5.3GHz OFDM power offset */
+-#define SSB_SPROM8_OFDM5GLPO		0x114A	/* 5.2GHz OFDM power offset */
+-#define SSB_SPROM8_OFDM5GHPO		0x114E	/* 5.8GHz OFDM power offset */
++#define SSB_SPROM8_PA1B0		0x00CC	/* 5.3GHz power amp settings */
++#define SSB_SPROM8_PA1B1		0x00CE
++#define SSB_SPROM8_PA1B2		0x00D0
++#define SSB_SPROM8_PA1LOB0		0x00D2	/* 5.2GHz power amp settings */
++#define SSB_SPROM8_PA1LOB1		0x00D4
++#define SSB_SPROM8_PA1LOB2		0x00D6
++#define SSB_SPROM8_PA1HIB0		0x00D8	/* 5.8GHz power amp settings */
++#define SSB_SPROM8_PA1HIB1		0x00DA
++#define SSB_SPROM8_PA1HIB2		0x00DC
++#define SSB_SPROM8_CCK2GPO		0x0140	/* CCK power offset */
++#define SSB_SPROM8_OFDM2GPO		0x0142	/* 2.4GHz OFDM power offset */
++#define SSB_SPROM8_OFDM5GPO		0x0146	/* 5.3GHz OFDM power offset */
++#define SSB_SPROM8_OFDM5GLPO		0x014A	/* 5.2GHz OFDM power offset */
++#define SSB_SPROM8_OFDM5GHPO		0x014E	/* 5.8GHz OFDM power offset */
+ 
+ /* Values for SSB_SPROM1_BINF_CCODE */
+ enum {
diff --git a/target/linux/generic-2.6/patches-2.6.34/975-ssb_update.patch b/target/linux/generic-2.6/patches-2.6.34/975-ssb_update.patch
new file mode 100644
index 0000000000..ce2c487bff
--- /dev/null
+++ b/target/linux/generic-2.6/patches-2.6.34/975-ssb_update.patch
@@ -0,0 +1,530 @@
+--- a/drivers/ssb/driver_chipcommon.c
++++ b/drivers/ssb/driver_chipcommon.c
+@@ -233,6 +233,8 @@ void ssb_chipcommon_init(struct ssb_chip
+ {
+ 	if (!cc->dev)
+ 		return; /* We don't have a ChipCommon */
++	if (cc->dev->id.revision >= 11)
++		cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
+ 	ssb_pmu_init(cc);
+ 	chipco_powercontrol_init(cc);
+ 	ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
+@@ -370,6 +372,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c
+ {
+ 	return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
+ }
++EXPORT_SYMBOL(ssb_chipco_gpio_control);
+ 
+ u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
+ {
+--- a/drivers/ssb/main.c
++++ b/drivers/ssb/main.c
+@@ -834,6 +834,9 @@ int ssb_bus_pcibus_register(struct ssb_b
+ 	if (!err) {
+ 		ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
+ 			   "PCI device %s\n", dev_name(&host_pci->dev));
++	} else {
++		ssb_printk(KERN_ERR PFX "Failed to register PCI version"
++			   " of SSB with error %d\n", err);
+ 	}
+ 
+ 	return err;
+--- a/drivers/ssb/pci.c
++++ b/drivers/ssb/pci.c
+@@ -168,7 +168,7 @@ err_pci:
+ }
+ 
+ /* Get the word-offset for a SSB_SPROM_XXX define. */
+-#define SPOFF(offset)	(((offset) - SSB_SPROM_BASE) / sizeof(u16))
++#define SPOFF(offset)	((offset) / sizeof(u16))
+ /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
+ #define SPEX16(_outvar, _offset, _mask, _shift)	\
+ 	out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
+@@ -254,7 +254,7 @@ static int sprom_do_read(struct ssb_bus 
+ 	int i;
+ 
+ 	for (i = 0; i < bus->sprom_size; i++)
+-		sprom[i] = ioread16(bus->mmio + SSB_SPROM_BASE + (i * 2));
++		sprom[i] = ioread16(bus->mmio + bus->sprom_offset + (i * 2));
+ 
+ 	return 0;
+ }
+@@ -285,7 +285,7 @@ static int sprom_do_write(struct ssb_bus
+ 			ssb_printk("75%%");
+ 		else if (i % 2)
+ 			ssb_printk(".");
+-		writew(sprom[i], bus->mmio + SSB_SPROM_BASE + (i * 2));
++		writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
+ 		mmiowb();
+ 		msleep(20);
+ 	}
+@@ -621,6 +621,14 @@ static int ssb_pci_sprom_get(struct ssb_
+ 	int err = -ENOMEM;
+ 	u16 *buf;
+ 
++	if (!ssb_is_sprom_available(bus)) {
++		ssb_printk(KERN_ERR PFX "No SPROM available!\n");
++		return -ENODEV;
++	}
++
++	bus->sprom_offset = (bus->chipco.dev->id.revision < 31) ?
++		SSB_SPROM_BASE1 : SSB_SPROM_BASE31;
++
+ 	buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
+ 	if (!buf)
+ 		goto out;
+--- a/drivers/ssb/sprom.c
++++ b/drivers/ssb/sprom.c
+@@ -176,3 +176,17 @@ const struct ssb_sprom *ssb_get_fallback
+ {
+ 	return fallback_sprom;
+ }
++
++/* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
++bool ssb_is_sprom_available(struct ssb_bus *bus)
++{
++	/* status register only exists on chipcomon rev >= 11 and we need check
++	   for >= 31 only */
++	/* this routine differs from specs as we do not access SPROM directly
++	   on PCMCIA */
++	if (bus->bustype == SSB_BUSTYPE_PCI &&
++	    bus->chipco.dev->id.revision >= 31)
++		return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
++
++	return true;
++}
+--- a/include/linux/ssb/ssb.h
++++ b/include/linux/ssb/ssb.h
+@@ -305,6 +305,7 @@ struct ssb_bus {
+ 	/* ID information about the Chip. */
+ 	u16 chip_id;
+ 	u16 chip_rev;
++	u16 sprom_offset;
+ 	u16 sprom_size;		/* number of words in sprom */
+ 	u8 chip_package;
+ 
+@@ -394,6 +395,9 @@ extern int ssb_bus_sdiobus_register(stru
+ 
+ extern void ssb_bus_unregister(struct ssb_bus *bus);
+ 
++/* Does the device have an SPROM? */
++extern bool ssb_is_sprom_available(struct ssb_bus *bus);
++
+ /* Set a fallback SPROM.
+  * See kdoc at the function definition for complete documentation. */
+ extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
+--- a/include/linux/ssb/ssb_driver_chipcommon.h
++++ b/include/linux/ssb/ssb_driver_chipcommon.h
+@@ -53,6 +53,7 @@
+ #define  SSB_CHIPCO_CAP_64BIT		0x08000000	/* 64-bit Backplane */
+ #define  SSB_CHIPCO_CAP_PMU		0x10000000	/* PMU available (rev >= 20) */
+ #define  SSB_CHIPCO_CAP_ECI		0x20000000	/* ECI available (rev >= 20) */
++#define  SSB_CHIPCO_CAP_SPROM		0x40000000	/* SPROM present */
+ #define SSB_CHIPCO_CORECTL		0x0008
+ #define  SSB_CHIPCO_CORECTL_UARTCLK0	0x00000001	/* Drive UART with internal clock */
+ #define	 SSB_CHIPCO_CORECTL_SE		0x00000002	/* sync clk out enable (corerev >= 3) */
+@@ -385,6 +386,7 @@
+ 
+ 
+ /** Chip specific Chip-Status register contents. */
++#define SSB_CHIPCO_CHST_4322_SPROM_EXISTS	0x00000040 /* SPROM present */
+ #define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL	0x00000003
+ #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL		0 /* OTP is powered up, use def. CIS, no SPROM */
+ #define SSB_CHIPCO_CHST_4325_SPROM_SEL		1 /* OTP is powered up, SPROM is present */
+@@ -398,6 +400,18 @@
+ #define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT	4
+ #define SSB_CHIPCO_CHST_4325_PMUTOP_2B 		0x00000200 /* 1 for 2b, 0 for to 2a */
+ 
++/** Macros to determine SPROM presence based on Chip-Status register. */
++#define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) \
++	((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
++		SSB_CHIPCO_CHST_4325_OTP_SEL)
++#define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) \
++	(status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS)
++#define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) \
++	(((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
++		SSB_CHIPCO_CHST_4325_DEFCIS_SEL) && \
++	 ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
++		SSB_CHIPCO_CHST_4325_OTP_SEL))
++
+ 
+ 
+ /** Clockcontrol masks and values **/
+@@ -564,6 +578,7 @@ struct ssb_chipcommon_pmu {
+ struct ssb_chipcommon {
+ 	struct ssb_device *dev;
+ 	u32 capabilities;
++	u32 status;
+ 	/* Fast Powerup Delay constant */
+ 	u16 fast_pwrup_delay;
+ 	struct ssb_chipcommon_pmu pmu;
+--- a/include/linux/ssb/ssb_regs.h
++++ b/include/linux/ssb/ssb_regs.h
+@@ -170,26 +170,27 @@
+ #define SSB_SPROMSIZE_WORDS_R4		220
+ #define SSB_SPROMSIZE_BYTES_R123	(SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
+ #define SSB_SPROMSIZE_BYTES_R4		(SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
+-#define SSB_SPROM_BASE			0x1000
+-#define SSB_SPROM_REVISION		0x107E
++#define SSB_SPROM_BASE1			0x1000
++#define SSB_SPROM_BASE31		0x0800
++#define SSB_SPROM_REVISION		0x007E
+ #define  SSB_SPROM_REVISION_REV		0x00FF	/* SPROM Revision number */
+ #define  SSB_SPROM_REVISION_CRC		0xFF00	/* SPROM CRC8 value */
+ #define  SSB_SPROM_REVISION_CRC_SHIFT	8
+ 
+ /* SPROM Revision 1 */
+-#define SSB_SPROM1_SPID			0x1004	/* Subsystem Product ID for PCI */
+-#define SSB_SPROM1_SVID			0x1006	/* Subsystem Vendor ID for PCI */
+-#define SSB_SPROM1_PID			0x1008	/* Product ID for PCI */
+-#define SSB_SPROM1_IL0MAC		0x1048	/* 6 bytes MAC address for 802.11b/g */
+-#define SSB_SPROM1_ET0MAC		0x104E	/* 6 bytes MAC address for Ethernet */
+-#define SSB_SPROM1_ET1MAC		0x1054	/* 6 bytes MAC address for 802.11a */
+-#define SSB_SPROM1_ETHPHY		0x105A	/* Ethernet PHY settings */
++#define SSB_SPROM1_SPID			0x0004	/* Subsystem Product ID for PCI */
++#define SSB_SPROM1_SVID			0x0006	/* Subsystem Vendor ID for PCI */
++#define SSB_SPROM1_PID			0x0008	/* Product ID for PCI */
++#define SSB_SPROM1_IL0MAC		0x0048	/* 6 bytes MAC address for 802.11b/g */
++#define SSB_SPROM1_ET0MAC		0x004E	/* 6 bytes MAC address for Ethernet */
++#define SSB_SPROM1_ET1MAC		0x0054	/* 6 bytes MAC address for 802.11a */
++#define SSB_SPROM1_ETHPHY		0x005A	/* Ethernet PHY settings */
+ #define  SSB_SPROM1_ETHPHY_ET0A		0x001F	/* MII Address for enet0 */
+ #define  SSB_SPROM1_ETHPHY_ET1A		0x03E0	/* MII Address for enet1 */
+ #define  SSB_SPROM1_ETHPHY_ET1A_SHIFT	5
+ #define  SSB_SPROM1_ETHPHY_ET0M		(1<<14)	/* MDIO for enet0 */
+ #define  SSB_SPROM1_ETHPHY_ET1M		(1<<15)	/* MDIO for enet1 */
+-#define SSB_SPROM1_BINF			0x105C	/* Board info */
++#define SSB_SPROM1_BINF			0x005C	/* Board info */
+ #define  SSB_SPROM1_BINF_BREV		0x00FF	/* Board Revision */
+ #define  SSB_SPROM1_BINF_CCODE		0x0F00	/* Country Code */
+ #define  SSB_SPROM1_BINF_CCODE_SHIFT	8
+@@ -197,63 +198,63 @@
+ #define  SSB_SPROM1_BINF_ANTBG_SHIFT	12
+ #define  SSB_SPROM1_BINF_ANTA		0xC000	/* Available A-PHY antennas */
+ #define  SSB_SPROM1_BINF_ANTA_SHIFT	14
+-#define SSB_SPROM1_PA0B0		0x105E
+-#define SSB_SPROM1_PA0B1		0x1060
+-#define SSB_SPROM1_PA0B2		0x1062
+-#define SSB_SPROM1_GPIOA		0x1064	/* General Purpose IO pins 0 and 1 */
++#define SSB_SPROM1_PA0B0		0x005E
++#define SSB_SPROM1_PA0B1		0x0060
++#define SSB_SPROM1_PA0B2		0x0062
++#define SSB_SPROM1_GPIOA		0x0064	/* General Purpose IO pins 0 and 1 */
+ #define  SSB_SPROM1_GPIOA_P0		0x00FF	/* Pin 0 */
+ #define  SSB_SPROM1_GPIOA_P1		0xFF00	/* Pin 1 */
+ #define  SSB_SPROM1_GPIOA_P1_SHIFT	8
+-#define SSB_SPROM1_GPIOB		0x1066	/* General Purpuse IO pins 2 and 3 */
++#define SSB_SPROM1_GPIOB		0x0066	/* General Purpuse IO pins 2 and 3 */
+ #define  SSB_SPROM1_GPIOB_P2		0x00FF	/* Pin 2 */
+ #define  SSB_SPROM1_GPIOB_P3		0xFF00	/* Pin 3 */
+ #define  SSB_SPROM1_GPIOB_P3_SHIFT	8
+-#define SSB_SPROM1_MAXPWR		0x1068	/* Power Amplifier Max Power */
++#define SSB_SPROM1_MAXPWR		0x0068	/* Power Amplifier Max Power */
+ #define  SSB_SPROM1_MAXPWR_BG		0x00FF	/* B-PHY and G-PHY (in dBm Q5.2) */
+ #define  SSB_SPROM1_MAXPWR_A		0xFF00	/* A-PHY (in dBm Q5.2) */
+ #define  SSB_SPROM1_MAXPWR_A_SHIFT	8
+-#define SSB_SPROM1_PA1B0		0x106A
+-#define SSB_SPROM1_PA1B1		0x106C
+-#define SSB_SPROM1_PA1B2		0x106E
+-#define SSB_SPROM1_ITSSI		0x1070	/* Idle TSSI Target */
++#define SSB_SPROM1_PA1B0		0x006A
++#define SSB_SPROM1_PA1B1		0x006C
++#define SSB_SPROM1_PA1B2		0x006E
++#define SSB_SPROM1_ITSSI		0x0070	/* Idle TSSI Target */
+ #define  SSB_SPROM1_ITSSI_BG		0x00FF	/* B-PHY and G-PHY*/
+ #define  SSB_SPROM1_ITSSI_A		0xFF00	/* A-PHY */
+ #define  SSB_SPROM1_ITSSI_A_SHIFT	8
+-#define SSB_SPROM1_BFLLO		0x1072	/* Boardflags (low 16 bits) */
+-#define SSB_SPROM1_AGAIN		0x1074	/* Antenna Gain (in dBm Q5.2) */
++#define SSB_SPROM1_BFLLO		0x0072	/* Boardflags (low 16 bits) */
++#define SSB_SPROM1_AGAIN		0x0074	/* Antenna Gain (in dBm Q5.2) */
+ #define  SSB_SPROM1_AGAIN_BG		0x00FF	/* B-PHY and G-PHY */
+ #define  SSB_SPROM1_AGAIN_BG_SHIFT	0
+ #define  SSB_SPROM1_AGAIN_A		0xFF00	/* A-PHY */
+ #define  SSB_SPROM1_AGAIN_A_SHIFT	8
+ 
+ /* SPROM Revision 2 (inherits from rev 1) */
+-#define SSB_SPROM2_BFLHI		0x1038	/* Boardflags (high 16 bits) */
+-#define SSB_SPROM2_MAXP_A		0x103A	/* A-PHY Max Power */
++#define SSB_SPROM2_BFLHI		0x0038	/* Boardflags (high 16 bits) */
++#define SSB_SPROM2_MAXP_A		0x003A	/* A-PHY Max Power */
+ #define  SSB_SPROM2_MAXP_A_HI		0x00FF	/* Max Power High */
+ #define  SSB_SPROM2_MAXP_A_LO		0xFF00	/* Max Power Low */
+ #define  SSB_SPROM2_MAXP_A_LO_SHIFT	8
+-#define SSB_SPROM2_PA1LOB0		0x103C	/* A-PHY PowerAmplifier Low Settings */
+-#define SSB_SPROM2_PA1LOB1		0x103E	/* A-PHY PowerAmplifier Low Settings */
+-#define SSB_SPROM2_PA1LOB2		0x1040	/* A-PHY PowerAmplifier Low Settings */
+-#define SSB_SPROM2_PA1HIB0		0x1042	/* A-PHY PowerAmplifier High Settings */
+-#define SSB_SPROM2_PA1HIB1		0x1044	/* A-PHY PowerAmplifier High Settings */
+-#define SSB_SPROM2_PA1HIB2		0x1046	/* A-PHY PowerAmplifier High Settings */
+-#define SSB_SPROM2_OPO			0x1078	/* OFDM Power Offset from CCK Level */
++#define SSB_SPROM2_PA1LOB0		0x003C	/* A-PHY PowerAmplifier Low Settings */
++#define SSB_SPROM2_PA1LOB1		0x003E	/* A-PHY PowerAmplifier Low Settings */
++#define SSB_SPROM2_PA1LOB2		0x0040	/* A-PHY PowerAmplifier Low Settings */
++#define SSB_SPROM2_PA1HIB0		0x0042	/* A-PHY PowerAmplifier High Settings */
++#define SSB_SPROM2_PA1HIB1		0x0044	/* A-PHY PowerAmplifier High Settings */
++#define SSB_SPROM2_PA1HIB2		0x0046	/* A-PHY PowerAmplifier High Settings */
++#define SSB_SPROM2_OPO			0x0078	/* OFDM Power Offset from CCK Level */
+ #define  SSB_SPROM2_OPO_VALUE		0x00FF
+ #define  SSB_SPROM2_OPO_UNUSED		0xFF00
+-#define SSB_SPROM2_CCODE		0x107C	/* Two char Country Code */
++#define SSB_SPROM2_CCODE		0x007C	/* Two char Country Code */
+ 
+ /* SPROM Revision 3 (inherits most data from rev 2) */
+-#define SSB_SPROM3_IL0MAC		0x104A	/* 6 bytes MAC address for 802.11b/g */
+-#define SSB_SPROM3_OFDMAPO		0x102C	/* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
+-#define SSB_SPROM3_OFDMALPO		0x1030	/* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
+-#define SSB_SPROM3_OFDMAHPO		0x1034	/* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
+-#define SSB_SPROM3_GPIOLDC		0x1042	/* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
++#define SSB_SPROM3_OFDMAPO		0x002C	/* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
++#define SSB_SPROM3_OFDMALPO		0x0030	/* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
++#define SSB_SPROM3_OFDMAHPO		0x0034	/* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
++#define SSB_SPROM3_GPIOLDC		0x0042	/* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
+ #define  SSB_SPROM3_GPIOLDC_OFF		0x0000FF00	/* Off Count */
+ #define  SSB_SPROM3_GPIOLDC_OFF_SHIFT	8
+ #define  SSB_SPROM3_GPIOLDC_ON		0x00FF0000	/* On Count */
+ #define  SSB_SPROM3_GPIOLDC_ON_SHIFT	16
+-#define SSB_SPROM3_CCKPO		0x1078	/* CCK Power Offset */
++#define SSB_SPROM3_IL0MAC		0x004A	/* 6 bytes MAC address for 802.11b/g */
++#define SSB_SPROM3_CCKPO		0x0078	/* CCK Power Offset */
+ #define  SSB_SPROM3_CCKPO_1M		0x000F	/* 1M Rate PO */
+ #define  SSB_SPROM3_CCKPO_2M		0x00F0	/* 2M Rate PO */
+ #define  SSB_SPROM3_CCKPO_2M_SHIFT	4
+@@ -264,100 +265,100 @@
+ #define  SSB_SPROM3_OFDMGPO		0x107A	/* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
+ 
+ /* SPROM Revision 4 */
+-#define SSB_SPROM4_IL0MAC		0x104C	/* 6 byte MAC address for a/b/g/n */
+-#define SSB_SPROM4_ETHPHY		0x105A	/* Ethernet PHY settings ?? */
++#define SSB_SPROM4_BFLLO		0x0044	/* Boardflags (low 16 bits) */
++#define SSB_SPROM4_BFLHI		0x0046  /* Board Flags Hi */
++#define SSB_SPROM4_IL0MAC		0x004C	/* 6 byte MAC address for a/b/g/n */
++#define SSB_SPROM4_CCODE		0x0052	/* Country Code (2 bytes) */
++#define SSB_SPROM4_GPIOA		0x0056	/* Gen. Purpose IO # 0 and 1 */
++#define  SSB_SPROM4_GPIOA_P0		0x00FF	/* Pin 0 */
++#define  SSB_SPROM4_GPIOA_P1		0xFF00	/* Pin 1 */
++#define  SSB_SPROM4_GPIOA_P1_SHIFT	8
++#define SSB_SPROM4_GPIOB		0x0058	/* Gen. Purpose IO # 2 and 3 */
++#define  SSB_SPROM4_GPIOB_P2		0x00FF	/* Pin 2 */
++#define  SSB_SPROM4_GPIOB_P3		0xFF00	/* Pin 3 */
++#define  SSB_SPROM4_GPIOB_P3_SHIFT	8
++#define SSB_SPROM4_ETHPHY		0x005A	/* Ethernet PHY settings ?? */
+ #define  SSB_SPROM4_ETHPHY_ET0A		0x001F	/* MII Address for enet0 */
+ #define  SSB_SPROM4_ETHPHY_ET1A		0x03E0	/* MII Address for enet1 */
+ #define  SSB_SPROM4_ETHPHY_ET1A_SHIFT	5
+ #define  SSB_SPROM4_ETHPHY_ET0M		(1<<14)	/* MDIO for enet0 */
+ #define  SSB_SPROM4_ETHPHY_ET1M		(1<<15)	/* MDIO for enet1 */
+-#define SSB_SPROM4_CCODE		0x1052	/* Country Code (2 bytes) */
+-#define SSB_SPROM4_ANTAVAIL		0x105D  /* Antenna available bitfields */
+-#define SSB_SPROM4_ANTAVAIL_A		0x00FF	/* A-PHY bitfield */
+-#define SSB_SPROM4_ANTAVAIL_A_SHIFT	0
+-#define SSB_SPROM4_ANTAVAIL_BG		0xFF00	/* B-PHY and G-PHY bitfield */
+-#define SSB_SPROM4_ANTAVAIL_BG_SHIFT	8
+-#define SSB_SPROM4_BFLLO		0x1044	/* Boardflags (low 16 bits) */
+-#define SSB_SPROM4_AGAIN01		0x105E	/* Antenna Gain (in dBm Q5.2) */
++#define SSB_SPROM4_ANTAVAIL		0x005D  /* Antenna available bitfields */
++#define  SSB_SPROM4_ANTAVAIL_A		0x00FF	/* A-PHY bitfield */
++#define  SSB_SPROM4_ANTAVAIL_A_SHIFT	0
++#define  SSB_SPROM4_ANTAVAIL_BG		0xFF00	/* B-PHY and G-PHY bitfield */
++#define  SSB_SPROM4_ANTAVAIL_BG_SHIFT	8
++#define SSB_SPROM4_AGAIN01		0x005E	/* Antenna Gain (in dBm Q5.2) */
+ #define  SSB_SPROM4_AGAIN0		0x00FF	/* Antenna 0 */
+ #define  SSB_SPROM4_AGAIN0_SHIFT	0
+ #define  SSB_SPROM4_AGAIN1		0xFF00	/* Antenna 1 */
+ #define  SSB_SPROM4_AGAIN1_SHIFT	8
+-#define SSB_SPROM4_AGAIN23		0x1060
++#define SSB_SPROM4_AGAIN23		0x0060
+ #define  SSB_SPROM4_AGAIN2		0x00FF	/* Antenna 2 */
+ #define  SSB_SPROM4_AGAIN2_SHIFT	0
+ #define  SSB_SPROM4_AGAIN3		0xFF00	/* Antenna 3 */
+ #define  SSB_SPROM4_AGAIN3_SHIFT	8
+-#define SSB_SPROM4_BFLHI		0x1046  /* Board Flags Hi */
+-#define SSB_SPROM4_MAXP_BG		0x1080  /* Max Power BG in path 1 */
++#define SSB_SPROM4_MAXP_BG		0x0080  /* Max Power BG in path 1 */
+ #define  SSB_SPROM4_MAXP_BG_MASK	0x00FF  /* Mask for Max Power BG */
+ #define  SSB_SPROM4_ITSSI_BG		0xFF00	/* Mask for path 1 itssi_bg */
+ #define  SSB_SPROM4_ITSSI_BG_SHIFT	8
+-#define SSB_SPROM4_MAXP_A		0x108A  /* Max Power A in path 1 */
++#define SSB_SPROM4_MAXP_A		0x008A  /* Max Power A in path 1 */
+ #define  SSB_SPROM4_MAXP_A_MASK		0x00FF  /* Mask for Max Power A */
+ #define  SSB_SPROM4_ITSSI_A		0xFF00	/* Mask for path 1 itssi_a */
+ #define  SSB_SPROM4_ITSSI_A_SHIFT	8
+-#define SSB_SPROM4_GPIOA		0x1056	/* Gen. Purpose IO # 0 and 1 */
+-#define  SSB_SPROM4_GPIOA_P0		0x00FF	/* Pin 0 */
+-#define  SSB_SPROM4_GPIOA_P1		0xFF00	/* Pin 1 */
+-#define  SSB_SPROM4_GPIOA_P1_SHIFT	8
+-#define SSB_SPROM4_GPIOB		0x1058	/* Gen. Purpose IO # 2 and 3 */
+-#define  SSB_SPROM4_GPIOB_P2		0x00FF	/* Pin 2 */
+-#define  SSB_SPROM4_GPIOB_P3		0xFF00	/* Pin 3 */
+-#define  SSB_SPROM4_GPIOB_P3_SHIFT	8
+-#define SSB_SPROM4_PA0B0		0x1082	/* The paXbY locations are */
+-#define SSB_SPROM4_PA0B1		0x1084	/*   only guesses */
+-#define SSB_SPROM4_PA0B2		0x1086
+-#define SSB_SPROM4_PA1B0		0x108E
+-#define SSB_SPROM4_PA1B1		0x1090
+-#define SSB_SPROM4_PA1B2		0x1092
++#define SSB_SPROM4_PA0B0		0x0082	/* The paXbY locations are */
++#define SSB_SPROM4_PA0B1		0x0084	/*   only guesses */
++#define SSB_SPROM4_PA0B2		0x0086
++#define SSB_SPROM4_PA1B0		0x008E
++#define SSB_SPROM4_PA1B1		0x0090
++#define SSB_SPROM4_PA1B2		0x0092
+ 
+ /* SPROM Revision 5 (inherits most data from rev 4) */
+-#define SSB_SPROM5_BFLLO		0x104A	/* Boardflags (low 16 bits) */
+-#define SSB_SPROM5_BFLHI		0x104C  /* Board Flags Hi */
+-#define SSB_SPROM5_IL0MAC		0x1052	/* 6 byte MAC address for a/b/g/n */
+-#define SSB_SPROM5_CCODE		0x1044	/* Country Code (2 bytes) */
+-#define SSB_SPROM5_GPIOA		0x1076	/* Gen. Purpose IO # 0 and 1 */
++#define SSB_SPROM5_CCODE		0x0044	/* Country Code (2 bytes) */
++#define SSB_SPROM5_BFLLO		0x004A	/* Boardflags (low 16 bits) */
++#define SSB_SPROM5_BFLHI		0x004C  /* Board Flags Hi */
++#define SSB_SPROM5_IL0MAC		0x0052	/* 6 byte MAC address for a/b/g/n */
++#define SSB_SPROM5_GPIOA		0x0076	/* Gen. Purpose IO # 0 and 1 */
+ #define  SSB_SPROM5_GPIOA_P0		0x00FF	/* Pin 0 */
+ #define  SSB_SPROM5_GPIOA_P1		0xFF00	/* Pin 1 */
+ #define  SSB_SPROM5_GPIOA_P1_SHIFT	8
+-#define SSB_SPROM5_GPIOB		0x1078	/* Gen. Purpose IO # 2 and 3 */
++#define SSB_SPROM5_GPIOB		0x0078	/* Gen. Purpose IO # 2 and 3 */
+ #define  SSB_SPROM5_GPIOB_P2		0x00FF	/* Pin 2 */
+ #define  SSB_SPROM5_GPIOB_P3		0xFF00	/* Pin 3 */
+ #define  SSB_SPROM5_GPIOB_P3_SHIFT	8
+ 
+ /* SPROM Revision 8 */
+-#define SSB_SPROM8_BOARDREV		0x1082	/* Board revision */
+-#define SSB_SPROM8_BFLLO		0x1084	/* Board flags (bits 0-15) */
+-#define SSB_SPROM8_BFLHI		0x1086	/* Board flags (bits 16-31) */
+-#define SSB_SPROM8_BFL2LO		0x1088	/* Board flags (bits 32-47) */
+-#define SSB_SPROM8_BFL2HI		0x108A	/* Board flags (bits 48-63) */
+-#define SSB_SPROM8_IL0MAC		0x108C	/* 6 byte MAC address */
+-#define SSB_SPROM8_CCODE		0x1092	/* 2 byte country code */
+-#define SSB_SPROM8_ANTAVAIL		0x109C  /* Antenna available bitfields*/
+-#define SSB_SPROM8_ANTAVAIL_A		0xFF00	/* A-PHY bitfield */
+-#define SSB_SPROM8_ANTAVAIL_A_SHIFT	8
+-#define SSB_SPROM8_ANTAVAIL_BG		0x00FF	/* B-PHY and G-PHY bitfield */
+-#define SSB_SPROM8_ANTAVAIL_BG_SHIFT	0
+-#define SSB_SPROM8_AGAIN01		0x109E	/* Antenna Gain (in dBm Q5.2) */
++#define SSB_SPROM8_BOARDREV		0x0082	/* Board revision */
++#define SSB_SPROM8_BFLLO		0x0084	/* Board flags (bits 0-15) */
++#define SSB_SPROM8_BFLHI		0x0086	/* Board flags (bits 16-31) */
++#define SSB_SPROM8_BFL2LO		0x0088	/* Board flags (bits 32-47) */
++#define SSB_SPROM8_BFL2HI		0x008A	/* Board flags (bits 48-63) */
++#define SSB_SPROM8_IL0MAC		0x008C	/* 6 byte MAC address */
++#define SSB_SPROM8_CCODE		0x0092	/* 2 byte country code */
++#define SSB_SPROM8_GPIOA		0x0096	/*Gen. Purpose IO # 0 and 1 */
++#define  SSB_SPROM8_GPIOA_P0		0x00FF	/* Pin 0 */
++#define  SSB_SPROM8_GPIOA_P1		0xFF00	/* Pin 1 */
++#define  SSB_SPROM8_GPIOA_P1_SHIFT	8
++#define SSB_SPROM8_GPIOB		0x0098	/* Gen. Purpose IO # 2 and 3 */
++#define  SSB_SPROM8_GPIOB_P2		0x00FF	/* Pin 2 */
++#define  SSB_SPROM8_GPIOB_P3		0xFF00	/* Pin 3 */
++#define  SSB_SPROM8_GPIOB_P3_SHIFT	8
++#define SSB_SPROM8_ANTAVAIL		0x009C  /* Antenna available bitfields*/
++#define  SSB_SPROM8_ANTAVAIL_A		0xFF00	/* A-PHY bitfield */
++#define  SSB_SPROM8_ANTAVAIL_A_SHIFT	8
++#define  SSB_SPROM8_ANTAVAIL_BG		0x00FF	/* B-PHY and G-PHY bitfield */
++#define  SSB_SPROM8_ANTAVAIL_BG_SHIFT	0
++#define SSB_SPROM8_AGAIN01		0x009E	/* Antenna Gain (in dBm Q5.2) */
+ #define  SSB_SPROM8_AGAIN0		0x00FF	/* Antenna 0 */
+ #define  SSB_SPROM8_AGAIN0_SHIFT	0
+ #define  SSB_SPROM8_AGAIN1		0xFF00	/* Antenna 1 */
+ #define  SSB_SPROM8_AGAIN1_SHIFT	8
+-#define SSB_SPROM8_AGAIN23		0x10A0
++#define SSB_SPROM8_AGAIN23		0x00A0
+ #define  SSB_SPROM8_AGAIN2		0x00FF	/* Antenna 2 */
+ #define  SSB_SPROM8_AGAIN2_SHIFT	0
+ #define  SSB_SPROM8_AGAIN3		0xFF00	/* Antenna 3 */
+ #define  SSB_SPROM8_AGAIN3_SHIFT	8
+-#define SSB_SPROM8_GPIOA		0x1096	/*Gen. Purpose IO # 0 and 1 */
+-#define  SSB_SPROM8_GPIOA_P0		0x00FF	/* Pin 0 */
+-#define  SSB_SPROM8_GPIOA_P1		0xFF00	/* Pin 1 */
+-#define  SSB_SPROM8_GPIOA_P1_SHIFT	8
+-#define SSB_SPROM8_GPIOB		0x1098	/* Gen. Purpose IO # 2 and 3 */
+-#define  SSB_SPROM8_GPIOB_P2		0x00FF	/* Pin 2 */
+-#define  SSB_SPROM8_GPIOB_P3		0xFF00	/* Pin 3 */
+-#define  SSB_SPROM8_GPIOB_P3_SHIFT	8
+-#define SSB_SPROM8_RSSIPARM2G		0x10A4	/* RSSI params for 2GHz */
++#define SSB_SPROM8_RSSIPARM2G		0x00A4	/* RSSI params for 2GHz */
+ #define  SSB_SPROM8_RSSISMF2G		0x000F
+ #define  SSB_SPROM8_RSSISMC2G		0x00F0
+ #define  SSB_SPROM8_RSSISMC2G_SHIFT	4
+@@ -365,7 +366,7 @@
+ #define  SSB_SPROM8_RSSISAV2G_SHIFT	8
+ #define  SSB_SPROM8_BXA2G		0x1800
+ #define  SSB_SPROM8_BXA2G_SHIFT		11
+-#define SSB_SPROM8_RSSIPARM5G		0x10A6	/* RSSI params for 5GHz */
++#define SSB_SPROM8_RSSIPARM5G		0x00A6	/* RSSI params for 5GHz */
+ #define  SSB_SPROM8_RSSISMF5G		0x000F
+ #define  SSB_SPROM8_RSSISMC5G		0x00F0
+ #define  SSB_SPROM8_RSSISMC5G_SHIFT	4
+@@ -373,47 +374,47 @@
+ #define  SSB_SPROM8_RSSISAV5G_SHIFT	8
+ #define  SSB_SPROM8_BXA5G		0x1800
+ #define  SSB_SPROM8_BXA5G_SHIFT		11
+-#define SSB_SPROM8_TRI25G		0x10A8	/* TX isolation 2.4&5.3GHz */
++#define SSB_SPROM8_TRI25G		0x00A8	/* TX isolation 2.4&5.3GHz */
+ #define  SSB_SPROM8_TRI2G		0x00FF	/* TX isolation 2.4GHz */
+ #define  SSB_SPROM8_TRI5G		0xFF00	/* TX isolation 5.3GHz */
+ #define  SSB_SPROM8_TRI5G_SHIFT		8
+-#define SSB_SPROM8_TRI5GHL		0x10AA	/* TX isolation 5.2/5.8GHz */
++#define SSB_SPROM8_TRI5GHL		0x00AA	/* TX isolation 5.2/5.8GHz */
+ #define  SSB_SPROM8_TRI5GL		0x00FF	/* TX isolation 5.2GHz */
+ #define  SSB_SPROM8_TRI5GH		0xFF00	/* TX isolation 5.8GHz */
+ #define  SSB_SPROM8_TRI5GH_SHIFT	8
+-#define SSB_SPROM8_RXPO			0x10AC  /* RX power offsets */
++#define SSB_SPROM8_RXPO			0x00AC  /* RX power offsets */
+ #define  SSB_SPROM8_RXPO2G		0x00FF	/* 2GHz RX power offset */
+ #define  SSB_SPROM8_RXPO5G		0xFF00	/* 5GHz RX power offset */
+ #define  SSB_SPROM8_RXPO5G_SHIFT	8
+-#define SSB_SPROM8_MAXP_BG		0x10C0  /* Max Power 2GHz in path 1 */
++#define SSB_SPROM8_MAXP_BG		0x00C0  /* Max Power 2GHz in path 1 */
+ #define  SSB_SPROM8_MAXP_BG_MASK	0x00FF  /* Mask for Max Power 2GHz */
+ #define  SSB_SPROM8_ITSSI_BG		0xFF00	/* Mask for path 1 itssi_bg */
+ #define  SSB_SPROM8_ITSSI_BG_SHIFT	8
+-#define SSB_SPROM8_PA0B0		0x10C2	/* 2GHz power amp settings */
+-#define SSB_SPROM8_PA0B1		0x10C4
+-#define SSB_SPROM8_PA0B2		0x10C6
+-#define SSB_SPROM8_MAXP_A		0x10C8  /* Max Power 5.3GHz */
++#define SSB_SPROM8_PA0B0		0x00C2	/* 2GHz power amp settings */
++#define SSB_SPROM8_PA0B1		0x00C4
++#define SSB_SPROM8_PA0B2		0x00C6
++#define SSB_SPROM8_MAXP_A		0x00C8  /* Max Power 5.3GHz */
+ #define  SSB_SPROM8_MAXP_A_MASK		0x00FF  /* Mask for Max Power 5.3GHz */
+ #define  SSB_SPROM8_ITSSI_A		0xFF00	/* Mask for path 1 itssi_a */
+ #define  SSB_SPROM8_ITSSI_A_SHIFT	8
+-#define SSB_SPROM8_MAXP_AHL		0x10CA  /* Max Power 5.2/5.8GHz */
++#define SSB_SPROM8_MAXP_AHL		0x00CA  /* Max Power 5.2/5.8GHz */
+ #define  SSB_SPROM8_MAXP_AH_MASK	0x00FF  /* Mask for Max Power 5.8GHz */
+ #define  SSB_SPROM8_MAXP_AL_MASK	0xFF00  /* Mask for Max Power 5.2GHz */
+ #define  SSB_SPROM8_MAXP_AL_SHIFT	8
+-#define SSB_SPROM8_PA1B0		0x10CC	/* 5.3GHz power amp settings */
+-#define SSB_SPROM8_PA1B1		0x10CE
+-#define SSB_SPROM8_PA1B2		0x10D0
+-#define SSB_SPROM8_PA1LOB0		0x10D2	/* 5.2GHz power amp settings */
+-#define SSB_SPROM8_PA1LOB1		0x10D4
+-#define SSB_SPROM8_PA1LOB2		0x10D6
+-#define SSB_SPROM8_PA1HIB0		0x10D8	/* 5.8GHz power amp settings */
+-#define SSB_SPROM8_PA1HIB1		0x10DA
+-#define SSB_SPROM8_PA1HIB2		0x10DC
+-#define SSB_SPROM8_CCK2GPO		0x1140	/* CCK power offset */
+-#define SSB_SPROM8_OFDM2GPO		0x1142	/* 2.4GHz OFDM power offset */
+-#define SSB_SPROM8_OFDM5GPO		0x1146	/* 5.3GHz OFDM power offset */
+-#define SSB_SPROM8_OFDM5GLPO		0x114A	/* 5.2GHz OFDM power offset */
+-#define SSB_SPROM8_OFDM5GHPO		0x114E	/* 5.8GHz OFDM power offset */
++#define SSB_SPROM8_PA1B0		0x00CC	/* 5.3GHz power amp settings */
++#define SSB_SPROM8_PA1B1		0x00CE
++#define SSB_SPROM8_PA1B2		0x00D0
++#define SSB_SPROM8_PA1LOB0		0x00D2	/* 5.2GHz power amp settings */
++#define SSB_SPROM8_PA1LOB1		0x00D4
++#define SSB_SPROM8_PA1LOB2		0x00D6
++#define SSB_SPROM8_PA1HIB0		0x00D8	/* 5.8GHz power amp settings */
++#define SSB_SPROM8_PA1HIB1		0x00DA
++#define SSB_SPROM8_PA1HIB2		0x00DC
++#define SSB_SPROM8_CCK2GPO		0x0140	/* CCK power offset */
++#define SSB_SPROM8_OFDM2GPO		0x0142	/* 2.4GHz OFDM power offset */
++#define SSB_SPROM8_OFDM5GPO		0x0146	/* 5.3GHz OFDM power offset */
++#define SSB_SPROM8_OFDM5GLPO		0x014A	/* 5.2GHz OFDM power offset */
++#define SSB_SPROM8_OFDM5GHPO		0x014E	/* 5.8GHz OFDM power offset */
+ 
+ /* Values for SSB_SPROM1_BINF_CCODE */
+ enum {