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authorGabor Juhos <juhosg@openwrt.org>2008-11-25 17:39:12 +0000
committerGabor Juhos <juhosg@openwrt.org>2008-11-25 17:39:12 +0000
commitea8f5369e9895ac6a7ff900fc4958cb9d6fb9975 (patch)
treec2af8741cc40e22f51c3dbdbdef32539c31fc9a6 /target
parent1004fcf830718fcff2f13dc6e95f9da692922b1c (diff)
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[ar71xx] improve SoC detection
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13349 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target')
-rw-r--r--target/linux/ar71xx/files/arch/mips/ar71xx/setup.c45
-rw-r--r--target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h12
2 files changed, 50 insertions, 7 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/setup.c b/target/linux/ar71xx/files/arch/mips/ar71xx/setup.c
index fc8652098d..758f541423 100644
--- a/target/linux/ar71xx/files/arch/mips/ar71xx/setup.c
+++ b/target/linux/ar71xx/files/arch/mips/ar71xx/setup.c
@@ -44,6 +44,9 @@ EXPORT_SYMBOL_GPL(ar71xx_ahb_freq);
u32 ar71xx_ddr_freq;
EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
+enum ar71xx_soc_type ar71xx_soc;
+EXPORT_SYMBOL_GPL(ar71xx_soc);
+
int (*ar71xx_pci_bios_init)(unsigned nr_irqs,
struct ar71xx_pci_irq *map) __initdata;
@@ -105,21 +108,35 @@ static void __init ar71xx_detect_sys_type(void)
id = ar71xx_reset_rr(RESET_REG_REV_ID) & REV_ID_MASK;
rev = (id >> REV_ID_REVISION_SHIFT) & REV_ID_REVISION_MASK;
+
switch (id & REV_ID_CHIP_MASK) {
case REV_ID_CHIP_AR7130:
+ ar71xx_soc = AR71XX_SOC_AR7130;
chip = "7130";
break;
+
case REV_ID_CHIP_AR7141:
+ ar71xx_soc = AR71XX_SOC_AR7141;
chip = "7141";
break;
+
case REV_ID_CHIP_AR7161:
+ ar71xx_soc = AR71XX_SOC_AR7161;
chip = "7161";
break;
+
case REV_ID_CHIP_AR9130:
+ ar71xx_soc = AR71XX_SOC_AR9130;
chip = "9130";
break;
+
+ case REV_ID_CHIP_AR9132:
+ ar71xx_soc = AR71XX_SOC_AR9132;
+ chip = "9132";
+ break;
+
default:
- chip = "71xx";
+ panic("ar71xx: unknown chip id:0x%02x\n", id);
}
sprintf(ar71xx_sys_type, "Atheros AR%s rev %u (id:0x%02x)",
@@ -152,11 +169,6 @@ static void __init ar71xx_detect_sys_frequency(void)
u32 freq;
u32 div;
- if ((ar71xx_reset_rr(RESET_REG_REV_ID) & REV_ID_MASK) >=
- REV_ID_CHIP_AR9130) {
- return ar91xx_detect_sys_frequency();
- }
-
pll = ar71xx_pll_rr(PLL_REG_CPU_PLL_CFG);
div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
@@ -172,6 +184,25 @@ static void __init ar71xx_detect_sys_frequency(void)
ar71xx_ahb_freq = ar71xx_cpu_freq / div;
}
+static void __init detect_sys_frequency(void)
+{
+ switch (ar71xx_soc) {
+ case AR71XX_SOC_AR7130:
+ case AR71XX_SOC_AR7141:
+ case AR71XX_SOC_AR7161:
+ ar71xx_detect_sys_frequency();
+ break;
+
+ case AR71XX_SOC_AR9130:
+ case AR71XX_SOC_AR9132:
+ ar91xx_detect_sys_frequency();
+ break;
+
+ default:
+ BUG();
+ }
+}
+
#ifdef CONFIG_AR71XX_EARLY_SERIAL
static void __init ar71xx_early_serial_setup(void)
{
@@ -222,7 +253,7 @@ void __init plat_mem_setup(void)
ar71xx_detect_mem_size();
ar71xx_detect_sys_type();
- ar71xx_detect_sys_frequency();
+ detect_sys_frequency();
_machine_restart = ar71xx_restart;
_machine_halt = ar71xx_halt;
diff --git a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
index 729ec9452b..8dbe021614 100644
--- a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
@@ -92,6 +92,17 @@ extern u32 ar71xx_ahb_freq;
extern u32 ar71xx_cpu_freq;
extern u32 ar71xx_ddr_freq;
+enum ar71xx_soc_type {
+ AR71XX_SOC_UNKNOWN,
+ AR71XX_SOC_AR7130,
+ AR71XX_SOC_AR7141,
+ AR71XX_SOC_AR7161,
+ AR71XX_SOC_AR9130,
+ AR71XX_SOC_AR9132
+};
+
+extern enum ar71xx_soc_type ar71xx_soc;
+
/*
* PLL block
*/
@@ -321,6 +332,7 @@ extern void ar71xx_ddr_flush(u32 reg);
#define REV_ID_CHIP_AR7141 0xa1
#define REV_ID_CHIP_AR7161 0xa2
#define REV_ID_CHIP_AR9130 0xb0
+#define REV_ID_CHIP_AR9132 0xb1
#define REV_ID_REVISION_MASK 0x3
#define REV_ID_REVISION_SHIFT 2