diff options
| author | David Bauer <mail@david-bauer.net> | 2018-05-08 20:59:05 +0200 |
|---|---|---|
| committer | John Crispin <john@phrozen.org> | 2018-06-18 23:23:30 +0200 |
| commit | abb4ab076f37961a4dcaef4e87167b834f84e44e (patch) | |
| tree | 1dfaebe048c34f3feebf685278532d09b9b053e9 /target/linux | |
| parent | d661a5d754d1fb4731a5524a20c8c24eaf59f627 (diff) | |
| download | upstream-abb4ab076f37961a4dcaef4e87167b834f84e44e.tar.gz upstream-abb4ab076f37961a4dcaef4e87167b834f84e44e.tar.bz2 upstream-abb4ab076f37961a4dcaef4e87167b834f84e44e.zip | |
ar71xx: fix incorrect speed setting on QCA9556
The QCA9556 only has a SGMII interface. However the speed on the
ethernet link is set for the non-existant xMII interface.
This commit fixes this behavior.
Signed-off-by: David Bauer <mail@david-bauer.net>
Diffstat (limited to 'target/linux')
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c index b46bab7886..1e230bce61 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c @@ -383,16 +383,26 @@ static void qca955x_set_speed_xmii(int speed) iounmap(base); } -static void qca955x_set_speed_sgmii(int speed) +static void qca955x_set_speed_sgmii(int id, int speed) { void __iomem *base; - u32 val = ath79_get_eth_pll(1, speed); + u32 val = ath79_get_eth_pll(id, speed); base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG); iounmap(base); } +static void qca9556_set_speed_sgmii(int speed) +{ + qca955x_set_speed_sgmii(0, speed); +} + +static void qca9558_set_speed_sgmii(int speed) +{ + qca955x_set_speed_sgmii(1, speed); +} + static void qca956x_set_speed_sgmii(int speed) { void __iomem *base; @@ -1028,10 +1038,14 @@ void __init ath79_register_eth(unsigned int id) pdata->reset_bit = QCA955X_RESET_GE0_MAC | QCA955X_RESET_GE0_MDIO; pdata->set_speed = qca955x_set_speed_xmii; + + /* QCA9556 only has SGMII interface */ + if (ath79_soc == ATH79_SOC_QCA9556) + pdata->set_speed = qca9556_set_speed_sgmii; } else { pdata->reset_bit = QCA955X_RESET_GE1_MAC | QCA955X_RESET_GE1_MDIO; - pdata->set_speed = qca955x_set_speed_sgmii; + pdata->set_speed = qca9558_set_speed_sgmii; } pdata->has_gbit = 1; |