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authorMartin Blumenstingl <martin.blumenstingl@googlemail.com>2022-10-10 17:48:49 +0200
committerMartin Blumenstingl <martin.blumenstingl@googlemail.com>2022-10-10 21:51:05 +0200
commit2683cca5927844594f7835aa983e2690d1e343c6 (patch)
tree3d48a1d0aff83294bb5d89cdbf2b1545e0738ae2 /target/linux
parentffd29a55c31697a69f4ebc59305cd95bda82aae3 (diff)
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lantiq: dts: vr9: Add missing properties to the CPU port on the switch
The CPU port should define the phy-mode and and a PHY phandle or fixed-link to indicate how the CPU port is connected to the SoC's Ethernet controller. On xRX200 this is all internal connection, so use phy-mode = "internal" along with a fixed-link that matches the definition inside &eth0. Linux 6.0 shows a warning since upstream commit e09e9873152e3f ("net: dsa: make phylink-related OF properties mandatory on DSA and CPU ports"). when these properties are missing. Adding the properties before OpenWrt is updated to Linux 6.0 is harmless. Suggested-by: Martin Schiller <ms@dev.tdt.de> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Diffstat (limited to 'target/linux')
-rw-r--r--target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi6
1 files changed, 6 insertions, 0 deletions
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi
index 1089cdc80c..7fa2fac1ef 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi
@@ -448,7 +448,13 @@
port@6 {
reg = <0x6>;
label = "cpu";
+ phy-mode = "internal";
ethernet = <&eth0>;
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
};
};