diff options
| author | Christian Lamparter <chunkeey@gmail.com> | 2018-07-14 17:21:56 +0200 |
|---|---|---|
| committer | John Crispin <john@phrozen.org> | 2018-07-16 15:10:21 +0200 |
| commit | c3f9a1ac0e7ae536552e2745582dc47098cefc07 (patch) | |
| tree | 5562427ba8280613b1cbaece62489b81ee0630b0 /target/linux | |
| parent | c729c43b391e759b6700b28c8e02ba93fe15f8c2 (diff) | |
| download | upstream-c3f9a1ac0e7ae536552e2745582dc47098cefc07.tar.gz upstream-c3f9a1ac0e7ae536552e2745582dc47098cefc07.tar.bz2 upstream-c3f9a1ac0e7ae536552e2745582dc47098cefc07.zip | |
apm821xx: attempt to fix sata access freezes
The original vendor's driver programmed the dma controller's
AHB HPROT values to enable bufferable, privileged mode. This
along with the "same priorty for both channels" could very
well fix the freezes that have been reported on the forum by
@ticerex and @takimata.
<https://forum.lede-project.org/t/wd-mybook-live-duo-two-disks/16195/46>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Diffstat (limited to 'target/linux')
| -rw-r--r-- | target/linux/apm821xx/patches-4.14/302-dw-dma-hprot-fix-and-equal-priortiy.patch | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/target/linux/apm821xx/patches-4.14/302-dw-dma-hprot-fix-and-equal-priortiy.patch b/target/linux/apm821xx/patches-4.14/302-dw-dma-hprot-fix-and-equal-priortiy.patch new file mode 100644 index 0000000000..c6e4331aa9 --- /dev/null +++ b/target/linux/apm821xx/patches-4.14/302-dw-dma-hprot-fix-and-equal-priortiy.patch @@ -0,0 +1,25 @@ +--- a/drivers/dma/dw/core.c ++++ b/drivers/dma/dw/core.c +@@ -167,6 +167,8 @@ static void dwc_initialize_chan_dw(struc + cfghi |= DWC_CFGH_DST_PER(dwc->dws.dst_id); + cfghi |= DWC_CFGH_SRC_PER(dwc->dws.src_id); + ++ cfghi |= DWC_CFGH_PROTCTL(3); /* bufferable + privileged access */ ++ + /* Set polarity of handshake interface */ + cfglo |= hs_polarity ? DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL : 0; + +@@ -1293,11 +1295,8 @@ int dw_dma_probe(struct dw_dma_chip *chi + else + list_add(&dwc->chan.device_node, &dw->dma.channels); + +- /* 7 is highest priority & 0 is lowest. */ +- if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) +- dwc->priority = pdata->nr_channels - i - 1; +- else +- dwc->priority = i; ++ /* set all channels to the same priority */ ++ dwc->priority = pdata->nr_channels - 1; + + dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; + spin_lock_init(&dwc->lock); |