diff options
| author | Daniel Golle <daniel@makrotopia.org> | 2018-05-31 17:28:38 +0200 |
|---|---|---|
| committer | Daniel Golle <daniel@makrotopia.org> | 2018-06-01 15:45:06 +0200 |
| commit | 17511a7ea86a34b5a5cfd4831d3a2e8a9e0cc005 (patch) | |
| tree | 430bec140ba8a22a60f5422f79e4304b3cbaf1b5 /target/linux | |
| parent | 91b5b2e20d531584918c62a6c6cd046f0580f50a (diff) | |
| download | upstream-17511a7ea86a34b5a5cfd4831d3a2e8a9e0cc005.tar.gz upstream-17511a7ea86a34b5a5cfd4831d3a2e8a9e0cc005.tar.bz2 upstream-17511a7ea86a34b5a5cfd4831d3a2e8a9e0cc005.zip | |
oxnas: kill old oxnas target
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Diffstat (limited to 'target/linux')
62 files changed, 0 insertions, 15085 deletions
diff --git a/target/linux/oxnas/Makefile b/target/linux/oxnas/Makefile deleted file mode 100644 index a1f453a0db..0000000000 --- a/target/linux/oxnas/Makefile +++ /dev/null @@ -1,30 +0,0 @@ -# -# Copyright (C) 2013 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk - -ARCH:=arm -BOARD:=oxnas -BOARDNAME:=PLXTECH/Oxford NAS782x/OX82x -DEVICE_TYPE:=nas -FEATURES:=gpio nand pcie usb ramdisk rtc squashfs ubifs source-only -CPU_TYPE:=mpcore - -MAINTAINER:=Daniel Golle <daniel@makrotopia.org> - -KERNEL_PATCHVER:=4.4 - -include $(INCLUDE_DIR)/target.mk - -DEFAULT_PACKAGES += \ - kmod-ata-core kmod-ata-oxnas-sata kmod-button-hotplug \ - kmod-input-gpio-keys-polled kmod-usb-ledtrig-usbport \ - kmod-ledtrig-timer kmod-leds-gpio kmod-usb2-oxnas \ - kmod-usb-storage uboot-envtools uboot-oxnas-ox820 - -KERNELNAME:=zImage dtbs - -$(eval $(call BuildTarget)) diff --git a/target/linux/oxnas/base-files/etc/board.d/01_leds b/target/linux/oxnas/base-files/etc/board.d/01_leds deleted file mode 100755 index 5d665093f6..0000000000 --- a/target/linux/oxnas/base-files/etc/board.d/01_leds +++ /dev/null @@ -1,27 +0,0 @@ -#!/bin/sh - -. /lib/functions/uci-defaults.sh - -board=$(board_name) -board_config_update - -case $board in - akitio) - ucidef_set_led_default "status" "status" "akitio:red:status" "0" - ;; - stg212) - ucidef_set_led_default "power" "power" "zyxel:blue:status" "1" - ucidef_set_led_usbdev "usb" "USB" "zyxel:orange:copy" "1-1" - ;; - kd20) - ucidef_set_led_default "power" "power" "kd20:blue:status" "1" - ;; - pogoplug-pro | pogoplug-v3) - ucidef_set_led_default "power" "power" "pogoplug:blue:internal" "1" - ;; - -esac - -board_config_flush - -exit 0 diff --git a/target/linux/oxnas/base-files/etc/board.d/02_network b/target/linux/oxnas/base-files/etc/board.d/02_network deleted file mode 100755 index 7ecaed51bf..0000000000 --- a/target/linux/oxnas/base-files/etc/board.d/02_network +++ /dev/null @@ -1,22 +0,0 @@ -#!/bin/sh - -. /lib/functions/uci-defaults.sh -. /lib/functions/system.sh -. /lib/oxnas.sh - -board_config_update - -lan_mac="" - -case "$(board_name)" in - kd20) - lan_mac="$(legacy_boot_mac_adr)" - ;; -esac - -ucidef_set_interface_lan "eth0" "dhcp" -[ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" "$lan_mac" - -board_config_flush - -exit 0 diff --git a/target/linux/oxnas/base-files/etc/diag.sh b/target/linux/oxnas/base-files/etc/diag.sh deleted file mode 100644 index fd3bc3b336..0000000000 --- a/target/linux/oxnas/base-files/etc/diag.sh +++ /dev/null @@ -1,41 +0,0 @@ -#!/bin/sh -# Copyright (C) 2009-2013 OpenWrt.org - -. /lib/functions.sh -. /lib/functions/leds.sh - -get_status_led() { - case $(board_name) in - akitio) - status_led="akitio:red:status" - ;; - stg212) - status_led="zyxel:blue:status" - ;; - kd20) - status_led="kd20:blue:status" - ;; - pogoplug-pro | pogoplug-v3) - status_led="pogoplug:blue:internal" - ;; - esac -} - -set_state() { - get_status_led - - case "$1" in - preinit) - status_led_blink_preinit - ;; - failsafe) - status_led_blink_failsafe - ;; - preinit_regular) - status_led_blink_preinit_regular - ;; - done) - status_led_on - ;; - esac -} diff --git a/target/linux/oxnas/base-files/init.d/set-irq-affinity b/target/linux/oxnas/base-files/init.d/set-irq-affinity deleted file mode 100755 index 8ab066ff4c..0000000000 --- a/target/linux/oxnas/base-files/init.d/set-irq-affinity +++ /dev/null @@ -1,22 +0,0 @@ -#!/bin/sh /etc/rc.common - -START=99 - -get_irq() { - local name="$1" - grep -m 1 "$name" /proc/interrupts | cut -d: -f1 | sed 's, *,,' -} - -set_irq_affinity() { - local name="$1" - local val="$2" - local irq="$(get_irq "$name")" - [ -n "$irq" ] || return - echo "$val" > "/proc/irq/$irq/smp_affinity" -} - -start() { - set_irq_affinity ehci_hcd 2 - set_irq_affinity xhci_hcd 2 - set_irq_affinity sata 2 -} diff --git a/target/linux/oxnas/base-files/lib/oxnas.sh b/target/linux/oxnas/base-files/lib/oxnas.sh deleted file mode 100755 index 671dd05fa2..0000000000 --- a/target/linux/oxnas/base-files/lib/oxnas.sh +++ /dev/null @@ -1,66 +0,0 @@ -#!/bin/sh -# -# Copyright (C) 2013 OpenWrt.org -# - -OXNAS_BOARD_NAME= -OXNAS_MODEL= - -bootloader_cmdline_var() { - local param - local pval - for arg in $(cat /proc/device-tree/chosen/bootloader-args); do - param="$(echo $arg | cut -d'=' -f 1)" - pval="$(echo $arg | cut -d'=' -f 2-)" - - if [ "$param" = "$1" ]; then - echo "$pval" - fi - done -} - -legacy_boot_mac_adr() { - local macstr - local oIFS - macstr="$(bootloader_cmdline_var mac_adr)" - oIFS="$IFS" - IFS="," - set -- $macstr - printf "%02x:%02x:%02x:%02x:%02x:%02x" $1 $2 $3 $4 $5 $6 - IFS="$oIFS" -} - -oxnas_board_detect() { - local machine - local name - - machine=$(cat /proc/device-tree/model) - - case "$machine" in - *"Akitio MyCloud mini"*) - name="akitio" - ;; - *"MitraStar Technology Corp. STG-212"*) - name="stg212" - ;; - *"Shuttle KD20"*) - name="kd20" - ;; - *"Pogoplug Pro"*) - name="pogoplug-pro" - ;; - *"Pogoplug V3"*) - name="pogoplug-v3" - ;; - esac - - [ -z "$name" ] && name="unknown" - - [ -z "$OXNAS_BOARD_NAME" ] && OXNAS_BOARD_NAME="$name" - [ -z "$OXNAS_MODEL" ] && OXNAS_MODEL="$machine" - - [ -e "/tmp/sysinfo/" ] || mkdir -p "/tmp/sysinfo/" - - echo "$OXNAS_BOARD_NAME" > /tmp/sysinfo/board_name - echo "$OXNAS_MODEL" > /tmp/sysinfo/model -} diff --git a/target/linux/oxnas/base-files/lib/preinit/01_preinit_do_oxnas.sh b/target/linux/oxnas/base-files/lib/preinit/01_preinit_do_oxnas.sh deleted file mode 100644 index ca7bce1054..0000000000 --- a/target/linux/oxnas/base-files/lib/preinit/01_preinit_do_oxnas.sh +++ /dev/null @@ -1,9 +0,0 @@ -#!/bin/sh - -do_oxnas() { - . /lib/oxnas.sh - - oxnas_board_detect -} - -boot_hook_add preinit_main do_oxnas diff --git a/target/linux/oxnas/base-files/lib/upgrade/platform.sh b/target/linux/oxnas/base-files/lib/upgrade/platform.sh deleted file mode 100644 index 059d75f9a9..0000000000 --- a/target/linux/oxnas/base-files/lib/upgrade/platform.sh +++ /dev/null @@ -1,18 +0,0 @@ -# -# Copyright (C) 2014 OpenWrt.org -# - -REQUIRE_IMAGE_METADATA=1 - -platform_check_image() { - local board=$(board_name) - - [ "$ARGC" -gt 1 ] && return 1 - - nand_do_platform_check $board $1 - return $? -} - -platform_do_upgrade() { - nand_do_upgrade $1 -} diff --git a/target/linux/oxnas/config-4.4 b/target/linux/oxnas/config-4.4 deleted file mode 100644 index 0c6e992510..0000000000 --- a/target/linux/oxnas/config-4.4 +++ /dev/null @@ -1,366 +0,0 @@ -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_APM_EMULATION is not set -CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -CONFIG_ARCH_HAS_RESET_CONTROLLER=y -CONFIG_ARCH_HAS_SG_CHAIN=y -CONFIG_ARCH_HAS_TICK_BROADCAST=y -CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OXNAS=y -CONFIG_ARCH_REQUIRE_GPIOLIB=y -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_USE_BUILTIN_BSWAP=y -CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y -CONFIG_ARCH_WANT_GENERAL_HUGETLB=y -CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y -CONFIG_ARCH_WANT_LIBATA_LEDS=y -CONFIG_ARM=y -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ATAG_DTB_COMPAT=y -# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set -# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y -CONFIG_ARM_CPUIDLE=y -# CONFIG_ARM_CPU_SUSPEND is not set -CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8 -CONFIG_ARM_DMA_USE_IOMMU=y -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_L1_CACHE_SHIFT=5 -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_SMMU=y -CONFIG_ARM_THUMB=y -CONFIG_ARM_UNWIND=y -CONFIG_ATAGS=y -CONFIG_ATA_LEDS=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BLK_DEV_BSG=y -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_BLK_DEV_SD=y -CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=1 -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=1 -# CONFIG_CACHE_L2X0 is not set -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLKSRC_OF=y -CONFIG_CLKSRC_PROBE=y -CONFIG_CLKSRC_RPS_TIMER=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="console=ttyS0,115200n8 earlyprintk=serial" -CONFIG_CMDLINE_FROM_BOOTLOADER=y -CONFIG_COMMON_CLK=y -CONFIG_COMPACTION=y -CONFIG_CONSOLE_POLL=y -CONFIG_COREDUMP=y -CONFIG_CPU_32v6=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_ABRT_EV6=y -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_CPU_CACHE_V6=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_HAS_ASID=y -# CONFIG_CPU_ICACHE_DISABLE is not set -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_PABRT_V6=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -# CONFIG_CPU_SW_DOMAIN_PAN is not set -CONFIG_CPU_TLB_V6=y -CONFIG_CPU_V6K=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_WORKQUEUE=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_ICEDCC=y -CONFIG_DEBUG_LL=y -CONFIG_DEBUG_LL_INCLUDE="debug/icedcc.S" -# CONFIG_DEBUG_UART_8250 is not set -# CONFIG_DEBUG_USER is not set -CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=16 -CONFIG_DEPRECATED_PARAM_STRUCT=y -CONFIG_DETECT_HUNG_TASK=y -CONFIG_DMADEVICES=y -CONFIG_DMA_CACHE_FIQ_BROADCAST=y -# CONFIG_DMA_CACHE_RWFO is not set -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DNOTIFY=y -CONFIG_DTC=y -CONFIG_DT_IDLE_STATES=y -CONFIG_DWMAC_GENERIC=y -CONFIG_DWMAC_OXNAS=y -# CONFIG_DWMAC_SUNXI is not set -# CONFIG_DW_DMAC_PCI is not set -CONFIG_EARLY_PRINTK=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_FIQ=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IO=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_DEVRES=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_GPIO_SYSFS=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set -CONFIG_HAVE_ARCH_AUDITSYSCALL=y -# CONFIG_HAVE_ARCH_BITREVERSE is not set -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_ARCH_PFN_VALID=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_ARM_SCU=y -CONFIG_HAVE_ARM_TWD=y -# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set -CONFIG_HAVE_BPF_JIT=y -CONFIG_HAVE_CC_STACKPROTECTOR=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_CLK_PREPARE=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_HAVE_DEBUG_KMEMLEAK=y -CONFIG_HAVE_DMA_API_DEBUG=y -CONFIG_HAVE_DMA_ATTRS=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_HAVE_IDE=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_MEMBLOCK=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_HAVE_NET_DSA=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_OPTPROBES=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_HAVE_PERF_REGS=y -CONFIG_HAVE_PERF_USER_STACK_DUMP=y -CONFIG_HAVE_PROC_CPU=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_SMP=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_UID16=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HZ_FIXED=0 -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y -CONFIG_ICPLUS_PHY=y -CONFIG_INPUT=y -# CONFIG_INPUT_MISC is not set -CONFIG_IOMMU_API=y -CONFIG_IOMMU_HELPER=y -CONFIG_IOMMU_IO_PGTABLE=y -CONFIG_IOMMU_IO_PGTABLE_LPAE=y -# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set -CONFIG_IOMMU_SUPPORT=y -# CONFIG_IP_ADVANCED_ROUTER is not set -# CONFIG_IP_MULTICAST is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_BOOTP is not set -CONFIG_IP_PNP_DHCP=y -# CONFIG_IP_PNP_RARP is not set -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_IRQ_WORK=y -# CONFIG_ISDN is not set -# CONFIG_JFFS2_FS is not set -CONFIG_JUMP_LABEL=y -CONFIG_KALLSYMS=y -CONFIG_KALLSYMS_ALL=y -CONFIG_KGDB=y -# CONFIG_KGDB_KDB is not set -CONFIG_KGDB_SERIAL_CONSOLE=y -# CONFIG_KGDB_TESTS is not set -# CONFIG_LDM_DEBUG is not set -CONFIG_LDM_PARTITION=y -# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set -# CONFIG_LEDS_TRIGGER_NETDEV is not set -# CONFIG_LEDS_TRIGGER_TIMER is not set -CONFIG_LIBFDT=y -CONFIG_LOCKUP_DETECTOR=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MACH_OX820=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAILBOX=y -# CONFIG_MAILBOX_TEST is not set -CONFIG_MDIO_BOARDINFO=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGHT_HAVE_PCI=y -CONFIG_MIGRATION=y -CONFIG_MODULES_USE_ELF_REL=y -# CONFIG_MODULE_STRIPPED is not set -# CONFIG_MTD_CFI is not set -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_OXNAS=y -# CONFIG_MTD_SPLIT_FIRMWARE is not set -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -# CONFIG_MTD_UBI_FASTMAP is not set -# CONFIG_MTD_UBI_GLUEBI is not set -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MULTI_IRQ_HANDLER=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_NLS=y -CONFIG_NO_BOOTMEM=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=2 -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_ADDRESS_PCI=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IOMMU=y -CONFIG_OF_IRQ=y -CONFIG_OF_MDIO=y -CONFIG_OF_MTD=y -CONFIG_OF_NET=y -CONFIG_OF_PCI=y -CONFIG_OF_PCI_IRQ=y -CONFIG_OF_RESERVED_MEM=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEASPM=y -# CONFIG_PCIEASPM_DEBUG is not set -CONFIG_PCIEASPM_DEFAULT=y -# CONFIG_PCIEASPM_PERFORMANCE is not set -# CONFIG_PCIEASPM_POWERSAVE is not set -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_PME=y -# CONFIG_PCI_DOMAINS_GENERIC is not set -CONFIG_PCI_OXNAS=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_OXNAS=y -CONFIG_PLXTECH_RPS=y -CONFIG_PM=y -CONFIG_PM_CLK=y -# CONFIG_PM_DEBUG is not set -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_GPIO=y -CONFIG_POWER_RESET_SYSCON_POWEROFF=y -CONFIG_POWER_SUPPLY=y -CONFIG_PPS=y -CONFIG_PRINTK_TIME=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_PWM=y -CONFIG_PWM_SYSFS=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_RCU_CPU_STALL_TIMEOUT=21 -CONFIG_RCU_STALL_COMMON=y -CONFIG_REALTEK_PHY=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RELAY=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RESET_CONTROLLER_OXNAS=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -# CONFIG_RTC_DRV_CMOS is not set -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -# CONFIG_SCHED_INFO is not set -CONFIG_SCSI=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_NR_UARTS=1 -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_RUNTIME_UARTS=1 -# CONFIG_SERIAL_KGDB_NMI is not set -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -CONFIG_SRCU=y -CONFIG_STMMAC_ETH=y -CONFIG_STMMAC_PLATFORM=y -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_SWIOTLB=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_TREE_RCU=y -CONFIG_UBIFS_FS=y -# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set -CONFIG_UBIFS_FS_LZO=y -CONFIG_UBIFS_FS_ZLIB=y -CONFIG_UNCOMPRESS_INCLUDE="mach/uncompress.h" -CONFIG_USB=y -CONFIG_USB_COMMON=y -# CONFIG_USB_EHCI_HCD is not set -CONFIG_USB_SUPPORT=y -# CONFIG_USB_UHCI_HCD is not set -CONFIG_USE_OF=y -CONFIG_VECTORS_BASE=0xffff0000 -# CONFIG_VFIO is not set -# CONFIG_VFP is not set -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_WATCHDOG_CORE=y -CONFIG_WATCHDOG_NOWAYOUT=y -CONFIG_XPS=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-akitio.dts b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-akitio.dts deleted file mode 100644 index 54aad1d86c..0000000000 --- a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-akitio.dts +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright (C) 2016 Daniel Golle <daniel@makrotopia.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; -#include "ox820.dtsi" - -#include <dt-bindings/input/input.h> - -/ { - model = "Akitio MyCloud mini"; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk=serial"; - }; - - pcie-controller@47C00000 { - status = "disabled"; - }; - - uart@44200000 { - status = "okay"; - }; - - sata@45900000 { - status = "okay"; - nr-ports = <2>; - }; - - nand@41000000 { - status = "okay"; - - }; - - ethernet@40400000 { - status = "okay"; - }; - - ehci@40200100 { - status = "okay"; - }; - - i2c-gpio { - compatible = "i2c-gpio"; - gpios = <&GPIOB 9 0 &GPIOB 10 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c>; - i2c-gpio,delay-us = <10>; - #address-cells = <1>; - #size-cells = <0>; - ds1307: rtc@68 { - compatible = "dallas,ds1307"; - reg = <0x68>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_buttons>; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - power { - label = "power"; - gpios = <&GPIOA 11 1>; - linux,code = <KEY_POWER>; - }; - reset { - label = "reset"; - gpios = <&GPIOB 6 1>; - linux,code = <KEY_RESTART>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - status { - label = "akitio:red:status"; - gpios = <&GPIOA 29 0>; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_poweroff>; - gpios = <&GPIOB 13 2>; - }; - - pinctrl { - i2c { - pinctrl_i2c: i2c-0 { - plxtech,pins = - <1 9 0 4 /* MF_B9 GPIO debounce */ - 1 10 0 4>; /* MF_B10 GPIO debounce */ - }; - }; - buttons { - pinctrl_buttons: buttons-0 { - plxtech,pins = - <0 11 0 0 /* MF_A11 GPIO */ - 1 6 0 0>; /* MF_B6 GPIO */ - }; - }; - leds { - pinctrl_leds: leds-0 { - plxtech,pins = - <0 29 0 0>; /* MF_A29 GPIO */ - }; - }; - poweroff { - pinctrl_poweroff: poweroff-0 { - plxtech,pins = - <1 13 0 0>; /* MF_B13 GPIO */ - }; - }; - }; -}; - -&nandc { - status = "okay"; - - nand@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - nand-ecc-mode = "soft"; - nand-ecc-algo = "hamming"; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x026c0000>; - }; - - partition@26c0000 { - label = "ubi"; - reg = <0x026c0000 0x0d940000>; - }; - }; -}; diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-kd20.dts b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-kd20.dts deleted file mode 100644 index a59addccac..0000000000 --- a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-kd20.dts +++ /dev/null @@ -1,173 +0,0 @@ -/* - * Copyright (C) 2014 Daniel Golle <daniel@makrotopia.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; -#include "ox820.dtsi" - -#include <dt-bindings/input/input.h> - -/ { - model = "Shuttle KD20"; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk=serial mem=256M"; - }; - - pcie-controller@47C00000 { - status = "okay"; - }; - - uart@44200000 { - status = "okay"; - }; - - sata@45900000 { - status = "okay"; - nr-ports = <2>; - }; - - ethernet@40400000 { - status = "okay"; - snps,phy-addr = <1>; - phy-mode = "rgmii-id"; - }; - - ehci@40200100 { - status = "okay"; - }; - - i2c-gpio { - compatible = "i2c-gpio"; - gpios = <&GPIOB 9 0 &GPIOB 10 0>; - i2c-gpio,delay-us = <10>; - #address-cells = <1>; - #size-cells = <0>; - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - power { - label = "power"; - gpios = <&GPIOA 10 1>; - linux,code = <KEY_POWER>; - }; - reset { - label = "reset"; - gpios = <&GPIOA 11 1>; - linux,code = <KEY_RESTART>; - }; - eject1 { - label = "eject1"; - gpios = <&GPIOA 5 1>; - linux,code = <KEY_EJECTCD>; - }; - eject2 { - label = "eject2"; - gpios = <&GPIOA 6 1>; - linux,code = <162>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - status { - label = "kd20:blue:status"; - gpios = <&GPIOB 16 0>; - }; - status2 { - label = "kd20:red:status"; - gpios = <&GPIOB 17 0>; - }; - hdd1blue { - label = "kd20:blue:hdd1"; - gpios = <&GPIOA 27 0>; - linux,default-trigger = "ata1"; - }; - hdd1red { - label = "kd20:red:hdd1"; - gpios = <&GPIOB 4 0>; - }; - hdd2blue { - label = "kd20:blue:hdd2"; - gpios = <&GPIOB 6 0>; - linux,default-trigger = "ata2"; - }; - hdd2red { - label = "kd20:red:hdd2"; - gpios = <&GPIOB 7 0>; - }; - usb { - label = "kd20:blue:usb"; - gpios = <&GPIOB 8 0>; - }; - }; - - beeper: beeper { - compatible = "gpio-beeper"; - gpios = <&GPIOB 11 0>; - }; - - gpio-fan { - compatible = "gpio-fan"; - gpios = <&GPIOA 2 1>; - gpio-fan,speed-map = <0 0 - 3000 1>; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&GPIOA 9 0>; - }; -}; - -&nandc { - status = "okay"; - - nand@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - nand-ecc-mode = "soft"; - nand-ecc-algo = "hamming"; - - partition@0 { - label = "stage1"; - reg = <0x00000000 0x00040000>; - read-only; - }; - - partition@40000 { - label = "u-boot"; - reg = <0x00040000 0x00200000>; - read-only; - }; - - partition@240000 { - label = "initrd"; - reg = <0x00240000 0x00600000>; - }; - - partition@840000 { - label = "kernel"; - reg = <0x00840000 0x007C0000>; - }; - - partition@e00000 { - label = "ubi"; - reg = <0x01000000 0x07000000>; - }; - }; -}; diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-pogoplug-pro.dts b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-pogoplug-pro.dts deleted file mode 100644 index 5b087e93fa..0000000000 --- a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-pogoplug-pro.dts +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; -#include "ox820.dtsi" - -/ { - model = "Pogoplug Pro"; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk=serial"; - }; - - pcie-controller@47C00000 { - status = "okay"; - }; - - uart@44200000 { - status = "okay"; - }; - - sata@45900000 { - status = "okay"; - }; - - ethernet@40400000 { - status = "okay"; - }; - - ehci@40200100 { - status = "okay"; - }; - - pinctrl { - leds { - pinctrl_leds: leds-0 { - plxtech,pins = - <0 2 0 0 /* MF_A2 */ - 1 16 0 0 /* MF_B16 */ - 1 17 0 0>; /* MF_B17 */ - }; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - blue { - label = "pogoplug:blue:internal"; - gpios = <&GPIOA 2 0>; - - }; - - orange { - label = "pogoplug:orange:usr"; - gpios = <&GPIOB 16 1>; - }; - - green { - label = "pogoplug:green:usr"; - gpios = <&GPIOB 17 1>; - }; - }; -}; - -&nandc { - status = "okay"; - - nand@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - nand-ecc-mode = "soft"; - nand-ecc-algo = "hamming"; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x00e00000>; - /*read-only;*/ - }; - - partition@e00000 { - label = "ubi"; - reg = <0x00e00000 0x07200000>; - }; - }; -}; diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-pogoplug-v3.dts b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-pogoplug-v3.dts deleted file mode 100644 index be0f6c9077..0000000000 --- a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-pogoplug-v3.dts +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (C) 2014 Daniel Golle <daniel@makrotopia.org> - * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; -#include "ox820.dtsi" - -/ { - model = "Pogoplug V3"; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk=serial"; - }; - - uart@44200000 { - status = "okay"; - }; - - sata@45900000 { - status = "okay"; - }; - - ethernet@40400000 { - status = "okay"; - }; - - ehci@40200100 { - status = "okay"; - }; - - pinctrl { - leds { - pinctrl_leds: leds-0 { - plxtech,pins = - <0 2 0 0 /* MF_A2 */ - 1 16 0 0 /* MF_B16 */ - 1 17 0 0>; /* MF_B17 */ - }; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - blue { - label = "pogoplug:blue:internal"; - gpios = <&GPIOA 2 0>; - }; - - orange { - label = "pogoplug:orange:usr"; - gpios = <&GPIOB 16 1>; - }; - - green { - label = "pogoplug:green:usr"; - gpios = <&GPIOB 17 1>; - }; - }; - -}; - -&nandc { - status = "okay"; - - nand@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - nand-ecc-mode = "soft"; - nand-ecc-algo = "hamming"; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x00e00000>; - /*read-only;*/ - }; - - partition@e00000 { - label = "ubi"; - reg = <0x00e00000 0x07200000>; - }; - }; -}; diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-stg212.dts b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-stg212.dts deleted file mode 100644 index ad93d4ec15..0000000000 --- a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-stg212.dts +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (C) 2013 OpenWrt.org - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; - -#include "ox820.dtsi" - -#include <dt-bindings/input/input.h> - -/ { - model = "MitraStar Technology Corp. STG-212"; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk=serial mem=128M"; - }; - - uart@44200000 { - status = "okay"; - }; - - sata@45900000 { - status = "okay"; - }; - - - ethernet@40400000 { - status = "okay"; - }; - - ehci@40200100 { - status = "okay"; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - reset { - label = "reset"; - gpios = <&GPIOB 11 1>; - linux,code = <KEY_RESTART>; - }; - copy { - label = "copy"; - gpios = <&GPIOB 13 1>; - linux,code = <KEY_COPY>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - status { - label = "zyxel:blue:status"; - gpios = <&GPIOB 5 0>; - }; - status2 { - label = "zyxel:red:status"; - gpios = <&GPIOB 6 1>; - }; - copy { - label = "zyxel:orange:copy"; - gpios = <&GPIOB 8 1>; - }; - }; - - i2c-gpio { - compatible = "i2c-gpio"; - gpios = <&GPIOB 9 0 &GPIOB 10 0>; - i2c-gpio,delay-us = <10>; - }; - -}; - -&nandc { - status = "okay"; - - nand@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - nand-ecc-mode = "soft"; - nand-ecc-algo = "hamming"; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x00e00000>; - read-only; - }; - - partition@e00000 { - label = "ubi"; - reg = <0x00e00000 0x07200000>; - }; - }; -}; diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820.dtsi b/target/linux/oxnas/files/arch/arm/boot/dts/ox820.dtsi deleted file mode 100644 index c096a7d1c3..0000000000 --- a/target/linux/oxnas/files/arch/arm/boot/dts/ox820.dtsi +++ /dev/null @@ -1,342 +0,0 @@ -/* - * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "skeleton.dtsi" - -/ { - compatible = "plxtech,nas7820", "plxtech,nas782x"; - interrupt-parent = <&gic>; - - aliases { - serial0 = &uart0; - /* alias to determine bank index */ - gpio0 = &GPIOA; - gpio1 = &GPIOB; - - ethernet0 = &gmac; - }; - - cpus { - cpu@0 { - compatible = "arm,arm11mpcore"; - }; - cpu@1 { - compatible = "arm,arm11mpcore"; - }; - }; - - gic: gic@47001000 { - compatible = "arm,arm11mp-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x47001000 0x1000>, - <0x47000100 0x0100>; - }; - - rst: reset-controller@44E00034 { - compatible = "plxtech,nas782x-reset"; - #reset-cells = <1>; - reg = <0x44E00034 0x8>; /* currently not used */ - }; - - rps: rps@44400000 { - compatible = "plxtech,nas782x-rps"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x44400000 0x14>; - interrupts = <0 5 0x304>; - }; - - /* external oscillator */ - osc: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - sysclk: sysclk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - clocks = <&osc>; - }; - - plla: plla@44e001f0 { - compatible = "plxtech,nas782x-plla"; - #clock-cells = <0>; - clocks = <&osc>; - reg = <0x44e001f0 0x10>; - }; - - pllb: pllb@44f001f0 { - compatible = "plxtech,nas782x-pllb"; - #clock-cells = <0>; - clocks = <&osc>; - reg = <0x44f001f0 0x10>; - resets = <&rst 31>; - }; - - stdclk: stdclk { - compatible = "plxtech,nas782x-stdclk"; - #clock-cells = <1>; - clocks = <&osc>; - }; - - twdclk: twdclk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - clocks = <&plla>; - }; - - gmacclk: gmacclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - - pinctrl { - /* act as a simple bus, so children will be probed automatically */ - #address-cells = <1>; - #size-cells = <1>; - compatible = "plxtech,nas782x-pinctrl", "simple-bus"; - ranges; - - plxtech,mux-mask = < - 0xFFFFFFFF 0xCC0FFDF9 0xFC000E60 0x0F03F7E0 0xF00C0FE0 - 0x0003FFFF 0x00037FFF 0x0003FFF8 0x00000F00 0x0003F7F3 - >; - - GPIOA: gpio@44000000 { - compatible = "plxtech,nas782x-gpio"; - reg = <0x44000000 0x100>, <0x44E00000 0x200>; - interrupts = <0 21 0x304>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - #gpio-lines = <32>; /* real gpio pin count */ - }; - - GPIOB: gpio@44100000 { - compatible = "plxtech,nas782x-gpio"; - reg = <0x44100000 0x100>, <0x44F00000 0x200>; - interrupts = <0 22 0x304>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - #gpio-lines = <18>; /* real gpio pin count */ - }; - - uart0 { - pinctrl_uart0: uart0-0 { - plxtech,pins = - <0 30 5 0 /* MF_A30 PINMUX_ALT PINMUX_UARTA_SIN */ - 0 31 5 0>; /* MF_A31 PINMUX_ALT PINMUX_UARTA_SOUT */ - }; - }; - - gmac0 { - pinctrl_gmac0: gmac0-0 { - plxtech,pins = - <0 3 1 0 /* MF_A3 PINMUX_2 PINMUX_MACA_MDC */ - 0 4 1 0>; /* MF_A4 PINMUX_2 PINMUX_MACA_MDIO */ - }; - }; - - nand0 { - pinctrl_nand0: nand0-0 { - plxtech,pins = - <0 12 1 0 /* MF_A12 PINMUX_2 PINMUX_STATIC_DATA0 */ - 0 13 1 0 /* MF_A13 PINMUX_2 PINMUX_STATIC_DATA1 */ - 0 14 1 0 /* MF_A14 PINMUX_2 PINMUX_STATIC_DATA2 */ - 0 15 1 0 /* MF_A15 PINMUX_2 PINMUX_STATIC_DATA3 */ - 0 16 1 0 /* MF_A16 PINMUX_2 PINMUX_STATIC_DATA4 */ - 0 17 1 0 /* MF_A17 PINMUX_2 PINMUX_STATIC_DATA5 */ - 0 18 1 0 /* MF_A18 PINMUX_2 PINMUX_STATIC_DATA6 */ - 0 19 1 0 /* MF_A19 PINMUX_2 PINMUX_STATIC_DATA7 */ - - 0 20 1 0 /* MF_A20 PINMUX_2 PINMUX_STATIC_NWE */ - 0 21 1 0 /* MF_A21 PINMUX_2 PINMUX_STATIC_NOE */ - 0 22 1 0 /* MF_A22 PINMUX_2 PINMUX_STATIC_NCS */ - 0 23 1 0 /* MF_A23 PINMUX_2 PINMUX_STATIC_ADDR18 */ - 0 24 1 0>; /* MF_A24 PINMUX_2 PINMUX_STATIC_ADDR19 */ - }; - }; - }; - - pcie-controller@47C00000 { - compatible = "plxtech,nas782x-pcie"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - - /* flag & space bus address host address size */ - ranges = < 0x82000000 0 0x48000000 0x48000000 0 0x2000000 - 0xC2000000 0 0x4A000000 0x4A000000 0 0x1E00000 - 0x81000000 0 0x4BE00000 0x4BE00000 0 0x0100000 - 0x80000000 0 0x4BF00000 0x4BF00000 0 0x0100000>; - - bus-range = <0x00 0x7f>; - - /* cfg inbound translator phy*/ - reg = <0x47C00000 0x1000>, <0x47D00000 0x100>, <0x44A00000 0x10>; - - #interrupt-cells = <1>; - /* wild card mask, match all bus address & interrupt specifier */ - /* format: bus address mask, interrupt specifier mask */ - /* each bit 1 means need match, 0 means ignored when match */ - interrupt-map-mask = <0 0 0 0>; - /* format: a list of: bus address, interrupt specifier, - * parent interrupt controller & specifier */ - interrupt-map = <0 0 0 0 &gic 0 19 0x304>; - - gpios = <&GPIOB 12 0>; - clocks = <&stdclk 8>, <&pllb>; - clock-names = "pcie", "busclk"; - resets = <&rst 7>, <&rst 14>; - reset-names = "pcie", "phy"; - - plxtech,pcie-hcsl-bit = <2>; - plxtech,pcie-ctrl-offset = <0x120>; - plxtech,pcie-outbound-offset = <0x138>; - status = "disabled"; - }; - - pcie-controller@47E00000 { - compatible = "plxtech,nas782x-pcie"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - - /* flag & space bus address host address size */ - ranges = < 0x82000000 0 0x4C000000 0x4C000000 0 0x2000000 - 0xC2000000 0 0x4E000000 0x4E000000 0 0x1E00000 - 0x81000000 0 0x4FE00000 0x4FE00000 0 0x0100000 - 0x80000000 0 0x4FF00000 0x4FF00000 0 0x0100000>; - - bus-range = <0x80 0xff>; - - /* cfg inbound translator phy*/ - reg = <0x47E00000 0x1000>, <0x47F00000 0x100>, <0x44A00000 0x10>; - - #interrupt-cells = <1>; - /* wild card mask, match all bus address & interrupt specifier */ - /* format: bus address mask, interrupt specifier mask */ - /* each bit 1 means need match, 0 means ignored when match */ - interrupt-map-mask = <0 0 0 0>; - /* format: a list of: bus address, interrupt specifier, - * parent interrupt controller & specifier */ - interrupt-map = <0 0 0 0 &gic 0 20 0x304>; - - /* gpios = <&GPIOB 12 0>; */ - clocks = <&stdclk 11>, <&pllb>; - clock-names = "pcie", "busclk"; - resets = <&rst 23>, <&rst 14>; - reset-names = "pcie", "phy"; - - plxtech,pcie-hcsl-bit = <3>; - plxtech,pcie-ctrl-offset = <0x124>; - plxtech,pcie-outbound-offset = <0x174>; - status = "disabled"; - }; - - local-timer@47000600 { - compatible = "arm,arm11mp-twd-timer"; - reg = <0x47000600 0x20>; - interrupts = <1 13 0x304>; /* percpu, irq 29, cpu mask 3, level high */ - clocks = <&twdclk>; - }; - - watchdog@47000620 { - compatible = "mpcore_wdt"; - reg = <0x47000620 0x20>; - interrupts = <1 14 0x304>; /* percpu, irq 30, cpu mask 3, level high */ - clocks = <&twdclk>; - }; - - timer@44400200 { - compatible = "plxtech,nas782x-rps-timer"; - reg = <0x44400200 0x40>; - clocks = <&sysclk>; - }; - - uart0: uart@44200000 { - compatible = "ns16550a"; - reg = <0x44200000 0x100>; - clock-frequency = <6250000>; - interrupts = <0 23 0x304>; - reg-shift = <0>; - fifo-size = <16>; - reg-io-width = <1>; - current-speed = <115200>; - no-loopback-test; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - status = "disabled"; - }; - - sata@45900000 { - compatible = "plxtech,nas782x-sata"; - /* ports dmactl sgdma */ - reg = <0x45900000 0x20000>, <0x459A0000 0x40>, <0x459B0000 0x20>, - /* core phy descriptors (optional) */ - <0x459E0000 0x2000>, <0x44900000 0x0C>, <0x50000000 0x1000>; - interrupts = <0 18 0x304>; - clocks = <&stdclk 4>; - resets = <&rst 11>, <&rst 12>, <&rst 13>; - reset-names = "sata", "link", "phy"; - nr-ports = <1>; - status = "disabled"; - }; - - nandc: nand-controller@41000000 { - compatible = "oxsemi,ox820-nand"; - reg = <0x41000000 0x100000>; - clocks = <&stdclk 9>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand0>; - resets = <&rst 15>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gmac: ethernet@40400000 { - compatible = "plxtech,nas782x-gmac", "snps,dwmac"; - reg = <0x40400000 0x2000>; - interrupts = <0 8 0x304>, <0 17 0x304>; - interrupt-names = "macirq", "eth_wake_irq"; - mac-address = [000000000000]; /* Filled in by U-Boot */ - phy-mode = "rgmii"; - clocks = <&stdclk 7>, <&gmacclk>; - clock-names = "gmac", "stmmaceth"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gmac0>; - resets = <&rst 6>; - status = "disabled"; - }; - - ehci@40200100 { - compatible = "plxtech,nas782x-ehci"; - reg = <0x40200100 0xf00>; - interrupts = <0 7 0x304>; - clocks = <&stdclk 6>, <&pllb>, <&stdclk 12>; - clock-names = "usb", "refsrc", "phyref"; - resets = <&rst 4>, <&rst 5>, <&rst 26>; - reset-names = "host", "phya", "phyb"; - /* Otherwise ref300 is used, which is derived from sata phy - * in that case, usb depends on sata initialization */ - /* FIXME: how to make this dependency explicit ? */ - plxtech,ehci_use_pllb; - status = "disabled"; - }; -}; diff --git a/target/linux/oxnas/files/arch/arm/configs/ox820_defconfig b/target/linux/oxnas/files/arch/arm/configs/ox820_defconfig deleted file mode 100644 index bb0a9d68a8..0000000000 --- a/target/linux/oxnas/files/arch/arm/configs/ox820_defconfig +++ /dev/null @@ -1,104 +0,0 @@ -CONFIG_CROSS_COMPILE="arm-linux-gnueabi-" -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_NO_HZ_IDLE=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_CGROUPS=y -CONFIG_NAMESPACES=y -CONFIG_EMBEDDED=y -# CONFIG_COMPAT_BRK is not set -CONFIG_JUMP_LABEL=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_ARCH_OXNAS=y -# CONFIG_DMA_CACHE_RWFO is not set -CONFIG_DMA_CACHE_FIQ_BROADCAST=y -CONFIG_PCI=y -CONFIG_PCI_OXNAS=y -CONFIG_SMP=y -# CONFIG_SMP_ON_UP is not set -CONFIG_NR_CPUS=2 -CONFIG_HOTPLUG_CPU=y -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_UACCESS_WITH_MEMCPY=y -CONFIG_USE_OF=y -CONFIG_BINFMT_MISC=y -# CONFIG_SUSPEND is not set -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IPV6=y -CONFIG_CFG80211=y -CONFIG_MAC80211=y -CONFIG_MAC80211_RC_PID=y -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_OXNAS=y -CONFIG_MTD_UBI=y -CONFIG_BLK_DEV_SD=y -CONFIG_SCSI_MULTI_LUN=y -CONFIG_ATA=y -CONFIG_SATA_OXNAS=y -CONFIG_NETDEVICES=y -CONFIG_STMMAC_ETH=y -CONFIG_STMMAC_DEBUG_FS=y -CONFIG_STMMAC_DA=y -CONFIG_ATH_CARDS=y -CONFIG_ATH9K=y -CONFIG_ATH9K_LEGACY_RATE_CONTROL=y -# CONFIG_RTL_CARDS is not set -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -# CONFIG_LEGACY_PTYS is not set -CONFIG_SERIAL_8250=y -# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=1 -CONFIG_SERIAL_8250_RUNTIME_UARTS=1 -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_GPIO_SYSFS=y -CONFIG_USB=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_OXNAS=y -CONFIG_USB_STORAGE=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_ONESHOT=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -CONFIG_COMMON_CLK_DEBUG=y -CONFIG_EXT2_FS=y -CONFIG_EXT4_FS=y -CONFIG_FUSE_FS=y -CONFIG_VFAT_FS=y -CONFIG_NTFS_FS=m -CONFIG_NTFS_RW=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_UBIFS_FS=y -CONFIG_NFS_FS=y -CONFIG_ROOT_NFS=y -CONFIG_PRINTK_TIME=y -# CONFIG_ENABLE_WARN_DEPRECATED is not set -# CONFIG_ENABLE_MUST_CHECK is not set -# CONFIG_FTRACE is not set -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y -CONFIG_DEBUG_LL_UART_8250=y -CONFIG_DEBUG_UART_PHYS=0x44200000 -CONFIG_DEBUG_UART_VIRT=0xF0000000 -CONFIG_DEBUG_UART_8250_SHIFT=0 -CONFIG_EARLY_PRINTK=y -CONFIG_CRYPTO_ANSI_CPRNG=y diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/Kconfig b/target/linux/oxnas/files/arch/arm/mach-oxnas/Kconfig deleted file mode 100644 index 6bdf3f6efd..0000000000 --- a/target/linux/oxnas/files/arch/arm/mach-oxnas/Kconfig +++ /dev/null @@ -1,25 +0,0 @@ -choice - prompt "Oxnas platform type" - default MACH_OXNAS - depends on ARCH_OXNAS - -config MACH_OX820 - bool "Generic NAS7820 Support" - select ARM_GIC - select GENERIC_CLOCKEVENTS - select CPU_V6K - select HAVE_ARM_SCU if SMP - select HAVE_ARM_TWD if SMP - select HAVE_SMP - select PLXTECH_RPS - select CLKSRC_OF - select CLKSRC_RPS_TIMER - select USB_ARCH_HAS_EHCI - select PINCTRL_OXNAS - select PINCTRL - select RESET_CONTROLLER_OXNAS - select ARCH_WANT_LIBATA_LEDS - help - Include support for the ox820 platform. - -endchoice diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/Makefile b/target/linux/oxnas/files/arch/arm/mach-oxnas/Makefile deleted file mode 100644 index 6862c34981..0000000000 --- a/target/linux/oxnas/files/arch/arm/mach-oxnas/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Makefile for the linux kernel. -# - -obj-$(CONFIG_MACH_OX820) += mach-ox820.o -obj-$(CONFIG_SMP) += platsmp.o headsmp.o -obj-$(CONFIG_DMA_CACHE_FIQ_BROADCAST) += fiq.o -obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/Makefile.boot b/target/linux/oxnas/files/arch/arm/mach-oxnas/Makefile.boot deleted file mode 100644 index b52e473d64..0000000000 --- a/target/linux/oxnas/files/arch/arm/mach-oxnas/Makefile.boot +++ /dev/null @@ -1,2 +0,0 @@ - zreladdr-y += 0x60008000 -params_phys-y := 0x60000100 diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/fiq.S b/target/linux/oxnas/files/arch/arm/mach-oxnas/fiq.S deleted file mode 100644 index 6acd5a7394..0000000000 --- a/target/linux/oxnas/files/arch/arm/mach-oxnas/fiq.S +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (C) 2012 Gateworks Corporation - * Chris Lang <clang@gateworks.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/linkage.h> -#include <asm/assembler.h> -#include <asm/asm-offsets.h> - -#define D_CACHE_LINE_SIZE 32 - - .text - -/* - * R8 - DMA Start Address - * R9 - DMA Length - * R10 - DMA Direction - * R11 - DMA type - * R12 - fiq_buffer Address -*/ - - .global ox820_fiq_end -ENTRY(ox820_fiq_start) - str r8, [r13] - - ldmia r12, {r8, r9, r10} - and r11, r10, #0x3000000 - and r10, r10, #0xff - - teq r11, #0x1000000 - beq ox820_dma_map_area - teq r11, #0x2000000 - beq ox820_dma_unmap_area - /* fall through */ -ox820_dma_flush_range: - bic r8, r8, #D_CACHE_LINE_SIZE - 1 -1: - mcr p15, 0, r8, c7, c14, 1 @ clean & invalidate D line - add r8, r8, #D_CACHE_LINE_SIZE - cmp r8, r9 - blo 1b - /* fall through */ -ox820_fiq_exit: - mov r8, #0 - str r8, [r12, #8] - mcr p15, 0, r8, c7, c10, 4 @ drain write buffer - subs pc, lr, #4 - -ox820_dma_map_area: - add r9, r9, r8 - teq r10, #DMA_FROM_DEVICE - beq ox820_dma_inv_range - teq r10, #DMA_TO_DEVICE - bne ox820_dma_flush_range - /* fall through */ -ox820_dma_clean_range: - bic r8, r8, #D_CACHE_LINE_SIZE - 1 -1: - mcr p15, 0, r8, c7, c10, 1 @ clean D line - add r8, r8, #D_CACHE_LINE_SIZE - cmp r8, r9 - blo 1b - b ox820_fiq_exit - -ox820_dma_unmap_area: - add r9, r9, r8 - teq r10, #DMA_TO_DEVICE - beq ox820_fiq_exit - /* fall through */ -ox820_dma_inv_range: - tst r8, #D_CACHE_LINE_SIZE - 1 - bic r8, r8, #D_CACHE_LINE_SIZE - 1 - mcrne p15, 0, r8, c7, c10, 1 @ clean D line - tst r9, #D_CACHE_LINE_SIZE - 1 - bic r9, r9, #D_CACHE_LINE_SIZE - 1 - mcrne p15, 0, r9, c7, c14, 1 @ clean & invalidate D line -1: - mcr p15, 0, r8, c7, c6, 1 @ invalidate D line - add r8, r8, #D_CACHE_LINE_SIZE - cmp r8, r9 - blo 1b - b ox820_fiq_exit - -ox820_fiq_end: diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/headsmp.S b/target/linux/oxnas/files/arch/arm/mach-oxnas/headsmp.S deleted file mode 100644 index a63edae62b..0000000000 --- a/target/linux/oxnas/files/arch/arm/mach-oxnas/headsmp.S +++ /dev/null @@ -1,27 +0,0 @@ -/* - * linux/arch/arm/mach-ox820/headsmp.S - * - * Copyright (c) 2003 ARM Limited - * All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/linkage.h> -#include <linux/init.h> - - __INIT - -/* - * OX820 specific entry point for secondary CPUs. - */ -ENTRY(ox820_secondary_startup) - mov r4, #0 - /* invalidate both caches and branch target cache */ - mcr p15, 0, r4, c7, c7, 0 - /* - * we've been released from the holding pen: secondary_stack - * should now contain the SVC stack for this core - */ - b secondary_startup diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/hotplug.c b/target/linux/oxnas/files/arch/arm/mach-oxnas/hotplug.c deleted file mode 100644 index e3c9cb5db7..0000000000 --- a/target/linux/oxnas/files/arch/arm/mach-oxnas/hotplug.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * linux/arch/arm/mach-realview/hotplug.c - * - * Copyright (C) 2002 ARM Ltd. - * All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/kernel.h> -#include <linux/errno.h> -#include <linux/smp.h> - -#include <asm/cp15.h> -#include <asm/smp_plat.h> - -static inline void cpu_enter_lowpower(void) -{ - unsigned int v; - - asm volatile( - " mcr p15, 0, %1, c7, c5, 0\n" - " mcr p15, 0, %1, c7, c10, 4\n" - /* - * Turn off coherency - */ - " mrc p15, 0, %0, c1, c0, 1\n" - " bic %0, %0, #0x20\n" - " mcr p15, 0, %0, c1, c0, 1\n" - " mrc p15, 0, %0, c1, c0, 0\n" - " bic %0, %0, %2\n" - " mcr p15, 0, %0, c1, c0, 0\n" - : "=&r" (v) - : "r" (0), "Ir" (CR_C) - : "cc"); -} - -static inline void cpu_leave_lowpower(void) -{ - unsigned int v; - - asm volatile( "mrc p15, 0, %0, c1, c0, 0\n" - " orr %0, %0, %1\n" - " mcr p15, 0, %0, c1, c0, 0\n" - " mrc p15, 0, %0, c1, c0, 1\n" - " orr %0, %0, #0x20\n" - " mcr p15, 0, %0, c1, c0, 1\n" - : "=&r" (v) - : "Ir" (CR_C) - : "cc"); -} - -static inline void platform_do_lowpower(unsigned int cpu, int *spurious) -{ - /* - * there is no power-control hardware on this platform, so all - * we can do is put the core into WFI; this is safe as the calling - * code will have already disabled interrupts - */ - for (;;) { - /* - * here's the WFI - */ - asm(".word 0xe320f003\n" - : - : - : "memory", "cc"); - - if (pen_release == cpu_logical_map(cpu)) { - /* - * OK, proper wakeup, we're done - */ - break; - } - - /* - * Getting here, means that we have come out of WFI without - * having been woken up - this shouldn't happen - * - * Just note it happening - when we're woken, we can report - * its occurrence. - */ - (*spurious)++; - } -} - -/* - * platform-specific code to shutdown a CPU - * - * Called with IRQs disabled - */ -void ox820_cpu_die(unsigned int cpu) -{ - int spurious = 0; - - /* - * we're ready for shutdown now, so do it - */ - cpu_enter_lowpower(); - platform_do_lowpower(cpu, &spurious); - - /* - * bring this CPU back into the world of cache - * coherency, and then restore interrupts - */ - cpu_leave_lowpower(); - - if (spurious) - pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious); -} diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/hardware.h b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/hardware.h deleted file mode 100644 index caae772c31..0000000000 --- a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/hardware.h +++ /dev/null @@ -1,233 +0,0 @@ -/* - * arch/arm/mach-0x820/include/mach/hardware.h - * - * Copyright (C) 2009 Oxford Semiconductor Ltd - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include <linux/io.h> -#include <mach/iomap.h> - -/* - * Location of flags and vectors in SRAM for controlling the booting of the - * secondary ARM11 processors. - */ - -#define OXNAS_SCU_BASE_VA OXNAS_PERCPU_BASE_VA -#define OXNAS_GICN_BASE_VA(n) (OXNAS_PERCPU_BASE_VA + 0x200 + n*0x100) - -#define HOLDINGPEN_CPU IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc8) -#define HOLDINGPEN_LOCATION IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc4) - -/** - * System block reset and clock control - */ -#define SYS_CTRL_PCI_STAT IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x20) -#define SYSCTRL_CLK_STAT IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x24) -#define SYS_CTRL_CLK_SET_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x2C) -#define SYS_CTRL_CLK_CLR_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x30) -#define SYS_CTRL_RST_SET_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x34) -#define SYS_CTRL_RST_CLR_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x38) - -#define SYS_CTRL_PLLSYS_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x48) -#define SYS_CTRL_CLK_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x64) -#define SYS_CTRL_PLLSYS_KEY_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x6C) -#define SYS_CTRL_GMAC_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x78) -#define SYS_CTRL_GMAC_DELAY_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x100) - -/* Scratch registers */ -#define SYS_CTRL_SCRATCHWORD0 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc4) -#define SYS_CTRL_SCRATCHWORD1 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc8) -#define SYS_CTRL_SCRATCHWORD2 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xcc) -#define SYS_CTRL_SCRATCHWORD3 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xd0) - -#define SYS_CTRL_PLLA_CTRL0 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F0) -#define SYS_CTRL_PLLA_CTRL1 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F4) -#define SYS_CTRL_PLLA_CTRL2 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F8) -#define SYS_CTRL_PLLA_CTRL3 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1FC) - -#define SYS_CTRL_USBHSMPH_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x40) -#define SYS_CTRL_USBHSMPH_STAT IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x44) -#define SYS_CTRL_REF300_DIV IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xF8) -#define SYS_CTRL_USBHSPHY_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x84) -#define SYS_CTRL_USB_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x90) - -/* pcie */ -#define SYS_CTRL_HCSL_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x114) - -/* System control multi-function pin function selection */ -#define SYS_CTRL_SECONDARY_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x14) -#define SYS_CTRL_TERTIARY_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x8c) -#define SYS_CTRL_QUATERNARY_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x94) -#define SYS_CTRL_DEBUG_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x9c) -#define SYS_CTRL_ALTERNATIVE_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xa4) -#define SYS_CTRL_PULLUP_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xac) - -/* Secure control multi-function pin function selection */ -#define SEC_CTRL_SECONDARY_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x14) -#define SEC_CTRL_TERTIARY_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x8c) -#define SEC_CTRL_QUATERNARY_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x94) -#define SEC_CTRL_DEBUG_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x9c) -#define SEC_CTRL_ALTERNATIVE_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0xa4) -#define SEC_CTRL_PULLUP_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0xac) - -#define SEC_CTRL_COPRO_CTRL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x68) -#define SEC_CTRL_SECURE_CTRL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x98) -#define SEC_CTRL_LEON_DEBUG IOMEM(OXNAS_SECCRTL_BASE_VA + 0xF0) -#define SEC_CTRL_PLLB_DIV_CTRL IOMEM(OXNAS_SECCRTL_BASE_VA + 0xF8) -#define SEC_CTRL_PLLB_CTRL0 IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F0) -#define SEC_CTRL_PLLB_CTRL1 IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F4) -#define SEC_CTRL_PLLB_CTRL8 IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F4) - -#define RPSA_IRQ_SOFT IOMEM(OXNAS_RPSA_BASE_VA + 0x10) -#define RPSA_FIQ_ENABLE IOMEM(OXNAS_RPSA_BASE_VA + 0x108) -#define RPSA_FIQ_DISABLE IOMEM(OXNAS_RPSA_BASE_VA + 0x10C) -#define RPSA_FIQ_IRQ_TO_FIQ IOMEM(OXNAS_RPSA_BASE_VA + 0x1FC) - -#define RPSC_IRQ_SOFT IOMEM(OXNAS_RPSC_BASE_VA + 0x10) -#define RPSC_FIQ_ENABLE IOMEM(OXNAS_RPSC_BASE_VA + 0x108) -#define RPSC_FIQ_DISABLE IOMEM(OXNAS_RPSC_BASE_VA + 0x10C) -#define RPSC_FIQ_IRQ_TO_FIQ IOMEM(OXNAS_RPSC_BASE_VA + 0x1FC) - -#define RPSA_TIMER2_VAL IOMEM(OXNAS_RPSA_BASE_VA + 0x224) - -#define REF300_DIV_INT_SHIFT 8 -#define REF300_DIV_FRAC_SHIFT 0 -#define REF300_DIV_INT(val) ((val) << REF300_DIV_INT_SHIFT) -#define REF300_DIV_FRAC(val) ((val) << REF300_DIV_FRAC_SHIFT) - -#define USBHSPHY_SUSPENDM_MANUAL_ENABLE 16 -#define USBHSPHY_SUSPENDM_MANUAL_STATE 15 -#define USBHSPHY_ATE_ESET 14 -#define USBHSPHY_TEST_DIN 6 -#define USBHSPHY_TEST_ADD 2 -#define USBHSPHY_TEST_DOUT_SEL 1 -#define USBHSPHY_TEST_CLK 0 - -#define USB_CTRL_USBAPHY_CKSEL_SHIFT 5 -#define USB_CLK_XTAL0_XTAL1 (0 << USB_CTRL_USBAPHY_CKSEL_SHIFT) -#define USB_CLK_XTAL0 (1 << USB_CTRL_USBAPHY_CKSEL_SHIFT) -#define USB_CLK_INTERNAL (2 << USB_CTRL_USBAPHY_CKSEL_SHIFT) - -#define USBAMUX_DEVICE BIT(4) - -#define USBPHY_REFCLKDIV_SHIFT 2 -#define USB_PHY_REF_12MHZ (0 << USBPHY_REFCLKDIV_SHIFT) -#define USB_PHY_REF_24MHZ (1 << USBPHY_REFCLKDIV_SHIFT) -#define USB_PHY_REF_48MHZ (2 << USBPHY_REFCLKDIV_SHIFT) - -#define USB_CTRL_USB_CKO_SEL_BIT 0 - -#define USB_INT_CLK_XTAL 0 -#define USB_INT_CLK_REF300 2 -#define USB_INT_CLK_PLLB 3 - -#define SYS_CTRL_GMAC_CKEN_RX_IN 14 -#define SYS_CTRL_GMAC_CKEN_RXN_OUT 13 -#define SYS_CTRL_GMAC_CKEN_RX_OUT 12 -#define SYS_CTRL_GMAC_CKEN_TX_IN 10 -#define SYS_CTRL_GMAC_CKEN_TXN_OUT 9 -#define SYS_CTRL_GMAC_CKEN_TX_OUT 8 -#define SYS_CTRL_GMAC_RX_SOURCE 7 -#define SYS_CTRL_GMAC_TX_SOURCE 6 -#define SYS_CTRL_GMAC_LOW_TX_SOURCE 4 -#define SYS_CTRL_GMAC_AUTO_TX_SOURCE 3 -#define SYS_CTRL_GMAC_RGMII 2 -#define SYS_CTRL_GMAC_SIMPLE_MUX 1 -#define SYS_CTRL_GMAC_CKEN_GTX 0 -#define SYS_CTRL_GMAC_TX_VARDELAY_SHIFT 0 -#define SYS_CTRL_GMAC_TXN_VARDELAY_SHIFT 8 -#define SYS_CTRL_GMAC_RX_VARDELAY_SHIFT 16 -#define SYS_CTRL_GMAC_RXN_VARDELAY_SHIFT 24 -#define SYS_CTRL_GMAC_TX_VARDELAY(d) ((d)<<SYS_CTRL_GMAC_TX_VARDELAY_SHIFT) -#define SYS_CTRL_GMAC_TXN_VARDELAY(d) ((d)<<SYS_CTRL_GMAC_TXN_VARDELAY_SHIFT) -#define SYS_CTRL_GMAC_RX_VARDELAY(d) ((d)<<SYS_CTRL_GMAC_RX_VARDELAY_SHIFT) -#define SYS_CTRL_GMAC_RXN_VARDELAY(d) ((d)<<SYS_CTRL_GMAC_RXN_VARDELAY_SHIFT) - -#define PLLB_BYPASS 1 -#define PLLB_ENSAT 3 -#define PLLB_OUTDIV 4 -#define PLLB_REFDIV 8 -#define PLLB_DIV_INT_SHIFT 8 -#define PLLB_DIV_FRAC_SHIFT 0 -#define PLLB_DIV_INT(val) ((val) << PLLB_DIV_INT_SHIFT) -#define PLLB_DIV_FRAC(val) ((val) << PLLB_DIV_FRAC_SHIFT) - -#define SYS_CTRL_CKCTRL_PCI_DIV_BIT 0 -#define SYS_CTRL_CKCTRL_SLOW_BIT 8 - -#define SYS_CTRL_UART2_DEQ_EN 0 -#define SYS_CTRL_UART3_DEQ_EN 1 -#define SYS_CTRL_UART3_IQ_EN 2 -#define SYS_CTRL_UART4_IQ_EN 3 -#define SYS_CTRL_UART4_NOT_PCI_MODE 4 - -#define SYS_CTRL_PCI_CTRL1_PCI_STATIC_RQ_BIT 11 - -#define PLLA_REFDIV_MASK 0x3F -#define PLLA_REFDIV_SHIFT 8 -#define PLLA_OUTDIV_MASK 0x7 -#define PLLA_OUTDIV_SHIFT 4 - -/* bit numbers of clock control register */ -#define SYS_CTRL_CLK_COPRO 0 -#define SYS_CTRL_CLK_DMA 1 -#define SYS_CTRL_CLK_CIPHER 2 -#define SYS_CTRL_CLK_SD 3 -#define SYS_CTRL_CLK_SATA 4 -#define SYS_CTRL_CLK_I2S 5 -#define SYS_CTRL_CLK_USBHS 6 -#define SYS_CTRL_CLK_MACA 7 -#define SYS_CTRL_CLK_MAC SYS_CTRL_CLK_MACA -#define SYS_CTRL_CLK_PCIEA 8 -#define SYS_CTRL_CLK_STATIC 9 -#define SYS_CTRL_CLK_MACB 10 -#define SYS_CTRL_CLK_PCIEB 11 -#define SYS_CTRL_CLK_REF600 12 -#define SYS_CTRL_CLK_USBDEV 13 -#define SYS_CTRL_CLK_DDR 14 -#define SYS_CTRL_CLK_DDRPHY 15 -#define SYS_CTRL_CLK_DDRCK 16 - - -/* bit numbers of reset control register */ -#define SYS_CTRL_RST_SCU 0 -#define SYS_CTRL_RST_COPRO 1 -#define SYS_CTRL_RST_ARM0 2 -#define SYS_CTRL_RST_ARM1 3 -#define SYS_CTRL_RST_USBHS 4 -#define SYS_CTRL_RST_USBHSPHYA 5 -#define SYS_CTRL_RST_MACA 6 -#define SYS_CTRL_RST_MAC SYS_CTRL_RST_MACA -#define SYS_CTRL_RST_PCIEA 7 -#define SYS_CTRL_RST_SGDMA 8 -#define SYS_CTRL_RST_CIPHER 9 -#define SYS_CTRL_RST_DDR 10 -#define SYS_CTRL_RST_SATA 11 -#define SYS_CTRL_RST_SATA_LINK 12 -#define SYS_CTRL_RST_SATA_PHY 13 -#define SYS_CTRL_RST_PCIEPHY 14 -#define SYS_CTRL_RST_STATIC 15 -#define SYS_CTRL_RST_GPIO 16 -#define SYS_CTRL_RST_UART1 17 -#define SYS_CTRL_RST_UART2 18 -#define SYS_CTRL_RST_MISC 19 -#define SYS_CTRL_RST_I2S 20 -#define SYS_CTRL_RST_SD 21 -#define SYS_CTRL_RST_MACB 22 -#define SYS_CTRL_RST_PCIEB 23 -#define SYS_CTRL_RST_VIDEO 24 -#define SYS_CTRL_RST_DDR_PHY 25 -#define SYS_CTRL_RST_USBHSPHYB 26 -#define SYS_CTRL_RST_USBDEV 27 -#define SYS_CTRL_RST_ARMDBG 29 -#define SYS_CTRL_RST_PLLA 30 -#define SYS_CTRL_RST_PLLB 31 - -#endif diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/iomap.h b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/iomap.h deleted file mode 100644 index 01de7b78ef..0000000000 --- a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/iomap.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef __MACH_OXNAS_IOMAP_H -#define __MACH_OXNAS_IOMAP_H - -#include <linux/sizes.h> - -#define OXNAS_UART1_BASE 0x44200000 -#define OXNAS_UART1_SIZE SZ_32 -#define OXNAS_UART1_BASE_VA 0xF0000000 - -#define OXNAS_UART2_BASE 0x44300000 -#define OXNAS_UART2_SIZE SZ_32 - -#define OXNAS_PERCPU_BASE 0x47000000 -#define OXNAS_PERCPU_SIZE SZ_8K -#define OXNAS_PERCPU_BASE_VA 0xF0002000 - -#define OXNAS_SYSCRTL_BASE 0x44E00000 -#define OXNAS_SYSCRTL_SIZE SZ_4K -#define OXNAS_SYSCRTL_BASE_VA 0xF0004000 - -#define OXNAS_SECCRTL_BASE 0x44F00000 -#define OXNAS_SECCRTL_SIZE SZ_4K -#define OXNAS_SECCRTL_BASE_VA 0xF0005000 - -#define OXNAS_RPSA_BASE 0x44400000 -#define OXNAS_RPSA_SIZE SZ_4K -#define OXNAS_RPSA_BASE_VA 0xF0006000 - -#define OXNAS_RPSC_BASE 0x44500000 -#define OXNAS_RPSC_SIZE SZ_4K -#define OXNAS_RPSC_BASE_VA 0xF0007000 - -#endif diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/irqs.h b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/irqs.h deleted file mode 100644 index bcafd10ae0..0000000000 --- a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/irqs.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - -#define IRQ_SOFT 1 -#define NR_IRQS 160 - -#endif diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/smp.h b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/smp.h deleted file mode 100644 index 1128635963..0000000000 --- a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/smp.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * smp.h - * - * Created on: Sep 24, 2013 - * Author: mahaijun - */ - -#ifndef _NAS782X_SMP_H_ -#define _NAS782X_SMP_H_ - -#include <mach/hardware.h> - -extern void ox820_secondary_startup(void); -extern void ox820_cpu_die(unsigned int cpu); - -static inline void write_pen_release(int val) -{ - writel(val, HOLDINGPEN_CPU); -} - -static inline int read_pen_release(void) -{ - return readl(HOLDINGPEN_CPU); -} - -extern struct smp_operations ox820_smp_ops; - -extern unsigned char ox820_fiq_start, ox820_fiq_end; -extern void v6_dma_map_area(const void *, size_t, int); -extern void v6_dma_unmap_area(const void *, size_t, int); -extern void v6_dma_flush_range(const void *, const void *); -extern void v6_flush_kern_dcache_area(void *, size_t); - -#endif /* _NAS782X_SMP_H_ */ diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/timex.h b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/timex.h deleted file mode 100644 index 4133594d16..0000000000 --- a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/timex.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ASM_ARCH_TIMEX_H -#define __ASM_ARCH_TIMEX_H - -#define CLOCK_TICK_RATE 6250000 - -#endif diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/uncompress.h b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/uncompress.h deleted file mode 100644 index fbc372787e..0000000000 --- a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/uncompress.h +++ /dev/null @@ -1,32 +0,0 @@ -/* linux/include/asm-arm/arch-oxnas/uncompress.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_UNCOMPRESS_H -#define __ASM_ARCH_UNCOMPRESS_H - -#define OXNAS_UART1_BASE 0x44200000 - -static inline void putc(int c) -{ - static volatile unsigned char *uart = - (volatile unsigned char *)OXNAS_UART1_BASE; - - while (!(uart[5] & 0x20)) { /* LSR reg THR empty bit */ - barrier(); - } - uart[0] = c; /* THR register */ -} - -static inline void flush(void) -{ -} - -#define arch_decomp_setup() - -#define arch_decomp_wdog() - -#endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/utils.h b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/utils.h deleted file mode 100644 index 910d7019c7..0000000000 --- a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/utils.h +++ /dev/null @@ -1,34 +0,0 @@ -#ifndef _NAS782X_UTILS_H -#define _NAS782X_UTILS_H - -#include <linux/io.h> -#include <mach/hardware.h> - -static inline void oxnas_register_clear_mask(void __iomem *p, unsigned mask) -{ - u32 val = readl_relaxed(p); - - val &= ~mask; - writel_relaxed(val, p); -} - -static inline void oxnas_register_set_mask(void __iomem *p, unsigned mask) -{ - u32 val = readl_relaxed(p); - - val |= mask; - writel_relaxed(val, p); -} - -static inline void oxnas_register_value_mask(void __iomem *p, - unsigned mask, unsigned new_value) -{ - /* TODO sanity check mask & new_value = new_value */ - u32 val = readl_relaxed(p); - - val &= ~mask; - val |= new_value; - writel_relaxed(val, p); -} - -#endif /* _NAS782X_UTILS_H */ diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/mach-ox820.c b/target/linux/oxnas/files/arch/arm/mach-oxnas/mach-ox820.c deleted file mode 100644 index 31b7c90582..0000000000 --- a/target/linux/oxnas/files/arch/arm/mach-oxnas/mach-ox820.c +++ /dev/null @@ -1,183 +0,0 @@ -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/bug.h> -#include <linux/of_platform.h> -#include <linux/clocksource.h> -#include <linux/clk-provider.h> -#include <linux/clk.h> -#include <linux/slab.h> -#include <linux/gfp.h> -#include <linux/reset.h> -#include <asm/mach-types.h> -#include <asm/mach/map.h> -#include <asm/mach/arch.h> -#include <asm/page.h> -#include <mach/iomap.h> -#include <mach/hardware.h> -#include <mach/utils.h> -#include <mach/smp.h> - -static struct map_desc ox820_io_desc[] __initdata = { - { - .virtual = (unsigned long)OXNAS_PERCPU_BASE_VA, - .pfn = __phys_to_pfn(OXNAS_PERCPU_BASE), - .length = OXNAS_PERCPU_SIZE, - .type = MT_DEVICE, - }, - { - .virtual = (unsigned long)OXNAS_SYSCRTL_BASE_VA, - .pfn = __phys_to_pfn(OXNAS_SYSCRTL_BASE), - .length = OXNAS_SYSCRTL_SIZE, - .type = MT_DEVICE, - }, - { - .virtual = (unsigned long)OXNAS_SECCRTL_BASE_VA, - .pfn = __phys_to_pfn(OXNAS_SECCRTL_BASE), - .length = OXNAS_SECCRTL_SIZE, - .type = MT_DEVICE, - }, - { - .virtual = (unsigned long)OXNAS_RPSA_BASE_VA, - .pfn = __phys_to_pfn(OXNAS_RPSA_BASE), - .length = OXNAS_RPSA_SIZE, - .type = MT_DEVICE, - }, - { - .virtual = (unsigned long)OXNAS_RPSC_BASE_VA, - .pfn = __phys_to_pfn(OXNAS_RPSC_BASE), - .length = OXNAS_RPSC_SIZE, - .type = MT_DEVICE, - }, -}; - -void __init ox820_map_common_io(void) -{ - debug_ll_io_init(); - iotable_init(ox820_io_desc, ARRAY_SIZE(ox820_io_desc)); -} - -static void __init ox820_dt_init(void) -{ - int ret; - - ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, - NULL); - - if (ret) { - pr_err("of_platform_populate failed: %d\n", ret); - BUG(); - } - -} - -static void __init ox820_timer_init(void) -{ - of_clk_init(NULL); - clocksource_probe(); -} - -void ox820_init_early(void) -{ - -} - -void ox820_assert_system_reset(enum reboot_mode mode, const char *cmd) -{ - u32 value; - -/* Assert reset to cores as per power on defaults - * Don't touch the DDR interface as things will come to an impromptu stop - * NB Possibly should be asserting reset for PLLB, but there are timing - * concerns here according to the docs */ - value = BIT(SYS_CTRL_RST_COPRO) | - BIT(SYS_CTRL_RST_USBHS) | - BIT(SYS_CTRL_RST_USBHSPHYA) | - BIT(SYS_CTRL_RST_MACA) | - BIT(SYS_CTRL_RST_PCIEA) | - BIT(SYS_CTRL_RST_SGDMA) | - BIT(SYS_CTRL_RST_CIPHER) | - BIT(SYS_CTRL_RST_SATA) | - BIT(SYS_CTRL_RST_SATA_LINK) | - BIT(SYS_CTRL_RST_SATA_PHY) | - BIT(SYS_CTRL_RST_PCIEPHY) | - BIT(SYS_CTRL_RST_STATIC) | - BIT(SYS_CTRL_RST_UART1) | - BIT(SYS_CTRL_RST_UART2) | - BIT(SYS_CTRL_RST_MISC) | - BIT(SYS_CTRL_RST_I2S) | - BIT(SYS_CTRL_RST_SD) | - BIT(SYS_CTRL_RST_MACB) | - BIT(SYS_CTRL_RST_PCIEB) | - BIT(SYS_CTRL_RST_VIDEO) | - BIT(SYS_CTRL_RST_USBHSPHYB) | - BIT(SYS_CTRL_RST_USBDEV); - - writel(value, SYS_CTRL_RST_SET_CTRL); - - /* Release reset to cores as per power on defaults */ - writel(BIT(SYS_CTRL_RST_GPIO), SYS_CTRL_RST_CLR_CTRL); - - /* Disable clocks to cores as per power-on defaults - must leave DDR - * related clocks enabled otherwise we'll stop rather abruptly. */ - value = - BIT(SYS_CTRL_CLK_COPRO) | - BIT(SYS_CTRL_CLK_DMA) | - BIT(SYS_CTRL_CLK_CIPHER) | - BIT(SYS_CTRL_CLK_SD) | - BIT(SYS_CTRL_CLK_SATA) | - BIT(SYS_CTRL_CLK_I2S) | - BIT(SYS_CTRL_CLK_USBHS) | - BIT(SYS_CTRL_CLK_MAC) | - BIT(SYS_CTRL_CLK_PCIEA) | - BIT(SYS_CTRL_CLK_STATIC) | - BIT(SYS_CTRL_CLK_MACB) | - BIT(SYS_CTRL_CLK_PCIEB) | - BIT(SYS_CTRL_CLK_REF600) | - BIT(SYS_CTRL_CLK_USBDEV); - - writel(value, SYS_CTRL_CLK_CLR_CTRL); - - /* Enable clocks to cores as per power-on defaults */ - - /* Set sys-control pin mux'ing as per power-on defaults */ - writel(0, SYS_CTRL_SECONDARY_SEL); - writel(0, SYS_CTRL_TERTIARY_SEL); - writel(0, SYS_CTRL_QUATERNARY_SEL); - writel(0, SYS_CTRL_DEBUG_SEL); - writel(0, SYS_CTRL_ALTERNATIVE_SEL); - writel(0, SYS_CTRL_PULLUP_SEL); - - writel(0, SEC_CTRL_SECONDARY_SEL); - writel(0, SEC_CTRL_TERTIARY_SEL); - writel(0, SEC_CTRL_QUATERNARY_SEL); - writel(0, SEC_CTRL_DEBUG_SEL); - writel(0, SEC_CTRL_ALTERNATIVE_SEL); - writel(0, SEC_CTRL_PULLUP_SEL); - - /* No need to save any state, as the ROM loader can determine whether - * reset is due to power cycling or programatic action, just hit the - * (self-clearing) CPU reset bit of the block reset register */ - value = - BIT(SYS_CTRL_RST_SCU) | - BIT(SYS_CTRL_RST_ARM0) | - BIT(SYS_CTRL_RST_ARM1); - - writel(value, SYS_CTRL_RST_SET_CTRL); -} - -static const char * const ox820_dt_board_compat[] = { - "plxtech,nas7820", - "plxtech,nas7821", - "plxtech,nas7825", - NULL -}; - -DT_MACHINE_START(OX820_DT, "PLXTECH NAS782X SoC (Flattened Device Tree)") - .map_io = ox820_map_common_io, - .smp = smp_ops(ox820_smp_ops), - .init_early = ox820_init_early, - .init_time = ox820_timer_init, - .init_machine = ox820_dt_init, - .restart = ox820_assert_system_reset, - .dt_compat = ox820_dt_board_compat, -MACHINE_END diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/platsmp.c b/target/linux/oxnas/files/arch/arm/mach-oxnas/platsmp.c deleted file mode 100644 index 8e4e2d8273..0000000000 --- a/target/linux/oxnas/files/arch/arm/mach-oxnas/platsmp.c +++ /dev/null @@ -1,315 +0,0 @@ -/* - * arch/arm/mach-ox820/platsmp.c - * - * Copyright (C) 2002 ARM Ltd. - * All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/init.h> -#include <linux/device.h> -#include <linux/jiffies.h> -#include <linux/smp.h> -#include <linux/io.h> -#include <linux/dma-mapping.h> -#include <linux/cache.h> -#include <asm/cacheflush.h> -#include <asm/smp_scu.h> -#include <asm/tlbflush.h> -#include <asm/cputype.h> -#include <linux/delay.h> -#include <asm/fiq.h> - -#include <linux/irqchip/arm-gic.h> -#include <mach/iomap.h> -#include <mach/smp.h> -#include <mach/hardware.h> -#include <mach/irqs.h> - -#ifdef CONFIG_DMA_CACHE_FIQ_BROADCAST - -#define FIQ_GENERATE 0x00000002 -#define OXNAS_MAP_AREA 0x01000000 -#define OXNAS_UNMAP_AREA 0x02000000 -#define OXNAS_FLUSH_RANGE 0x03000000 - -struct fiq_req { - union { - struct { - const void *addr; - size_t size; - } map; - struct { - const void *addr; - size_t size; - } unmap; - struct { - const void *start; - const void *end; - } flush; - }; - volatile uint flags; - void __iomem *reg; -} ____cacheline_aligned; - -static struct fiq_handler fh = { - .name = "oxnas-fiq" -}; - -DEFINE_PER_CPU(struct fiq_req, fiq_data); - -static inline void ox820_set_fiq_regs(unsigned int cpu) -{ - struct pt_regs FIQ_regs; - struct fiq_req *fiq_req = &per_cpu(fiq_data, !cpu); - - FIQ_regs.ARM_r8 = 0; - FIQ_regs.ARM_ip = (unsigned int)fiq_req; - FIQ_regs.ARM_sp = (int)(cpu ? RPSC_IRQ_SOFT : RPSA_IRQ_SOFT); - fiq_req->reg = cpu ? RPSC_IRQ_SOFT : RPSA_IRQ_SOFT; - - set_fiq_regs(&FIQ_regs); -} - -static void __init ox820_init_fiq(void) -{ - void *fiqhandler_start; - unsigned int fiqhandler_length; - int ret; - - fiqhandler_start = &ox820_fiq_start; - fiqhandler_length = &ox820_fiq_end - &ox820_fiq_start; - - ret = claim_fiq(&fh); - - if (ret) - return; - - set_fiq_handler(fiqhandler_start, fiqhandler_length); - - writel(IRQ_SOFT, RPSA_FIQ_IRQ_TO_FIQ); - writel(1, RPSA_FIQ_ENABLE); - writel(IRQ_SOFT, RPSC_FIQ_IRQ_TO_FIQ); - writel(1, RPSC_FIQ_ENABLE); -} - -void fiq_dma_map_area(const void *addr, size_t size, int dir) -{ - unsigned long flags; - struct fiq_req *req; - - raw_local_irq_save(flags); - /* currently, not possible to take cpu0 down, so only check cpu1 */ - if (!cpu_online(1)) { - raw_local_irq_restore(flags); - v6_dma_map_area(addr, size, dir); - return; - } - - req = this_cpu_ptr(&fiq_data); - req->map.addr = addr; - req->map.size = size; - req->flags = dir | OXNAS_MAP_AREA; - smp_mb(); - - writel_relaxed(FIQ_GENERATE, req->reg); - - v6_dma_map_area(addr, size, dir); - while (req->flags) - barrier(); - - raw_local_irq_restore(flags); -} - -void fiq_dma_unmap_area(const void *addr, size_t size, int dir) -{ - unsigned long flags; - struct fiq_req *req; - - raw_local_irq_save(flags); - /* currently, not possible to take cpu0 down, so only check cpu1 */ - if (!cpu_online(1)) { - raw_local_irq_restore(flags); - v6_dma_unmap_area(addr, size, dir); - return; - } - - req = this_cpu_ptr(&fiq_data); - req->unmap.addr = addr; - req->unmap.size = size; - req->flags = dir | OXNAS_UNMAP_AREA; - smp_mb(); - - writel_relaxed(FIQ_GENERATE, req->reg); - - v6_dma_unmap_area(addr, size, dir); - while (req->flags) - barrier(); - - raw_local_irq_restore(flags); -} - -void fiq_dma_flush_range(const void *start, const void *end) -{ - unsigned long flags; - struct fiq_req *req; - - raw_local_irq_save(flags); - /* currently, not possible to take cpu0 down, so only check cpu1 */ - if (!cpu_online(1)) { - raw_local_irq_restore(flags); - v6_dma_flush_range(start, end); - return; - } - - req = this_cpu_ptr(&fiq_data); - - req->flush.start = start; - req->flush.end = end; - req->flags = OXNAS_FLUSH_RANGE; - smp_mb(); - - writel_relaxed(FIQ_GENERATE, req->reg); - - v6_dma_flush_range(start, end); - - while (req->flags) - barrier(); - - raw_local_irq_restore(flags); -} - -void fiq_flush_kern_dcache_area(void *addr, size_t size) -{ - fiq_dma_flush_range(addr, addr + size); -} -#else - -#define ox820_set_fiq_regs(cpu) do {} while (0) /* nothing */ -#define ox820_init_fiq() do {} while (0) /* nothing */ - -#endif /* DMA_CACHE_FIQ_BROADCAST */ - -static DEFINE_SPINLOCK(boot_lock); - -void ox820_secondary_init(unsigned int cpu) -{ - /* - * Setup Secondary Core FIQ regs - */ - ox820_set_fiq_regs(1); - - /* - * let the primary processor know we're out of the - * pen, then head off into the C entry point - */ - write_pen_release(-1); - - /* - * Synchronise with the boot thread. - */ - spin_lock(&boot_lock); - spin_unlock(&boot_lock); -} - -int ox820_boot_secondary(unsigned int cpu, struct task_struct *idle) -{ - unsigned long timeout; - - /* - * Set synchronisation state between this boot processor - * and the secondary one - */ - spin_lock(&boot_lock); - - /* - * This is really belt and braces; we hold unintended secondary - * CPUs in the holding pen until we're ready for them. However, - * since we haven't sent them a soft interrupt, they shouldn't - * be there. - */ - write_pen_release(cpu); - - writel(1, IOMEM(OXNAS_GICN_BASE_VA(cpu) + GIC_CPU_CTRL)); - - /* - * Send the secondary CPU a soft interrupt, thereby causing - * the boot monitor to read the system wide flags register, - * and branch to the address found there. - */ - - arch_send_wakeup_ipi_mask(cpumask_of(cpu)); - timeout = jiffies + (1 * HZ); - while (time_before(jiffies, timeout)) { - smp_rmb(); - if (read_pen_release() == -1) - break; - - udelay(10); - } - - /* - * now the secondary core is starting up let it run its - * calibrations, then wait for it to finish - */ - spin_unlock(&boot_lock); - - return read_pen_release() != -1 ? -ENOSYS : 0; -} - -void *scu_base_addr(void) -{ - return IOMEM(OXNAS_SCU_BASE_VA); -} - -/* - * Initialise the CPU possible map early - this describes the CPUs - * which may be present or become present in the system. - */ -static void __init ox820_smp_init_cpus(void) -{ - void __iomem *scu_base = scu_base_addr(); - unsigned int i, ncores; - - ncores = scu_base ? scu_get_core_count(scu_base) : 1; - - /* sanity check */ - if (ncores > nr_cpu_ids) { - pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", - ncores, nr_cpu_ids); - ncores = nr_cpu_ids; - } - - for (i = 0; i < ncores; i++) - set_cpu_possible(i, true); -} - -static void __init ox820_smp_prepare_cpus(unsigned int max_cpus) -{ - - scu_enable(scu_base_addr()); - - /* - * Write the address of secondary startup into the - * system-wide flags register. The BootMonitor waits - * until it receives a soft interrupt, and then the - * secondary CPU branches to this address. - */ - writel(virt_to_phys(ox820_secondary_startup), - HOLDINGPEN_LOCATION); - ox820_init_fiq(); - - ox820_set_fiq_regs(0); -} - -struct smp_operations ox820_smp_ops __initdata = { - .smp_init_cpus = ox820_smp_init_cpus, - .smp_prepare_cpus = ox820_smp_prepare_cpus, - .smp_secondary_init = ox820_secondary_init, - .smp_boot_secondary = ox820_boot_secondary, -#ifdef CONFIG_HOTPLUG_CPU - .cpu_die = ox820_cpu_die, -#endif -}; diff --git a/target/linux/oxnas/files/drivers/ata/sata_oxnas.c b/target/linux/oxnas/files/drivers/ata/sata_oxnas.c deleted file mode 100644 index 291a06f959..0000000000 --- a/target/linux/oxnas/files/drivers/ata/sata_oxnas.c +++ /dev/null @@ -1,2477 +0,0 @@ -/* - * sata_oxnas - * A driver to interface the 934 based sata core present in the ox820 - * with libata and scsi - * based on sata_oxnas driver by Ma Haijun <mahaijuns@gmail.com> - * based on ox820 sata code by: - * Copyright (c) 2007 Oxford Semiconductor Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/ata.h> -#include <linux/libata.h> -#include <linux/of_platform.h> -#include <linux/delay.h> -#include <linux/module.h> -#include <linux/slab.h> -#include <linux/spinlock.h> -#include <linux/of_address.h> -#include <linux/of_irq.h> -#include <linux/clk.h> -#include <linux/reset.h> - -#include <mach/utils.h> - -/* sgdma request structure */ -struct sgdma_request { - volatile u32 qualifier; - volatile u32 control; - dma_addr_t src_pa; - dma_addr_t dst_pa; -} __packed __aligned(4); - - -/* Controller information */ -enum { - SATA_OXNAS_MAX_PRD = 254, - SATA_OXNAS_DMA_SIZE = SATA_OXNAS_MAX_PRD * - sizeof(struct ata_bmdma_prd) + - sizeof(struct sgdma_request), - SATA_OXNAS_MAX_PORTS = 2, - /** The different Oxsemi SATA core version numbers */ - SATA_OXNAS_CORE_VERSION = 0x1f3, - SATA_OXNAS_IRQ_FLAG = IRQF_SHARED, - SATA_OXNAS_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA | - ATA_FLAG_NO_ATAPI /*| ATA_FLAG_NCQ*/), - SATA_OXNAS_QUEUE_DEPTH = 32, - - SATA_OXNAS_DMA_BOUNDARY = 0xFFFFFFFF, -}; - - -/* - * SATA Port Registers - */ -enum { - /** sata host port register offsets */ - ORB1 = 0x00, - ORB2 = 0x04, - ORB3 = 0x08, - ORB4 = 0x0C, - ORB5 = 0x10, - MASTER_STATUS = 0x10, - FIS_CTRL = 0x18, - FIS_DATA = 0x1C, - INT_STATUS = 0x30, - INT_CLEAR = 0x30, - INT_ENABLE = 0x34, - INT_DISABLE = 0x38, - VERSION = 0x3C, - SATA_CONTROL = 0x5C, - SATA_COMMAND = 0x60, - HID_FEATURES = 0x64, - PORT_CONTROL = 0x68, - DRIVE_CONTROL = 0x6C, - /** These registers allow access to the link layer registers - that reside in a different clock domain to the processor bus */ - LINK_DATA = 0x70, - LINK_RD_ADDR = 0x74, - LINK_WR_ADDR = 0x78, - LINK_CONTROL = 0x7C, - /* window control */ - WIN1LO = 0x80, - WIN1HI = 0x84, - WIN2LO = 0x88, - WIN2HI = 0x8C, - WIN0_CONTROL = 0x90, -}; - -/** sata port register bits */ -enum{ - /** - * commands to issue in the master status to tell it to move shadow , - * registers to the actual device , - */ - SATA_OPCODE_MASK = 0x00000007, - CMD_WRITE_TO_ORB_REGS_NO_COMMAND = 0x4, - CMD_WRITE_TO_ORB_REGS = 0x2, - CMD_SYNC_ESCAPE = 0x7, - CMD_CORE_BUSY = (1 << 7), - CMD_DRIVE_SELECT_SHIFT = 12, - CMD_DRIVE_SELECT_MASK = (0xf << CMD_DRIVE_SELECT_SHIFT), - - /** interrupt bits */ - INT_END_OF_CMD = 1 << 0, - INT_LINK_SERROR = 1 << 1, - INT_ERROR = 1 << 2, - INT_LINK_IRQ = 1 << 3, - INT_REG_ACCESS_ERR = 1 << 7, - INT_BIST_FIS = 1 << 11, - INT_MASKABLE = INT_END_OF_CMD | - INT_LINK_SERROR | - INT_ERROR | - INT_LINK_IRQ | - INT_REG_ACCESS_ERR | - INT_BIST_FIS, - INT_WANT = INT_END_OF_CMD | - INT_LINK_SERROR | - INT_REG_ACCESS_ERR | - INT_ERROR, - INT_ERRORS = INT_LINK_SERROR | - INT_REG_ACCESS_ERR | - INT_ERROR, - - /** raw interrupt bits, unmaskable, but do not generate interrupts */ - RAW_END_OF_CMD = INT_END_OF_CMD << 16, - RAW_LINK_SERROR = INT_LINK_SERROR << 16, - RAW_ERROR = INT_ERROR << 16, - RAW_LINK_IRQ = INT_LINK_IRQ << 16, - RAW_REG_ACCESS_ERR = INT_REG_ACCESS_ERR << 16, - RAW_BIST_FIS = INT_BIST_FIS << 16, - RAW_WANT = INT_WANT << 16, - RAW_ERRORS = INT_ERRORS << 16, - - /** - * variables to write to the device control register to set the current - * device, ie. master or slave. - */ - DR_CON_48 = 2, - DR_CON_28 = 0, - - SATA_CTL_ERR_MASK = 0x00000016, - -}; - -/* ATA SGDMA register offsets */ -enum { - SGDMA_CONTROL = 0x0, - SGDMA_STATUS = 0x4, - SGDMA_REQUESTPTR = 0x8, - SGDMA_RESETS = 0xC, - SGDMA_CORESIZE = 0x10, -}; - -/* DMA controller register offsets */ -enum { - DMA_CONTROL = 0x0, - DMA_CORESIZE = 0x20, - - DMA_CONTROL_RESET = (1 << 12), -}; - -enum { - /* see DMA core docs for the values. Out means from memory (bus A) out - * to disk (bus B) */ - SGDMA_REQCTL0OUT = 0x0497c03d, - /* burst mode disabled when no micro code used */ - SGDMA_REQCTL0IN = 0x0493a3c1, - SGDMA_REQCTL1OUT = 0x0497c07d, - SGDMA_REQCTL1IN = 0x0497a3c5, - SGDMA_CONTROL_NOGO = 0x3e, - SGDMA_CONTROL_GO = SGDMA_CONTROL_NOGO | 1, - SGDMA_ERRORMASK = 0x3f, - SGDMA_BUSY = 0x80, - - SGDMA_RESETS_CTRL = 1 << 0, - SGDMA_RESETS_ARBT = 1 << 1, - SGDMA_RESETS_AHB = 1 << 2, - SGDMA_RESETS_ALL = SGDMA_RESETS_CTRL | - SGDMA_RESETS_ARBT | - SGDMA_RESETS_AHB, - - /* Final EOTs */ - SGDMA_REQQUAL = 0x00220001, - -}; - -/** SATA core register offsets */ -enum { - DM_DBG1 = 0x000, - RAID_SET = 0x004, - DM_DBG2 = 0x008, - DATACOUNT_PORT0 = 0x010, - DATACOUNT_PORT1 = 0x014, - CORE_INT_STATUS = 0x030, - CORE_INT_CLEAR = 0x030, - CORE_INT_ENABLE = 0x034, - CORE_INT_DISABLE = 0x038, - CORE_REBUILD_ENABLE = 0x050, - CORE_FAILED_PORT_R = 0x054, - DEVICE_CONTROL = 0x068, - EXCESS = 0x06C, - RAID_SIZE_LOW = 0x070, - RAID_SIZE_HIGH = 0x074, - PORT_ERROR_MASK = 0x078, - IDLE_STATUS = 0x07C, - RAID_CONTROL = 0x090, - DATA_PLANE_CTRL = 0x0AC, - CORE_DATAPLANE_STAT = 0x0b8, - PROC_PC = 0x100, - CONFIG_IN = 0x3d8, - PROC_START = 0x3f0, - PROC_RESET = 0x3f4, - UCODE_STORE = 0x1000, - RAID_WP_BOT_LOW = 0x1FF0, - RAID_WP_BOT_HIGH = 0x1FF4, - RAID_WP_TOP_LOW = 0x1FF8, - RAID_WP_TOP_HIGH = 0x1FFC, - DATA_MUX_RAM0 = 0x8000, - DATA_MUX_RAM1 = 0xA000, - PORT_SIZE = 0x10000, -}; - -enum { - /* Sata core debug1 register bits */ - CORE_PORT0_DATA_DIR_BIT = 20, - CORE_PORT1_DATA_DIR_BIT = 21, - CORE_PORT0_DATA_DIR = 1 << CORE_PORT0_DATA_DIR_BIT, - CORE_PORT1_DATA_DIR = 1 << CORE_PORT1_DATA_DIR_BIT, - - /** sata core control register bits */ - SCTL_CLR_ERR = 0x00003016, - RAID_CLR_ERR = 0x0000011e, - - /* Interrupts direct from the ports */ - NORMAL_INTS_WANTED = 0x00000303, - - /* shift these left by port number */ - COREINT_HOST = 0x00000001, - COREINT_END = 0x00000100, - CORERAW_HOST = COREINT_HOST << 16, - CORERAW_END = COREINT_END << 16, - - /* Interrupts from the RAID controller only */ - RAID_INTS_WANTED = 0x00008300, - - /* The bits in the IDLE_STATUS that, when set indicate an idle core */ - IDLE_CORES = (1 << 18) | (1 << 19), - - /* Data plane control error-mask mask and bit, these bit in the data - * plane control mask out errors from the ports that prevent the SGDMA - * care from sending an interrupt */ - DPC_ERROR_MASK = 0x00000300, - DPC_ERROR_MASK_BIT = 0x00000100, - /* enable jbod micro-code */ - DPC_JBOD_UCODE = 1 << 0, - DPC_FIS_SWCH = 1 << 1, - - /** Device Control register bits */ - DEVICE_CONTROL_DMABT = 1 << 4, - DEVICE_CONTROL_ABORT = 1 << 2, - DEVICE_CONTROL_PAD = 1 << 3, - DEVICE_CONTROL_PADPAT = 1 << 16, - DEVICE_CONTROL_PRTRST = 1 << 8, - DEVICE_CONTROL_RAMRST = 1 << 12, - DEVICE_CONTROL_ATA_ERR_OVERRIDE = 1 << 28, - - /** oxsemi HW raid modes */ - OXNASSATA_NOTRAID = 0, - OXNASSATA_RAID0 = 1, - OXNASSATA_RAID1 = 2, - /** OX820 specific HW-RAID register values */ - RAID_TWODISKS = 3, - UNKNOWN_MODE = ~0, - - CONFIG_IN_RESUME = 2, -}; - -/* SATA PHY Registers */ -enum { - PHY_STAT = 0x00, - PHY_DATA = 0x04, -}; - -enum { - STAT_READ_VALID = (1 << 21), - STAT_CR_ACK = (1 << 20), - STAT_CR_READ = (1 << 19), - STAT_CR_WRITE = (1 << 18), - STAT_CAP_DATA = (1 << 17), - STAT_CAP_ADDR = (1 << 16), - - STAT_ACK_ANY = STAT_CR_ACK | - STAT_CR_READ | - STAT_CR_WRITE | - STAT_CAP_DATA | - STAT_CAP_ADDR, - - CR_READ_ENABLE = (1 << 16), - CR_WRITE_ENABLE = (1 << 17), - CR_CAP_DATA = (1 << 18), -}; - -enum { - /* Link layer registers */ - SERROR_IRQ_MASK = 5, -}; - -enum { - OXNAS_SATA_SOFTRESET = 1, - OXNAS_SATA_REINIT = 2, -}; - -enum { - OXNAS_SATA_UCODE_RAID0, - OXNAS_SATA_UCODE_RAID1, - OXNAS_SATA_UCODE_JBOD, - OXNAS_SATA_UCODE_NONE, -}; - -enum { - SATA_UNLOCKED, - SATA_WRITER, - SATA_READER, - SATA_REBUILD, - SATA_HWRAID, - SATA_SCSI_STACK -}; - -typedef irqreturn_t (*oxnas_sata_isr_callback_t)(int, unsigned long, int); - -struct sata_oxnas_host_priv { - void __iomem *port_base; - void __iomem *dmactl_base; - void __iomem *sgdma_base; - void __iomem *core_base; - void __iomem *phy_base; - dma_addr_t dma_base; - void __iomem *dma_base_va; - size_t dma_size; - int irq; - int n_ports; - int current_ucode; - u32 port_frozen; - u32 port_in_eh; - struct clk *clk; - struct reset_control *rst_sata; - struct reset_control *rst_link; - struct reset_control *rst_phy; - spinlock_t phy_lock; - spinlock_t core_lock; - int core_locked; - int reentrant_port_no; - int hw_lock_count; - int direct_lock_count; - void *locker_uid; - int current_locker_type; - int scsi_nonblocking_attempts; - oxnas_sata_isr_callback_t isr_callback; - void *isr_arg; - wait_queue_head_t fast_wait_queue; - wait_queue_head_t scsi_wait_queue; -}; - - -struct sata_oxnas_port_priv { - void __iomem *port_base; - void __iomem *dmactl_base; - void __iomem *sgdma_base; - void __iomem *core_base; - struct sgdma_request *sgdma_request; - dma_addr_t sgdma_request_pa; -}; - -static u8 sata_oxnas_check_status(struct ata_port *ap); -static int sata_oxnas_cleanup(struct ata_host *ah); -static void sata_oxnas_tf_load(struct ata_port *ap, - const struct ata_taskfile *tf); -static void sata_oxnas_irq_on(struct ata_port *ap); -static void sata_oxnas_post_reset_init(struct ata_port *ap); - -static int sata_oxnas_acquire_hw(struct ata_port *ap, int may_sleep, - int timeout_jiffies); -static void sata_oxnas_release_hw(struct ata_port *ap); - -static const void *HW_LOCKER_UID = (void *)0xdeadbeef; - -/*************************************************************************** -* ASIC access -***************************************************************************/ -static void wait_cr_ack(void __iomem *phy_base) -{ - while ((ioread32(phy_base + PHY_STAT) >> 16) & 0x1f) - ; /* wait for an ack bit to be set */ -} - -static u16 read_cr(void __iomem *phy_base, u16 address) -{ - iowrite32((u32)address, phy_base + PHY_STAT); - wait_cr_ack(phy_base); - iowrite32(CR_READ_ENABLE, phy_base + PHY_DATA); - wait_cr_ack(phy_base); - return (u16)ioread32(phy_base + PHY_STAT); -} - -static void write_cr(void __iomem *phy_base, u16 data, u16 address) -{ - iowrite32((u32)address, phy_base + PHY_STAT); - wait_cr_ack(phy_base); - iowrite32((data | CR_CAP_DATA), phy_base + PHY_DATA); - wait_cr_ack(phy_base); - iowrite32(CR_WRITE_ENABLE, phy_base + PHY_DATA); - wait_cr_ack(phy_base); -} - -#define PH_GAIN 2 -#define FR_GAIN 3 -#define PH_GAIN_OFFSET 6 -#define FR_GAIN_OFFSET 8 -#define PH_GAIN_MASK (0x3 << PH_GAIN_OFFSET) -#define FR_GAIN_MASK (0x3 << FR_GAIN_OFFSET) -#define USE_INT_SETTING (1<<5) - -void workaround5458(struct ata_host *ah) -{ - struct sata_oxnas_host_priv *hd = ah->private_data; - void __iomem *phy_base = hd->phy_base; - u16 rx_control; - unsigned i; - - for (i = 0; i < 2; i++) { - rx_control = read_cr(phy_base, 0x201d + (i << 8)); - rx_control &= ~(PH_GAIN_MASK | FR_GAIN_MASK); - rx_control |= PH_GAIN << PH_GAIN_OFFSET; - rx_control |= (FR_GAIN << FR_GAIN_OFFSET) | USE_INT_SETTING; - write_cr(phy_base, rx_control, 0x201d+(i<<8)); - } -} - -/** - * allows access to the link layer registers - * @param link_reg the link layer register to access (oxsemi indexing ie - * 00 = static config, 04 = phy ctrl) - */ -void sata_oxnas_link_write(struct ata_port *ap, unsigned int link_reg, u32 val) -{ - struct sata_oxnas_port_priv *pd = ap->private_data; - struct sata_oxnas_host_priv *hd = ap->host->private_data; - void __iomem *port_base = pd->port_base; - u32 patience; - unsigned long flags; - - DPRINTK("P%d [0x%02x]->0x%08x\n", ap->port_no, link_reg, val); - - spin_lock_irqsave(&hd->phy_lock, flags); - iowrite32(val, port_base + LINK_DATA); - - /* accessed twice as a work around for a bug in the SATA abp bridge - * hardware (bug 6828) */ - iowrite32(link_reg , port_base + LINK_WR_ADDR); - ioread32(port_base + LINK_WR_ADDR); - - for (patience = 0x100000; patience > 0; --patience) { - if (ioread32(port_base + LINK_CONTROL) & 0x00000001) - break; - } - spin_unlock_irqrestore(&hd->phy_lock, flags); -} - -static int sata_oxnas_scr_write_port(struct ata_port *ap, unsigned int sc_reg, - u32 val) -{ - sata_oxnas_link_write(ap, 0x20 + (sc_reg * 4), val); - return 0; -} - -static int sata_oxnas_scr_write(struct ata_link *link, unsigned int sc_reg, - u32 val) -{ - return sata_oxnas_scr_write_port(link->ap, sc_reg, val); -} - -u32 sata_oxnas_link_read(struct ata_port *ap, unsigned int link_reg) -{ - struct sata_oxnas_port_priv *pd = ap->private_data; - struct sata_oxnas_host_priv *hd = ap->host->private_data; - void __iomem *port_base = pd->port_base; - u32 result; - u32 patience; - unsigned long flags; - - spin_lock_irqsave(&hd->phy_lock, flags); - /* accessed twice as a work around for a bug in the SATA abp bridge - * hardware (bug 6828) */ - iowrite32(link_reg, port_base + LINK_RD_ADDR); - ioread32(port_base + LINK_RD_ADDR); - - for (patience = 0x100000; patience > 0; --patience) { - if (ioread32(port_base + LINK_CONTROL) & 0x00000001) - break; - } - if (patience == 0) - DPRINTK("link read timed out for port %d\n", ap->port_no); - - result = ioread32(port_base + LINK_DATA); - spin_unlock_irqrestore(&hd->phy_lock, flags); - - return result; -} - -static int sata_oxnas_scr_read_port(struct ata_port *ap, unsigned int sc_reg, - u32 *val) -{ - *val = sata_oxnas_link_read(ap, 0x20 + (sc_reg*4)); - return 0; -} - -static int sata_oxnas_scr_read(struct ata_link *link, - unsigned int sc_reg, u32 *val) -{ - return sata_oxnas_scr_read_port(link->ap, sc_reg, val); -} - -/** - * sata_oxnas_irq_clear is called during probe just before the interrupt handler is - * registered, to be sure hardware is quiet. It clears and masks interrupt bits - * in the SATA core. - * - * @param ap hardware with the registers in - */ -static void sata_oxnas_irq_clear(struct ata_port *ap) -{ - struct sata_oxnas_port_priv *port_priv = ap->private_data; - - /* clear pending interrupts */ - iowrite32(~0, port_priv->port_base + INT_CLEAR); - iowrite32(COREINT_END, port_priv->core_base + CORE_INT_CLEAR); -} - -/** - * qc_issue is used to make a command active, once the hardware and S/G tables - * have been prepared. IDE BMDMA drivers use the helper function - * ata_qc_issue_prot() for taskfile protocol-based dispatch. More advanced - * drivers roll their own ->qc_issue implementation, using this as the - * "issue new ATA command to hardware" hook. - * @param qc the queued command to issue - */ -static unsigned int sata_oxnas_qc_issue(struct ata_queued_cmd *qc) -{ - struct sata_oxnas_port_priv *pd = qc->ap->private_data; - struct sata_oxnas_host_priv *hd = qc->ap->host->private_data; - - void __iomem *port_base = pd->port_base; - void __iomem *core_base = pd->core_base; - int port_no = qc->ap->port_no; - int no_microcode = (hd->current_ucode == UNKNOWN_MODE); - u32 reg; - - /* check the core is idle */ - if (ioread32(port_base + SATA_COMMAND) & CMD_CORE_BUSY) { - int count = 0; - - DPRINTK("core busy for a command on port %d\n", - qc->ap->port_no); - do { - mdelay(1); - if (++count > 100) { - DPRINTK("core busy for a command on port %d\n", - qc->ap->port_no); - /* CrazyDumpDebug(); */ - sata_oxnas_cleanup(qc->ap->host); - } - } while (ioread32(port_base + SATA_COMMAND) & CMD_CORE_BUSY); - } - - /* enable passing of error signals to DMA sub-core by clearing the - * appropriate bit */ - reg = ioread32(core_base + DATA_PLANE_CTRL); - if (no_microcode) - reg |= (DPC_ERROR_MASK_BIT | (DPC_ERROR_MASK_BIT << 1)); - reg &= ~(DPC_ERROR_MASK_BIT << port_no); - iowrite32(reg, core_base + DATA_PLANE_CTRL); - - /* Disable all interrupts for ports and RAID controller */ - iowrite32(~0, port_base + INT_DISABLE); - - /* Disable all interrupts for core */ - iowrite32(~0, core_base + CORE_INT_DISABLE); - wmb(); - - /* Load the command settings into the orb registers */ - sata_oxnas_tf_load(qc->ap, &qc->tf); - - /* both pio and dma commands use dma */ - if (ata_is_dma(qc->tf.protocol) || ata_is_pio(qc->tf.protocol)) { - /* Start the DMA */ - iowrite32(SGDMA_CONTROL_GO, pd->sgdma_base + SGDMA_CONTROL); - wmb(); - } - - /* enable End of command interrupt */ - iowrite32(INT_WANT, port_base + INT_ENABLE); - iowrite32(COREINT_END, core_base + CORE_INT_ENABLE); - wmb(); - - /* Start the command */ - reg = ioread32(port_base + SATA_COMMAND); - reg &= ~SATA_OPCODE_MASK; - reg |= CMD_WRITE_TO_ORB_REGS; - iowrite32(reg , port_base + SATA_COMMAND); - wmb(); - - return 0; -} - -/** - * Will schedule the libATA error handler on the premise that there has - * been a hotplug event on the port specified - */ -void sata_oxnas_checkforhotplug(struct ata_port *ap) -{ - DPRINTK("ENTER\n"); - - ata_ehi_hotplugged(&ap->link.eh_info); - ata_port_freeze(ap); -} - - -/**************************************************************************/ -/* Locking */ -/**************************************************************************/ -/** - * The underlying function that controls access to the sata core - * - * @return non-zero indicates that you have acquired exclusive access to the - * sata core. - */ -static int __acquire_sata_core( - struct ata_host *ah, - int port_no, - oxnas_sata_isr_callback_t callback, - void *arg, - int may_sleep, - int timeout_jiffies, - int hw_access, - void *uid, - int locker_type) -{ - unsigned long end = jiffies + timeout_jiffies; - int acquired = 0; - unsigned long flags; - int timed_out = 0; - struct sata_oxnas_host_priv *hd; - - DEFINE_WAIT(wait); - - if (!ah) - return acquired; - - hd = ah->private_data; - - spin_lock_irqsave(&hd->core_lock, flags); - - DPRINTK("Entered uid %p, port %d, h/w count %d, d count %d, " - "callback %p, hw_access %d, core_locked %d, " - "reentrant_port_no %d, isr_callback %p\n", - uid, port_no, hd->hw_lock_count, hd->direct_lock_count, - callback, hw_access, hd->core_locked, hd->reentrant_port_no, - hd->isr_callback); - - while (!timed_out) { - if (hd->core_locked || - (!hw_access && hd->scsi_nonblocking_attempts)) { - /* Can only allow access if from SCSI/SATA stack and if - * reentrant access is allowed and this access is to the - * same port for which the lock is current held - */ - if (hw_access && (port_no == hd->reentrant_port_no)) { - BUG_ON(!hd->hw_lock_count); - ++(hd->hw_lock_count); - - DPRINTK("Allow SCSI/SATA re-entrant access to " - "uid %p port %d\n", uid, port_no); - acquired = 1; - break; - } else if (!hw_access) { - if ((locker_type == SATA_READER) && - (hd->current_locker_type == SATA_READER)) { - WARN(1, - "Already locked by reader, " - "uid %p, locker_uid %p, " - "port %d, h/w count %d, " - "d count %d, hw_access %d\n", - uid, hd->locker_uid, port_no, - hd->hw_lock_count, - hd->direct_lock_count, - hw_access); - goto check_uid; - } - - if ((locker_type != SATA_READER) && - (locker_type != SATA_WRITER)) { - goto wait_for_lock; - } - -check_uid: - WARN(uid == hd->locker_uid, "Attempt to lock " - "by locker type %d uid %p, already " - "locked by locker type %d with " - "locker_uid %p, port %d, " - "h/w count %d, d count %d, " - "hw_access %d\n", locker_type, uid, - hd->current_locker_type, - hd->locker_uid, port_no, - hd->hw_lock_count, - hd->direct_lock_count, hw_access); - } - } else { - WARN(hd->hw_lock_count || hd->direct_lock_count, - "Core unlocked but counts non-zero: uid %p, " - "locker_uid %p, port %d, h/w count %d, " - "d count %d, hw_access %d\n", uid, - hd->locker_uid, port_no, hd->hw_lock_count, - hd->direct_lock_count, hw_access); - - BUG_ON(hd->current_locker_type != SATA_UNLOCKED); - - WARN(hd->locker_uid, "Attempt to lock uid %p when " - "locker_uid %p is non-zero, port %d, " - "h/w count %d, d count %d, hw_access %d\n", - uid, hd->locker_uid, port_no, hd->hw_lock_count, - hd->direct_lock_count, hw_access); - - if (!hw_access) { - /* Direct access attempting to acquire - * non-contented lock - */ - /* Must have callback for direct access */ - BUG_ON(!callback); - /* Sanity check lock state */ - BUG_ON(hd->reentrant_port_no != -1); - - hd->isr_callback = callback; - hd->isr_arg = arg; - ++(hd->direct_lock_count); - - hd->current_locker_type = locker_type; - } else { - /* SCSI/SATA attempting to acquire - * non-contented lock - */ - /* No callbacks for SCSI/SATA access */ - BUG_ON(callback); - /* No callback args for SCSI/SATA access */ - BUG_ON(arg); - - /* Sanity check lock state */ - BUG_ON(hd->isr_callback); - BUG_ON(hd->isr_arg); - - ++(hd->hw_lock_count); - hd->reentrant_port_no = port_no; - - hd->current_locker_type = SATA_SCSI_STACK; - } - - hd->core_locked = 1; - hd->locker_uid = uid; - acquired = 1; - break; - } - -wait_for_lock: - if (!may_sleep) { - DPRINTK("Denying for uid %p locker_type %d, " - "hw_access %d, port %d, current_locker_type %d as " - "cannot sleep\n", uid, locker_type, hw_access, port_no, - hd->current_locker_type); - - if (hw_access) - ++(hd->scsi_nonblocking_attempts); - - break; - } - - /* Core is locked and we're allowed to sleep, so wait to be - * awoken when the core is unlocked - */ - for (;;) { - prepare_to_wait(hw_access ? &hd->scsi_wait_queue : - &hd->fast_wait_queue, - &wait, TASK_UNINTERRUPTIBLE); - if (!hd->core_locked && - !(!hw_access && hd->scsi_nonblocking_attempts)) { - /* We're going to use variables that will have - * been changed by the waker prior to clearing - * core_locked so we need to ensure we see - * changes to all those variables - */ - smp_rmb(); - break; - } - if (time_after(jiffies, end)) { - printk(KERN_WARNING "__acquire_sata_core() " - "uid %p failing for port %d timed out, " - "locker_uid %p, h/w count %d, " - "d count %d, callback %p, hw_access %d, " - "core_locked %d, reentrant_port_no %d, " - "isr_callback %p, isr_arg %p\n", uid, - port_no, hd->locker_uid, - hd->hw_lock_count, - hd->direct_lock_count, callback, - hw_access, hd->core_locked, - hd->reentrant_port_no, hd->isr_callback, - hd->isr_arg); - timed_out = 1; - break; - } - spin_unlock_irqrestore(&hd->core_lock, flags); - if (!schedule_timeout(4*HZ)) { - printk(KERN_INFO "__acquire_sata_core() uid %p, " - "locker_uid %p, timed-out of " - "schedule(), checking overall timeout\n", - uid, hd->locker_uid); - } - spin_lock_irqsave(&hd->core_lock, flags); - } - finish_wait(hw_access ? &hd->scsi_wait_queue : - &hd->fast_wait_queue, &wait); - } - - if (hw_access && acquired) { - if (hd->scsi_nonblocking_attempts) - hd->scsi_nonblocking_attempts = 0; - - /* Wake any other SCSI/SATA waiters so they can get reentrant - * access to the same port if appropriate. This is because if - * the SATA core is locked by fast access, or SCSI/SATA access - * to other port, then can have >1 SCSI/SATA waiters on the wait - * list so want to give reentrant accessors a chance to get - * access ASAP - */ - if (!list_empty(&hd->scsi_wait_queue.task_list)) - wake_up(&hd->scsi_wait_queue); - } - - DPRINTK("Leaving uid %p with acquired = %d, port %d, callback %p\n", - uid, acquired, port_no, callback); - - spin_unlock_irqrestore(&hd->core_lock, flags); - - return acquired; -} - -int sata_core_has_fast_waiters(struct ata_host *ah) -{ - int has_waiters; - unsigned long flags; - struct sata_oxnas_host_priv *hd = ah->private_data; - - spin_lock_irqsave(&hd->core_lock, flags); - has_waiters = !list_empty(&hd->fast_wait_queue.task_list); - spin_unlock_irqrestore(&hd->core_lock, flags); - - return has_waiters; -} -EXPORT_SYMBOL(sata_core_has_fast_waiters); - -int sata_core_has_scsi_waiters(struct ata_host *ah) -{ - int has_waiters; - unsigned long flags; - struct sata_oxnas_host_priv *hd = ah->private_data; - - spin_lock_irqsave(&hd->core_lock, flags); - has_waiters = hd->scsi_nonblocking_attempts || - !list_empty(&hd->scsi_wait_queue.task_list); - spin_unlock_irqrestore(&hd->core_lock, flags); - - return has_waiters; -} -EXPORT_SYMBOL(sata_core_has_scsi_waiters); - -/* - * ata_port operation to gain ownership of the SATA hardware prior to issuing - * a command against a SATA host. Allows any number of users of the port against - * which the lock was first acquired, thus enforcing that only one SATA core - * port may be operated on at once. - */ -static int sata_oxnas_acquire_hw( - struct ata_port *ap, - int may_sleep, - int timeout_jiffies) -{ - return __acquire_sata_core(ap->host, ap->port_no, NULL, 0, may_sleep, - timeout_jiffies, 1, (void *)HW_LOCKER_UID, - SATA_SCSI_STACK); -} - -/* - * operation to release ownership of the SATA hardware - */ -static void sata_oxnas_release_hw(struct ata_port *ap) -{ - unsigned long flags; - int released = 0; - struct sata_oxnas_host_priv *hd = ap->host->private_data; - - spin_lock_irqsave(&hd->core_lock, flags); - - DPRINTK("Entered port_no = %d, h/w count %d, d count %d, " - "core locked = %d, reentrant_port_no = %d, isr_callback %p\n", - ap->port_no, hd->hw_lock_count, hd->direct_lock_count, - hd->core_locked, hd->reentrant_port_no, hd->isr_callback); - - if (!hd->core_locked) { - /* Nobody holds the SATA lock */ - printk(KERN_WARNING "Nobody holds SATA lock, port_no %d\n", - ap->port_no); - released = 1; - } else if (!hd->hw_lock_count) { - /* SCSI/SATA has released without holding the lock */ - printk(KERN_WARNING "SCSI/SATA does not hold SATA lock, " - "port_no %d\n", ap->port_no); - } else { - /* Trap incorrect usage */ - BUG_ON(hd->reentrant_port_no == -1); - BUG_ON(ap->port_no != hd->reentrant_port_no); - BUG_ON(hd->direct_lock_count); - BUG_ON(hd->current_locker_type != SATA_SCSI_STACK); - - WARN(!hd->locker_uid || (hd->locker_uid != HW_LOCKER_UID), - "Invalid locker uid %p, h/w count %d, d count %d, " - "reentrant_port_no %d, core_locked %d, " - "isr_callback %p\n", hd->locker_uid, hd->hw_lock_count, - hd->direct_lock_count, hd->reentrant_port_no, - hd->core_locked, hd->isr_callback); - - if (--(hd->hw_lock_count)) { - DPRINTK("Still nested port_no %d\n", ap->port_no); - } else { - DPRINTK("Release port_no %d\n", ap->port_no); - hd->reentrant_port_no = -1; - hd->isr_callback = NULL; - hd->current_locker_type = SATA_UNLOCKED; - hd->locker_uid = 0; - hd->core_locked = 0; - released = 1; - wake_up(!list_empty(&hd->scsi_wait_queue.task_list) ? - &hd->scsi_wait_queue : - &hd->fast_wait_queue); - } - } - - DPRINTK("Leaving, port_no %d, count %d\n", ap->port_no, - hd->hw_lock_count); - - spin_unlock_irqrestore(&hd->core_lock, flags); - - /* CONFIG_SATA_OX820_DIRECT_HWRAID */ - /* if (released) - ox820hwraid_restart_queue(); - } */ -} - -static inline int sata_oxnas_is_host_frozen(struct ata_host *ah) -{ - struct sata_oxnas_host_priv *hd = ah->private_data; - - smp_rmb(); - return hd->port_in_eh || hd->port_frozen; -} - - -static inline u32 sata_oxnas_hostportbusy(struct ata_port *ap) -{ - struct sata_oxnas_host_priv *hd = ap->host->private_data; - - return (ioread32(hd->port_base + SATA_COMMAND) & CMD_CORE_BUSY) || - (hd->n_ports > 1 && - (ioread32(hd->port_base + PORT_SIZE + SATA_COMMAND) & - CMD_CORE_BUSY)); -} - -static inline u32 sata_oxnas_hostdmabusy(struct ata_port *ap) -{ - struct sata_oxnas_port_priv *pd = ap->private_data; - - return ioread32(pd->sgdma_base + SGDMA_STATUS) & SGDMA_BUSY; -} - - -/** - * Turns on the cores clock and resets it - */ -static void sata_oxnas_reset_core(struct ata_host *ah) -{ - struct sata_oxnas_host_priv *host_priv = ah->private_data; - int n; - - DPRINTK("ENTER\n"); - clk_prepare_enable(host_priv->clk); - - reset_control_assert(host_priv->rst_sata); - reset_control_assert(host_priv->rst_link); - reset_control_assert(host_priv->rst_phy); - - udelay(50); - - /* un-reset the PHY, then Link and Controller */ - reset_control_deassert(host_priv->rst_phy); - udelay(50); - - reset_control_deassert(host_priv->rst_sata); - reset_control_deassert(host_priv->rst_link); - udelay(50); - - workaround5458(ah); - /* tune for sata compatibility */ - sata_oxnas_link_write(ah->ports[0], 0x60, 0x2988); - - for (n = 0; n < host_priv->n_ports; n++) { - /* each port in turn */ - sata_oxnas_link_write(ah->ports[n], 0x70, 0x55629); - } - udelay(50); -} - - -/** - * Called after an identify device command has worked out what kind of device - * is on the port - * - * @param port The port to configure - * @param pdev The hardware associated with controlling the port - */ -static void sata_oxnas_dev_config(struct ata_device *pdev) -{ - struct sata_oxnas_port_priv *pd = pdev->link->ap->private_data; - void __iomem *port_base = pd->port_base; - u32 reg; - - DPRINTK("ENTER\n"); - /* Set the bits to put the port into 28 or 48-bit node */ - reg = ioread32(port_base + DRIVE_CONTROL); - reg &= ~3; - reg |= (pdev->flags & ATA_DFLAG_LBA48) ? DR_CON_48 : DR_CON_28; - iowrite32(reg, port_base + DRIVE_CONTROL); - - /* if this is an ATA-6 disk, put port into ATA-5 auto translate mode */ - if (pdev->flags & ATA_DFLAG_LBA48) { - reg = ioread32(port_base + PORT_CONTROL); - reg |= 2; - iowrite32(reg, port_base + PORT_CONTROL); - } -} -/** - * called to write a taskfile into the ORB registers - * @param ap hardware with the registers in - * @param tf taskfile to write to the registers - */ -static void sata_oxnas_tf_load(struct ata_port *ap, - const struct ata_taskfile *tf) -{ - u32 count = 0; - u32 Orb1 = 0; - u32 Orb2 = 0; - u32 Orb3 = 0; - u32 Orb4 = 0; - u32 Command_Reg; - - struct sata_oxnas_port_priv *port_priv = ap->private_data; - void __iomem *port_base = port_priv->port_base; - unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; - - /* wait a maximum of 10ms for the core to be idle */ - do { - Command_Reg = ioread32(port_base + SATA_COMMAND); - if (!(Command_Reg & CMD_CORE_BUSY)) - break; - count++; - udelay(50); - } while (count < 200); - - /* check if the ctl register has interrupts disabled or enabled and - * modify the interrupt enable registers on the ata core as required */ - if (tf->ctl & ATA_NIEN) { - /* interrupts disabled */ - u32 mask = (COREINT_END << ap->port_no); - - iowrite32(mask, port_priv->core_base + CORE_INT_DISABLE); - sata_oxnas_irq_clear(ap); - } else { - sata_oxnas_irq_on(ap); - } - - Orb2 |= (tf->command) << 24; - - /* write 48 or 28 bit tf parameters */ - if (is_addr) { - /* set LBA bit as it's an address */ - Orb1 |= (tf->device & ATA_LBA) << 24; - - if (tf->flags & ATA_TFLAG_LBA48) { - Orb1 |= ATA_LBA << 24; - Orb2 |= (tf->hob_nsect) << 8; - Orb3 |= (tf->hob_lbal) << 24; - Orb4 |= (tf->hob_lbam) << 0; - Orb4 |= (tf->hob_lbah) << 8; - Orb4 |= (tf->hob_feature) << 16; - } else { - Orb3 |= (tf->device & 0xf) << 24; - } - - /* write 28-bit lba */ - Orb2 |= (tf->nsect) << 0; - Orb2 |= (tf->feature) << 16; - Orb3 |= (tf->lbal) << 0; - Orb3 |= (tf->lbam) << 8; - Orb3 |= (tf->lbah) << 16; - Orb4 |= (tf->ctl) << 24; - } - - if (tf->flags & ATA_TFLAG_DEVICE) - Orb1 |= (tf->device) << 24; - - ap->last_ctl = tf->ctl; - - /* write values to registers */ - iowrite32(Orb1, port_base + ORB1); - iowrite32(Orb2, port_base + ORB2); - iowrite32(Orb3, port_base + ORB3); - iowrite32(Orb4, port_base + ORB4); -} - - -void sata_oxnas_set_mode(struct ata_host *ah, u32 mode, u32 force) -{ - struct sata_oxnas_host_priv *host_priv = ah->private_data; - void __iomem *core_base = host_priv->core_base; - - unsigned int *src; - void __iomem *dst; - unsigned int progmicrocode = 0; - unsigned int changeparameters = 0; - - u32 previous_mode; - - /* these micro-code programs _should_ include the version word */ - - /* JBOD */ - static const unsigned int jbod[] = { - 0x07B400AC, 0x0228A280, 0x00200001, 0x00204002, 0x00224001, - 0x00EE0009, 0x00724901, 0x01A24903, 0x00E40009, 0x00224001, - 0x00621120, 0x0183C908, 0x00E20005, 0x00718908, 0x0198A206, - 0x00621124, 0x0183C908, 0x00E20046, 0x00621104, 0x0183C908, - 0x00E20015, 0x00EE009D, 0x01A3E301, 0x00E2001B, 0x0183C900, - 0x00E2001B, 0x00210001, 0x00EE0020, 0x01A3E302, 0x00E2009D, - 0x0183C901, 0x00E2009D, 0x00210002, 0x0235D700, 0x0208A204, - 0x0071C908, 0x000F8207, 0x000FC207, 0x0071C920, 0x000F8507, - 0x000FC507, 0x0228A240, 0x02269A40, 0x00094004, 0x00621104, - 0x0180C908, 0x00E40031, 0x00621112, 0x01A3C801, 0x00E2002B, - 0x00294000, 0x0228A220, 0x01A69ABF, 0x002F8000, 0x002FC000, - 0x0198A204, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007, - 0x0183C903, 0x00E2009D, 0x0228A220, 0x0071890C, 0x0208A206, - 0x0198A206, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007, - 0x00EE009D, 0x00621104, 0x0183C908, 0x00E2004A, 0x00EE009D, - 0x01A3C901, 0x00E20050, 0x0021E7FF, 0x0183E007, 0x00E2009D, - 0x00EE0054, 0x0061600B, 0x0021E7FF, 0x0183C507, 0x00E2009D, - 0x01A3E301, 0x00E2005A, 0x0183C900, 0x00E2005A, 0x00210001, - 0x00EE005F, 0x01A3E302, 0x00E20005, 0x0183C901, 0x00E20005, - 0x00210002, 0x0235D700, 0x0208A204, 0x000F8109, 0x000FC109, - 0x0071C918, 0x000F8407, 0x000FC407, 0x0001C022, 0x01A1A2BF, - 0x0001C106, 0x00088007, 0x02269A40, 0x00094004, 0x00621112, - 0x01A3C801, 0x00E4007F, 0x00621104, 0x0180C908, 0x00E4008D, - 0x00621128, 0x0183C908, 0x00E2006C, 0x01A3C901, 0x00E2007B, - 0x0021E7FF, 0x0183E007, 0x00E2007F, 0x00EE006C, 0x0061600B, - 0x0021E7FF, 0x0183C507, 0x00E4006C, 0x00621111, 0x01A3C801, - 0x00E2007F, 0x00621110, 0x01A3C801, 0x00E20082, 0x0228A220, - 0x00621119, 0x01A3C801, 0x00E20086, 0x0001C022, 0x01B1A220, - 0x0001C106, 0x00088007, 0x0198A204, 0x00294000, 0x01A69ABF, - 0x002F8000, 0x002FC000, 0x0183C903, 0x00E20005, 0x0228A220, - 0x0071890C, 0x0208A206, 0x0198A206, 0x0001C022, 0x01B1A220, - 0x0001C106, 0x00088007, 0x00EE009D, 0x00621128, 0x0183C908, - 0x00E20005, 0x00621104, 0x0183C908, 0x00E200A6, 0x0062111C, - 0x0183C908, 0x00E20005, 0x0071890C, 0x0208A206, 0x0198A206, - 0x00718908, 0x0208A206, 0x00EE0005, ~0 - }; - - /* Bi-Modal RAID-0/1 */ - static const unsigned int raid[] = { - 0x00F20145, 0x00EE20FA, 0x00EE20A7, 0x0001C009, 0x00EE0004, - 0x00220000, 0x0001000B, 0x037003FF, 0x00700018, 0x037003FE, - 0x037043FD, 0x00704118, 0x037043FC, 0x01A3D240, 0x00E20017, - 0x00B3C235, 0x00E40018, 0x0093C104, 0x00E80014, 0x0093C004, - 0x00E80017, 0x01020000, 0x00274020, 0x00EE0083, 0x0080C904, - 0x0093C104, 0x00EA0020, 0x0093C103, 0x00EC001F, 0x00220002, - 0x00924104, 0x0005C009, 0x00EE0058, 0x0093CF04, 0x00E80026, - 0x00900F01, 0x00600001, 0x00910400, 0x00EE0058, 0x00601604, - 0x01A00003, 0x00E2002C, 0x01018000, 0x00274040, 0x00EE0083, - 0x0093CF03, 0x00EC0031, 0x00220003, 0x00924F04, 0x0005C009, - 0x00810104, 0x00B3C235, 0x00E20037, 0x0022C000, 0x00218210, - 0x00EE0039, 0x0022C001, 0x00218200, 0x00600401, 0x00A04901, - 0x00604101, 0x01A0C401, 0x00E20040, 0x00216202, 0x00EE0041, - 0x00216101, 0x02018506, 0x00EE2141, 0x00904901, 0x00E20049, - 0x00A00401, 0x00600001, 0x02E0C301, 0x00EE2141, 0x00216303, - 0x037003EE, 0x01A3C001, 0x00E40105, 0x00250080, 0x00204000, - 0x002042F1, 0x0004C001, 0x00230001, 0x00100006, 0x02C18605, - 0x00100006, 0x01A3D502, 0x00E20055, 0x00EE0053, 0x00004009, - 0x00000004, 0x00B3C235, 0x00E40062, 0x0022C001, 0x0020C000, - 0x00EE2141, 0x0020C001, 0x00EE2141, 0x00EE006B, 0x0022C000, - 0x0060D207, 0x00EE2141, 0x00B3C242, 0x00E20069, 0x01A3D601, - 0x00E2006E, 0x02E0C301, 0x00EE2141, 0x00230001, 0x00301303, - 0x00EE007B, 0x00218210, 0x01A3C301, 0x00E20073, 0x00216202, - 0x00EE0074, 0x00216101, 0x02018506, 0x00214000, 0x037003EE, - 0x01A3C001, 0x00E40108, 0x00230001, 0x00100006, 0x00250080, - 0x00204000, 0x002042F1, 0x0004C001, 0x00EE007F, 0x0024C000, - 0x01A3D1F0, 0x00E20088, 0x00230001, 0x00300000, 0x01A3D202, - 0x00E20085, 0x00EE00A5, 0x00B3C800, 0x00E20096, 0x00218000, - 0x00924709, 0x0005C009, 0x00B20802, 0x00E40093, 0x037103FD, - 0x00710418, 0x037103FC, 0x00EE0006, 0x00220000, 0x0001000F, - 0x00EE0006, 0x00800B0C, 0x00B00001, 0x00204000, 0x00208550, - 0x00208440, 0x002083E0, 0x00208200, 0x00208100, 0x01008000, - 0x037083EE, 0x02008212, 0x02008216, 0x01A3C201, 0x00E400A5, - 0x0100C000, 0x00EE20FA, 0x02800000, 0x00208000, 0x00B24C00, - 0x00E400AD, 0x00224001, 0x00724910, 0x0005C009, 0x00B3CDC4, - 0x00E200D5, 0x00B3CD29, 0x00E200D5, 0x00B3CD20, 0x00E200D5, - 0x00B3CD24, 0x00E200D5, 0x00B3CDC5, 0x00E200D2, 0x00B3CD39, - 0x00E200D2, 0x00B3CD30, 0x00E200D2, 0x00B3CD34, 0x00E200D2, - 0x00B3CDCA, 0x00E200CF, 0x00B3CD35, 0x00E200CF, 0x00B3CDC8, - 0x00E200CC, 0x00B3CD25, 0x00E200CC, 0x00B3CD40, 0x00E200CB, - 0x00B3CD42, 0x00E200CB, 0x01018000, 0x00EE0083, 0x0025C000, - 0x036083EE, 0x0000800D, 0x00EE00D8, 0x036083EE, 0x00208035, - 0x00EE00DA, 0x036083EE, 0x00208035, 0x00EE00DA, 0x00208007, - 0x036083EE, 0x00208025, 0x036083EF, 0x02400000, 0x01A3D208, - 0x00E200D8, 0x0067120A, 0x0021C000, 0x0021C224, 0x00220000, - 0x00404B1C, 0x00600105, 0x00800007, 0x0020C00E, 0x00214000, - 0x01004000, 0x01A0411F, 0x00404E01, 0x01A3C101, 0x00E200F1, - 0x00B20800, 0x00E400D8, 0x00220001, 0x0080490B, 0x00B04101, - 0x0040411C, 0x00EE00E1, 0x02269A01, 0x01020000, 0x02275D80, - 0x01A3D202, 0x00E200F4, 0x01B75D80, 0x01030000, 0x01B69A01, - 0x00EE00D8, 0x01A3D204, 0x00E40104, 0x00224000, 0x0020C00E, - 0x0020001E, 0x00214000, 0x01004000, 0x0212490E, 0x00214001, - 0x01004000, 0x02400000, 0x00B3D702, 0x00E80112, 0x00EE010E, - 0x00B3D702, 0x00E80112, 0x00B3D702, 0x00E4010E, 0x00230001, - 0x00EE0140, 0x00200005, 0x036003EE, 0x00204001, 0x00EE0116, - 0x00230001, 0x00100006, 0x02C18605, 0x00100006, 0x01A3D1F0, - 0x00E40083, 0x037003EE, 0x01A3C002, 0x00E20121, 0x0020A300, - 0x0183D102, 0x00E20124, 0x037003EE, 0x01A00005, 0x036003EE, - 0x01A0910F, 0x00B3C20F, 0x00E2012F, 0x01A3D502, 0x00E20116, - 0x01A3C002, 0x00E20116, 0x00B3D702, 0x00E4012C, 0x00300000, - 0x00EE011F, 0x02C18605, 0x00100006, 0x00EE0116, 0x01A3D1F0, - 0x00E40083, 0x037003EE, 0x01A3C004, 0x00E20088, 0x00200003, - 0x036003EE, 0x01A3D502, 0x00E20136, 0x00230001, 0x00B3C101, - 0x00E4012C, 0x00100006, 0x02C18605, 0x00100006, 0x00204000, - 0x00EE0116, 0x00100006, 0x01A3D1F0, 0x00E40083, 0x01000000, - 0x02400000, ~0 - }; - - DPRINTK("ENTER: mode:%d, force:%d\n", mode, force); - - if (force) - previous_mode = UNKNOWN_MODE; - else - previous_mode = host_priv->current_ucode; - - if (mode == previous_mode) - return; - - host_priv->current_ucode = mode; - - /* decide what needs to be done using the STD in my logbook */ - switch (previous_mode) { - case OXNASSATA_RAID1: - switch (mode) { - case OXNASSATA_RAID0: - changeparameters = 1; - break; - case OXNASSATA_NOTRAID: - changeparameters = 1; - progmicrocode = 1; - break; - } - break; - case OXNASSATA_RAID0: - switch (mode) { - case OXNASSATA_RAID1: - changeparameters = 1; - break; - case OXNASSATA_NOTRAID: - changeparameters = 1; - progmicrocode = 1; - break; - } - break; - case OXNASSATA_NOTRAID: - switch (mode) { - case OXNASSATA_RAID0: - case OXNASSATA_RAID1: - changeparameters = 1; - progmicrocode = 1; - break; - } - break; - case UNKNOWN_MODE: - changeparameters = 1; - progmicrocode = 1; - break; - } - - /* no need to reprogram everything if already in the right mode */ - if (progmicrocode) { - /* reset micro-code processor */ - iowrite32(1, core_base + PROC_RESET); - wmb(); - - /* select micro-code */ - switch (mode) { - case OXNASSATA_RAID1: - case OXNASSATA_RAID0: - VPRINTK("Loading RAID micro-code\n"); - src = (unsigned int *)&raid[1]; - break; - case OXNASSATA_NOTRAID: - VPRINTK("Loading JBOD micro-code\n"); - src = (unsigned int *)&jbod[1]; - break; - default: - BUG(); - break; - } - - /* load micro code */ - dst = core_base + UCODE_STORE; - while (*src != ~0) { - iowrite32(*src, dst); - src++; - dst += sizeof(*src); - } - wmb(); - } - - if (changeparameters) { - u32 reg; - /* set other mode dependent flags */ - switch (mode) { - case OXNASSATA_RAID1: - /* clear JBOD mode */ - reg = ioread32(core_base + DATA_PLANE_CTRL); - reg |= DPC_JBOD_UCODE; - reg &= ~DPC_FIS_SWCH; - iowrite32(reg, core_base + DATA_PLANE_CTRL); - wmb(); - - /* set the hardware up for RAID-1 */ - iowrite32(0, core_base + RAID_WP_BOT_LOW); - iowrite32(0, core_base + RAID_WP_BOT_HIGH); - iowrite32(0xffffffff, core_base + RAID_WP_TOP_LOW); - iowrite32(0x7fffffff, core_base + RAID_WP_TOP_HIGH); - iowrite32(0, core_base + RAID_SIZE_LOW); - iowrite32(0, core_base + RAID_SIZE_HIGH); - wmb(); - break; - case OXNASSATA_RAID0: - /* clear JBOD mode */ - reg = ioread32(core_base + DATA_PLANE_CTRL); - reg |= DPC_JBOD_UCODE; - reg &= ~DPC_FIS_SWCH; - iowrite32(reg, core_base + DATA_PLANE_CTRL); - wmb(); - - /* set the hardware up for RAID-1 */ - iowrite32(0, core_base + RAID_WP_BOT_LOW); - iowrite32(0, core_base + RAID_WP_BOT_HIGH); - iowrite32(0xffffffff, core_base + RAID_WP_TOP_LOW); - iowrite32(0x7fffffff, core_base + RAID_WP_TOP_HIGH); - iowrite32(0xffffffff, core_base + RAID_SIZE_LOW); - iowrite32(0x7fffffff, core_base + RAID_SIZE_HIGH); - wmb(); - break; - case OXNASSATA_NOTRAID: - /* enable jbod mode */ - reg = ioread32(core_base + DATA_PLANE_CTRL); - reg &= ~DPC_JBOD_UCODE; - reg &= ~DPC_FIS_SWCH; - iowrite32(reg, core_base + DATA_PLANE_CTRL); - wmb(); - - /* start micro-code processor*/ - iowrite32(1, core_base + PROC_START); - break; - default: - reg = ioread32(core_base + DATA_PLANE_CTRL); - reg |= DPC_JBOD_UCODE; - reg &= ~DPC_FIS_SWCH; - iowrite32(reg, core_base + DATA_PLANE_CTRL); - wmb(); - break; - } - } -} - -/** - * sends a sync-escape if there is a link present - */ -static inline void sata_oxnas_send_sync_escape(struct ata_port *ap) -{ - struct sata_oxnas_port_priv *pd = ap->private_data; - u32 reg; - - /* read the SSTATUS register and only send a sync escape if there is a - * link active */ - if ((sata_oxnas_link_read(ap, 0x20) & 3) == 3) { - reg = ioread32(pd->port_base + SATA_COMMAND); - reg &= ~SATA_OPCODE_MASK; - reg |= CMD_SYNC_ESCAPE; - iowrite32(reg, pd->port_base + SATA_COMMAND); - } -} - -/* clears errors */ -static inline void sata_oxnas_clear_CS_error(struct ata_port *ap) -{ - struct sata_oxnas_port_priv *pd = ap->private_data; - u32 *base = pd->port_base; - u32 reg; - - reg = ioread32(base + SATA_CONTROL); - reg &= SATA_CTL_ERR_MASK; - iowrite32(reg, base + SATA_CONTROL); -} - -static inline void sata_oxnas_reset_sgdma(struct ata_port *ap) -{ - struct sata_oxnas_port_priv *pd = ap->private_data; - - iowrite32(SGDMA_RESETS_CTRL, pd->sgdma_base + SGDMA_RESETS); -} - -static inline void sata_oxnas_reset_dma(struct ata_port *ap, int assert) -{ - struct sata_oxnas_port_priv *pd = ap->private_data; - u32 reg; - - reg = ioread32(pd->dmactl_base + DMA_CONTROL); - if (assert) - reg |= DMA_CONTROL_RESET; - else - reg &= ~DMA_CONTROL_RESET; - - iowrite32(reg, pd->dmactl_base + DMA_CONTROL); -}; - -/** - * Clears the error caused by the core's registers being accessed when the - * core is busy. - */ -static inline void sata_oxnas_clear_reg_access_error(struct ata_port *ap) -{ - struct sata_oxnas_port_priv *pd = ap->private_data; - u32 *base = pd->port_base; - u32 reg; - - reg = ioread32(base + INT_STATUS); - - DPRINTK("ENTER\n"); - if (reg & INT_REG_ACCESS_ERR) { - DPRINTK("clearing register access error on port %d\n", - ap->port_no); - iowrite32(INT_REG_ACCESS_ERR, base + INT_STATUS); - } - reg = ioread32(base + INT_STATUS); - if (reg & INT_REG_ACCESS_ERR) - DPRINTK("register access error didn't clear\n"); -} - -static inline void sata_oxnas_clear_sctl_error(struct ata_port *ap) -{ - struct sata_oxnas_port_priv *pd = ap->private_data; - u32 *base = pd->port_base; - u32 reg; - - reg = ioread32(base + SATA_CONTROL); - reg |= SCTL_CLR_ERR; - iowrite32(reg, base + SATA_CONTROL); -} - -static inline void sata_oxnas_clear_raid_error(struct ata_host *ah) -{ - return; -}; - -/** - * Clean up all the state machines in the sata core. - * @return post cleanup action required - */ -static int sata_oxnas_cleanup(struct ata_host *ah) -{ - struct sata_oxnas_host_priv *hd = ah->private_data; - int actions_required = 0; - int n; - - printk(KERN_INFO "sata_oxnas: resetting SATA core\n"); - /* core not recovering, reset it */ - mdelay(5); - sata_oxnas_reset_core(ah); - mdelay(5); - actions_required |= OXNAS_SATA_REINIT; - /* Perform any SATA core re-initialisation after reset post reset init - * needs to be called for both ports as there's one reset for both - * ports */ - for (n = 0; n < hd->n_ports; n++) - sata_oxnas_post_reset_init(ah->ports[n]); - - - return actions_required; -} - -/** - * ata_qc_new - Request an available ATA command, for queueing - * @ap: Port associated with device @dev - * @return non zero will refuse a new command, zero will may grant on subject - * to conditions elsewhere. - * - */ -static int sata_oxnas_qc_new(struct ata_port *ap) -{ - struct sata_oxnas_host_priv *hd = ap->host->private_data; - - DPRINTK("port %d\n", ap->port_no); - smp_rmb(); - if (hd->port_frozen || hd->port_in_eh) - return 1; - else - return !sata_oxnas_acquire_hw(ap, 0, 0); -} - -/** - * releases the lock on the port the command used - */ -static void sata_oxnas_qc_free(struct ata_queued_cmd *qc) -{ - DPRINTK("\n"); - sata_oxnas_release_hw(qc->ap); -} - -static void sata_oxnas_freeze(struct ata_port *ap) -{ - struct sata_oxnas_host_priv *hd = ap->host->private_data; - - DPRINTK("\n"); - hd->port_frozen |= BIT(ap->port_no); - smp_wmb(); -} - -static void sata_oxnas_thaw(struct ata_port *ap) -{ - struct sata_oxnas_host_priv *hd = ap->host->private_data; - - DPRINTK("\n"); - hd->port_frozen &= ~BIT(ap->port_no); - smp_wmb(); -} - -void sata_oxnas_freeze_host(struct ata_port *ap) -{ - struct sata_oxnas_host_priv *hd = ap->host->private_data; - - DPRINTK("ENTER\n"); - hd->port_in_eh |= BIT(ap->port_no); - smp_wmb(); -} - -void sata_oxnas_thaw_host(struct ata_port *ap) -{ - struct sata_oxnas_host_priv *hd = ap->host->private_data; - - DPRINTK("ENTER\n"); - hd->port_in_eh &= ~BIT(ap->port_no); - smp_wmb(); -} - -static void sata_oxnas_post_internal_cmd(struct ata_queued_cmd *qc) -{ - DPRINTK("ENTER\n"); - /* If the core is busy here, make it idle */ - if (qc->flags & ATA_QCFLAG_FAILED) - sata_oxnas_cleanup(qc->ap->host); -} - - -/** - * turn on the interrupts - * - * @param ap Hardware with the registers in - */ -static void sata_oxnas_irq_on(struct ata_port *ap) -{ - struct sata_oxnas_port_priv *pd = ap->private_data; - u32 mask = (COREINT_END << ap->port_no); - - /* Clear pending interrupts */ - iowrite32(~0, pd->port_base + INT_CLEAR); - iowrite32(mask, pd->core_base + CORE_INT_STATUS); - wmb(); - - /* enable End of command interrupt */ - iowrite32(INT_WANT, pd->port_base + INT_ENABLE); - iowrite32(mask, pd->core_base + CORE_INT_ENABLE); -} - - -/** @return true if the port has a cable connected */ -int sata_oxnas_check_link(struct ata_port *ap) -{ - int reg; - - sata_oxnas_scr_read_port(ap, SCR_STATUS, ®); - /* Check for the cable present indicated by SCR status bit-0 set */ - return reg & 0x1; -} - -/** - * ata_std_postreset - standard postreset callback - * @link: the target ata_link - * @classes: classes of attached devices - * - * This function is invoked after a successful reset. Note that - * the device might have been reset more than once using - * different reset methods before postreset is invoked. - * - * LOCKING: - * Kernel thread context (may sleep) - */ -static void sata_oxnas_postreset(struct ata_link *link, unsigned int *classes) -{ - struct ata_port *ap = link->ap; - struct sata_oxnas_host_priv *hd = ap->host->private_data; - - unsigned int dev; - - DPRINTK("ENTER\n"); - ata_std_postreset(link, classes); - - /* turn on phy error detection by removing the masks */ - sata_oxnas_link_write(ap->host->ports[0], 0x0c, 0x30003); - if (hd->n_ports > 1) - sata_oxnas_link_write(ap->host->ports[1], 0x0c, 0x30003); - - /* bail out if no device is present */ - if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) { - DPRINTK("EXIT, no device\n"); - return; - } - - /* go through all the devices and configure them */ - for (dev = 0; dev < ATA_MAX_DEVICES; ++dev) { - if (ap->link.device[dev].class == ATA_DEV_ATA) - sata_oxnas_dev_config(&(ap->link.device[dev])); - } - - DPRINTK("EXIT\n"); -} - -/** - * Called to read the hardware registers / DMA buffers, to - * obtain the current set of taskfile register values. - * @param ap hardware with the registers in - * @param tf taskfile to read the registers into - */ -static void sata_oxnas_tf_read(struct ata_port *ap, struct ata_taskfile *tf) -{ - struct sata_oxnas_port_priv *port_priv = ap->private_data; - void __iomem *port_base = port_priv->port_base; - /* read the orb registers */ - u32 Orb1 = ioread32(port_base + ORB1); - u32 Orb2 = ioread32(port_base + ORB2); - u32 Orb3 = ioread32(port_base + ORB3); - u32 Orb4 = ioread32(port_base + ORB4); - - /* read common 28/48 bit tf parameters */ - tf->device = (Orb1 >> 24); - tf->nsect = (Orb2 >> 0); - tf->feature = (Orb2 >> 16); - tf->command = sata_oxnas_check_status(ap); - - /* read 48 or 28 bit tf parameters */ - if (tf->flags & ATA_TFLAG_LBA48) { - tf->hob_nsect = (Orb2 >> 8); - tf->lbal = (Orb3 >> 0); - tf->lbam = (Orb3 >> 8); - tf->lbah = (Orb3 >> 16); - tf->hob_lbal = (Orb3 >> 24); - tf->hob_lbam = (Orb4 >> 0); - tf->hob_lbah = (Orb4 >> 8); - /* feature ext and control are write only */ - } else { - /* read 28-bit lba */ - tf->lbal = (Orb3 >> 0); - tf->lbam = (Orb3 >> 8); - tf->lbah = (Orb3 >> 16); - } -} - -/** - * Read a result task-file from the sata core registers. - */ -static bool sata_oxnas_qc_fill_rtf(struct ata_queued_cmd *qc) -{ - /* Read the most recently received FIS from the SATA core ORB registers - and convert to an ATA taskfile */ - sata_oxnas_tf_read(qc->ap, &qc->result_tf); - return true; -} - -/** - * Reads the Status ATA shadow register from hardware. - * - * @return The status register - */ -static u8 sata_oxnas_check_status(struct ata_port *ap) -{ - u32 Reg; - u8 status; - struct sata_oxnas_port_priv *port_priv = ap->private_data; - void __iomem *port_base = port_priv->port_base; - - /* read byte 3 of Orb2 register */ - status = ioread32(port_base + ORB2) >> 24; - - /* check for the drive going missing indicated by SCR status bits - * 0-3 = 0 */ - sata_oxnas_scr_read_port(ap, SCR_STATUS, &Reg); - - if (!(Reg & 0x1)) { - status |= ATA_DF; - status |= ATA_ERR; - } - - return status; -} - -static inline void sata_oxnas_reset_ucode(struct ata_host *ah, int force, - int no_microcode) -{ - struct sata_oxnas_host_priv *hd = ah->private_data; - - DPRINTK("ENTER\n"); - if (no_microcode) { - u32 reg; - - sata_oxnas_set_mode(ah, UNKNOWN_MODE, force); - reg = ioread32(hd->core_base + DEVICE_CONTROL); - reg |= DEVICE_CONTROL_ATA_ERR_OVERRIDE; - iowrite32(reg, hd->core_base + DEVICE_CONTROL); - } else { - /* JBOD uCode */ - sata_oxnas_set_mode(ah, OXNASSATA_NOTRAID, force); - /* Turn the work around off as it may have been left on by any - * HW-RAID code that we've been working with */ - iowrite32(0x0, hd->core_base + PORT_ERROR_MASK); - } -} - -/** - * Prepare as much as possible for a command without involving anything that is - * shared between ports. - */ -static void sata_oxnas_qc_prep(struct ata_queued_cmd *qc) -{ - struct sata_oxnas_port_priv *pd; - int port_no = qc->ap->port_no; - - /* if the port's not connected, complete now with an error */ - if (!sata_oxnas_check_link(qc->ap)) { - ata_port_err(qc->ap, - "port %d not connected completing with error\n", - port_no); - qc->err_mask |= AC_ERR_ATA_BUS; - ata_qc_complete(qc); - } - - sata_oxnas_reset_ucode(qc->ap->host, 0, 0); - - /* both pio and dma commands use dma */ - if (ata_is_dma(qc->tf.protocol) || ata_is_pio(qc->tf.protocol)) { - - /* program the scatterlist into the prd table */ - ata_bmdma_qc_prep(qc); - - /* point the sgdma controller at the dma request structure */ - pd = qc->ap->private_data; - - iowrite32(pd->sgdma_request_pa, - pd->sgdma_base + SGDMA_REQUESTPTR); - - /* setup the request table */ - if (port_no == 0) { - pd->sgdma_request->control = - (qc->dma_dir == DMA_FROM_DEVICE) ? - SGDMA_REQCTL0IN : SGDMA_REQCTL0OUT; - } else { - pd->sgdma_request->control = - (qc->dma_dir == DMA_FROM_DEVICE) ? - SGDMA_REQCTL1IN : SGDMA_REQCTL1OUT; - } - pd->sgdma_request->qualifier = SGDMA_REQQUAL; - pd->sgdma_request->src_pa = qc->ap->bmdma_prd_dma; - pd->sgdma_request->dst_pa = qc->ap->bmdma_prd_dma; - smp_wmb(); - - /* tell it to wait */ - iowrite32(SGDMA_CONTROL_NOGO, pd->sgdma_base + SGDMA_CONTROL); - } -} - -static int sata_oxnas_port_start(struct ata_port *ap) -{ - struct sata_oxnas_host_priv *host_priv = ap->host->private_data; - struct device *dev = ap->host->dev; - struct sata_oxnas_port_priv *pp; - void *mem; - dma_addr_t mem_dma; - - DPRINTK("ENTER\n"); - - pp = kzalloc(sizeof(*pp), GFP_KERNEL); - if (!pp) - return -ENOMEM; - - pp->port_base = host_priv->port_base + - (ap->port_no ? PORT_SIZE : 0); - pp->dmactl_base = host_priv->dmactl_base + - (ap->port_no ? DMA_CORESIZE : 0); - pp->sgdma_base = host_priv->sgdma_base + - (ap->port_no ? SGDMA_CORESIZE : 0); - pp->core_base = host_priv->core_base; - - /* preallocated */ - if (host_priv->dma_size >= SATA_OXNAS_DMA_SIZE * host_priv->n_ports) { - DPRINTK("using preallocated DMA\n"); - mem_dma = host_priv->dma_base + - (ap->port_no ? SATA_OXNAS_DMA_SIZE : 0); - mem = ioremap(mem_dma, SATA_OXNAS_DMA_SIZE); - } else { - mem = dma_alloc_coherent(dev, SATA_OXNAS_DMA_SIZE, &mem_dma, - GFP_KERNEL); - } - if (!mem) - goto err_ret; - - pp->sgdma_request_pa = mem_dma; - pp->sgdma_request = mem; - - ap->bmdma_prd_dma = mem_dma + sizeof(struct sgdma_request); - ap->bmdma_prd = mem + sizeof(struct sgdma_request); - - ap->private_data = pp; - - sata_oxnas_post_reset_init(ap); - - return 0; - -err_ret: - kfree(pp); - return -ENOMEM; - -} - -static void sata_oxnas_port_stop(struct ata_port *ap) -{ - struct device *dev = ap->host->dev; - struct sata_oxnas_port_priv *pp = ap->private_data; - struct sata_oxnas_host_priv *host_priv = ap->host->private_data; - - DPRINTK("ENTER\n"); - ap->private_data = NULL; - if (host_priv->dma_size) { - iounmap(pp->sgdma_request); - } else { - dma_free_coherent(dev, SATA_OXNAS_DMA_SIZE, - pp->sgdma_request, pp->sgdma_request_pa); - } - - kfree(pp); -} - - -static void sata_oxnas_post_reset_init(struct ata_port *ap) -{ - uint dev; - - /* force to load u-code only once after reset */ - sata_oxnas_reset_ucode(ap->host, !ap->port_no, 0); - - /* turn on phy error detection by removing the masks */ - sata_oxnas_link_write(ap, 0x0C, 0x30003); - - /* enable hotplug event detection */ - sata_oxnas_scr_write_port(ap, SCR_ERROR, ~0); - sata_oxnas_scr_write_port(ap, SERROR_IRQ_MASK, 0x03feffff); - sata_oxnas_scr_write_port(ap, SCR_ACTIVE, ~0 & ~(1 << 26) & ~(1 << 16)); - - /* enable interrupts for ports */ - sata_oxnas_irq_on(ap); - - /* go through all the devices and configure them */ - for (dev = 0; dev < ATA_MAX_DEVICES; ++dev) { - if (ap->link.device[dev].class == ATA_DEV_ATA) { - sata_std_hardreset(&ap->link, NULL, jiffies + HZ); - sata_oxnas_dev_config(&(ap->link.device[dev])); - } - } - - /* clean up any remaining errors */ - sata_oxnas_scr_write_port(ap, SCR_ERROR, ~0); - VPRINTK("done\n"); -} - -/** - * host_stop() is called when the rmmod or hot unplug process begins. The - * hook must stop all hardware interrupts, DMA engines, etc. - * - * @param ap hardware with the registers in - */ -static void sata_oxnas_host_stop(struct ata_host *host_set) -{ - DPRINTK("\n"); -} - - -#define ERROR_HW_ACQUIRE_TIMEOUT_JIFFIES (10 * HZ) -static void sata_oxnas_error_handler(struct ata_port *ap) -{ - DPRINTK("Enter port_no %d\n", ap->port_no); - sata_oxnas_freeze_host(ap); - - /* If the core is busy here, make it idle */ - sata_oxnas_cleanup(ap->host); - - ata_std_error_handler(ap); - - sata_oxnas_thaw_host(ap); -} - -static int sata_oxnas_softreset(struct ata_link *link, unsigned int *class, - unsigned long deadline) -{ - struct ata_port *ap = link->ap; - struct sata_oxnas_port_priv *pd = ap->private_data; - void __iomem *port_base = pd->port_base; - int rc; - - struct ata_taskfile tf; - u32 Command_Reg; - - DPRINTK("ENTER\n"); - - port_base = pd->port_base; - - if (ata_link_offline(link)) { - DPRINTK("PHY reports no device\n"); - *class = ATA_DEV_NONE; - goto out; - } - - /* write value to register */ - iowrite32(0, port_base + ORB1); - iowrite32(0, port_base + ORB2); - iowrite32(0, port_base + ORB3); - iowrite32((ap->ctl) << 24, port_base + ORB4); - - /* command the core to send a control FIS */ - Command_Reg = ioread32(port_base + SATA_COMMAND); - Command_Reg &= ~SATA_OPCODE_MASK; - Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND; - iowrite32(Command_Reg, port_base + SATA_COMMAND); - udelay(20); /* FIXME: flush */ - - /* write value to register */ - iowrite32((ap->ctl | ATA_SRST) << 24, port_base + ORB4); - - /* command the core to send a control FIS */ - Command_Reg &= ~SATA_OPCODE_MASK; - Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND; - iowrite32(Command_Reg, port_base + SATA_COMMAND); - udelay(20); /* FIXME: flush */ - - /* write value to register */ - iowrite32((ap->ctl) << 24, port_base + ORB4); - - /* command the core to send a control FIS */ - Command_Reg &= ~SATA_OPCODE_MASK; - Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND; - iowrite32(Command_Reg, port_base + SATA_COMMAND); - - msleep(150); - - rc = ata_sff_wait_ready(link, deadline); - - /* if link is occupied, -ENODEV too is an error */ - if (rc && (rc != -ENODEV || sata_scr_valid(link))) { - ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc); - return rc; - } - - /* determine by signature whether we have ATA or ATAPI devices */ - sata_oxnas_tf_read(ap, &tf); - *class = ata_dev_classify(&tf); - - if (*class == ATA_DEV_UNKNOWN) - *class = ATA_DEV_NONE; - -out: - DPRINTK("EXIT, class=%u\n", *class); - return 0; -} - - -int sata_oxnas_init_controller(struct ata_host *host) -{ - return 0; -} - -/** - * Ref bug-6320 - * - * This code is a work around for a DMA hardware bug that will repeat the - * penultimate 8-bytes on some reads. This code will check that the amount - * of data transferred is a multiple of 512 bytes, if not the in it will - * fetch the correct data from a buffer in the SATA core and copy it into - * memory. - * - * @param port SATA port to check and if necessary, correct. - */ -static int sata_oxnas_bug_6320_detect(struct ata_port *ap) -{ - struct sata_oxnas_port_priv *pd = ap->private_data; - void __iomem *core_base = pd->core_base; - int is_read; - int quads_transferred; - int remainder; - int sector_quads_remaining; - int bug_present = 0; - - /* Only want to apply fix to reads */ - is_read = !(ioread32(core_base + DM_DBG1) & (ap->port_no ? - BIT(CORE_PORT1_DATA_DIR_BIT) : - BIT(CORE_PORT0_DATA_DIR_BIT))); - - /* Check for an incomplete transfer, i.e. not a multiple of 512 bytes - transferred (datacount_port register counts quads transferred) */ - quads_transferred = - ioread32(core_base + (ap->port_no ? - DATACOUNT_PORT1 : DATACOUNT_PORT0)); - - remainder = quads_transferred & 0x7f; - sector_quads_remaining = remainder ? (0x80 - remainder) : 0; - - if (is_read && (sector_quads_remaining == 2)) { - bug_present = 1; - } else if (sector_quads_remaining) { - if (is_read) { - ata_port_warn(ap, "SATA read fixup cannot deal with " - "%d quads remaining\n", - sector_quads_remaining); - } else { - ata_port_warn(ap, "SATA write fixup of %d quads " - "remaining not supported\n", - sector_quads_remaining); - } - } - - return bug_present; -} - -/* This port done an interrupt */ -static void sata_oxnas_port_irq(struct ata_port *ap, int force_error) -{ - struct ata_queued_cmd *qc; - struct sata_oxnas_port_priv *pd = ap->private_data; - void __iomem *port_base = pd->port_base; - - u32 int_status; - unsigned long flags = 0; - - DPRINTK("ENTER port %d irqstatus %x\n", ap->port_no, - ioread32(port_base + INT_STATUS)); - - if (ap->qc_active & (1 << ATA_TAG_INTERNAL)) { - qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL); - DPRINTK("completing non-ncq cmd\n"); - - if (qc) - ata_qc_complete(qc); - - return; - } - - qc = ata_qc_from_tag(ap, ap->link.active_tag); - - - /* record the port's interrupt */ - int_status = ioread32(port_base + INT_STATUS); - - /* If there's no command associated with this IRQ, ignore it. We may get - * spurious interrupts when cleaning-up after a failed command, ignore - * these too. */ - if (likely(qc)) { - /* get the status before any error cleanup */ - qc->err_mask = ac_err_mask(sata_oxnas_check_status(ap)); - if (force_error) { - /* Pretend there has been a link error */ - qc->err_mask |= AC_ERR_ATA_BUS; - DPRINTK(" ####force error####\n"); - } - /* tell libata we're done */ - local_irq_save(flags); - sata_oxnas_irq_clear(ap); - local_irq_restore(flags); - ata_qc_complete(qc); - } else { - VPRINTK("Ignoring interrupt, can't find the command tag=" - "%d %08x\n", ap->link.active_tag, ap->qc_active); - } - - /* maybe a hotplug event */ - if (unlikely(int_status & INT_LINK_SERROR)) { - u32 serror; - - sata_oxnas_scr_read_port(ap, SCR_ERROR, &serror); - if (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) { - ata_ehi_hotplugged(&ap->link.eh_info); - ata_port_freeze(ap); - } - } -} - -/** - * irq_handler is the interrupt handling routine registered with the system, - * by libata. - */ -static irqreturn_t sata_oxnas_interrupt(int irq, void *dev_instance) -{ - struct ata_host *ah = dev_instance; - struct sata_oxnas_host_priv *hd = ah->private_data; - void __iomem *core_base = hd->core_base; - - u32 int_status; - irqreturn_t ret = IRQ_NONE; - u32 port_no; - u32 mask; - int bug_present; - - /* loop until there are no more interrupts */ - while ((int_status = (ioread32(core_base + CORE_INT_STATUS)) & - (COREINT_END | (COREINT_END << 1)))) { - - /* clear any interrupt */ - iowrite32(int_status, core_base + CORE_INT_CLEAR); - - /* Only need workaround_bug_6320 for single disk systems as dual - * disk will use uCode which prevents this read underrun problem - * from occurring. - * All single disk systems will use port 0 */ - for (port_no = 0; port_no < hd->n_ports; ++port_no) { - /* check the raw end of command interrupt to see if the - * port is done */ - mask = (COREINT_END << port_no); - if (!(int_status & mask)) - continue; - - /* this port had an interrupt, clear it */ - iowrite32(mask, core_base + CORE_INT_CLEAR); - /* check for bug 6320 only if no microcode was loaded */ - bug_present = (hd->current_ucode == UNKNOWN_MODE) && - sata_oxnas_bug_6320_detect(ah->ports[port_no]); - - sata_oxnas_port_irq(ah->ports[port_no], - bug_present); - ret = IRQ_HANDLED; - } - } - - return ret; -} - -/* - * scsi mid-layer and libata interface structures - */ -static struct scsi_host_template sata_oxnas_sht = { - ATA_NCQ_SHT("sata_oxnas"), - .can_queue = SATA_OXNAS_QUEUE_DEPTH, - .sg_tablesize = SATA_OXNAS_MAX_PRD, - .dma_boundary = ATA_DMA_BOUNDARY, - .unchecked_isa_dma = 0, -}; - - -static struct ata_port_operations sata_oxnas_ops = { - .inherits = &sata_port_ops, - .qc_prep = sata_oxnas_qc_prep, - .qc_issue = sata_oxnas_qc_issue, - .qc_fill_rtf = sata_oxnas_qc_fill_rtf, - .qc_new = sata_oxnas_qc_new, - .qc_free = sata_oxnas_qc_free, - - .scr_read = sata_oxnas_scr_read, - .scr_write = sata_oxnas_scr_write, - - .freeze = sata_oxnas_freeze, - .thaw = sata_oxnas_thaw, - .softreset = sata_oxnas_softreset, - /* .hardreset = sata_oxnas_hardreset, */ - .postreset = sata_oxnas_postreset, - .error_handler = sata_oxnas_error_handler, - .post_internal_cmd = sata_oxnas_post_internal_cmd, - - .port_start = sata_oxnas_port_start, - .port_stop = sata_oxnas_port_stop, - - .host_stop = sata_oxnas_host_stop, - /* .pmp_attach = sata_oxnas_pmp_attach, */ - /* .pmp_detach = sata_oxnas_pmp_detach, */ - .sff_check_status = sata_oxnas_check_status, - .acquire_hw = sata_oxnas_acquire_hw, -}; - -static const struct ata_port_info sata_oxnas_port_info = { - .flags = SATA_OXNAS_HOST_FLAGS, - .pio_mask = ATA_PIO4, - .udma_mask = ATA_UDMA6, - .port_ops = &sata_oxnas_ops, -}; - -static int sata_oxnas_probe(struct platform_device *ofdev) -{ - int retval = -ENXIO; - int n_ports = 0; - void __iomem *port_base = NULL; - void __iomem *dmactl_base = NULL; - void __iomem *sgdma_base = NULL; - void __iomem *core_base = NULL; - void __iomem *phy_base = NULL; - struct reset_control *rstc; - - struct resource res = {}; - struct sata_oxnas_host_priv *host_priv = NULL; - int irq = 0; - struct ata_host *host = NULL; - struct clk *clk = NULL; - - const struct ata_port_info *ppi[] = { &sata_oxnas_port_info, NULL }; - - of_property_read_u32(ofdev->dev.of_node, "nr-ports", &n_ports); - if (n_ports < 1 || n_ports > SATA_OXNAS_MAX_PORTS) - goto error_exit_with_cleanup; - - port_base = of_iomap(ofdev->dev.of_node, 0); - if (!port_base) - goto error_exit_with_cleanup; - - dmactl_base = of_iomap(ofdev->dev.of_node, 1); - if (!dmactl_base) - goto error_exit_with_cleanup; - - sgdma_base = of_iomap(ofdev->dev.of_node, 2); - if (!sgdma_base) - goto error_exit_with_cleanup; - - core_base = of_iomap(ofdev->dev.of_node, 3); - if (!core_base) - goto error_exit_with_cleanup; - - phy_base = of_iomap(ofdev->dev.of_node, 4); - if (!phy_base) - goto error_exit_with_cleanup; - - host_priv = devm_kzalloc(&ofdev->dev, - sizeof(struct sata_oxnas_host_priv), - GFP_KERNEL); - if (!host_priv) - goto error_exit_with_cleanup; - - host_priv->port_base = port_base; - host_priv->dmactl_base = dmactl_base; - host_priv->sgdma_base = sgdma_base; - host_priv->core_base = core_base; - host_priv->phy_base = phy_base; - host_priv->n_ports = n_ports; - host_priv->current_ucode = UNKNOWN_MODE; - - if (!of_address_to_resource(ofdev->dev.of_node, 5, &res)) { - host_priv->dma_base = res.start; - host_priv->dma_size = resource_size(&res); - } - - irq = irq_of_parse_and_map(ofdev->dev.of_node, 0); - if (!irq) { - dev_err(&ofdev->dev, "invalid irq from platform\n"); - goto error_exit_with_cleanup; - } - host_priv->irq = irq; - - clk = of_clk_get(ofdev->dev.of_node, 0); - if (IS_ERR(clk)) { - retval = PTR_ERR(clk); - clk = NULL; - goto error_exit_with_cleanup; - } - host_priv->clk = clk; - - rstc = devm_reset_control_get(&ofdev->dev, "sata"); - if (IS_ERR(rstc)) { - retval = PTR_ERR(rstc); - goto error_exit_with_cleanup; - } - host_priv->rst_sata = rstc; - - rstc = devm_reset_control_get(&ofdev->dev, "link"); - if (IS_ERR(rstc)) { - retval = PTR_ERR(rstc); - goto error_exit_with_cleanup; - } - host_priv->rst_link = rstc; - - rstc = devm_reset_control_get(&ofdev->dev, "phy"); - if (IS_ERR(rstc)) { - retval = PTR_ERR(rstc); - goto error_exit_with_cleanup; - } - host_priv->rst_phy = rstc; - - /* allocate host structure */ - host = ata_host_alloc_pinfo(&ofdev->dev, ppi, n_ports); - - if (!host) { - retval = -ENOMEM; - goto error_exit_with_cleanup; - } - host->private_data = host_priv; - host->iomap = port_base; - - /* initialize core locking and queues */ - init_waitqueue_head(&host_priv->fast_wait_queue); - init_waitqueue_head(&host_priv->scsi_wait_queue); - spin_lock_init(&host_priv->phy_lock); - spin_lock_init(&host_priv->core_lock); - host_priv->core_locked = 0; - host_priv->reentrant_port_no = -1; - host_priv->hw_lock_count = 0; - host_priv->direct_lock_count = 0; - host_priv->locker_uid = 0; - host_priv->current_locker_type = SATA_UNLOCKED; - host_priv->isr_arg = NULL; - host_priv->isr_callback = NULL; - - /* initialize host controller */ - retval = sata_oxnas_init_controller(host); - if (retval) - goto error_exit_with_cleanup; - - /* - * Now, register with libATA core, this will also initiate the - * device discovery process, invoking our port_start() handler & - * error_handler() to execute a dummy softreset EH session - */ - ata_host_activate(host, irq, sata_oxnas_interrupt, SATA_OXNAS_IRQ_FLAG, - &sata_oxnas_sht); - - return 0; - -error_exit_with_cleanup: - if (irq) - irq_dispose_mapping(host_priv->irq); - if (clk) - clk_put(clk); - if (host) - ata_host_detach(host); - if (port_base) - iounmap(port_base); - if (sgdma_base) - iounmap(sgdma_base); - if (core_base) - iounmap(core_base); - if (phy_base) - iounmap(phy_base); - return retval; -} - - -static int sata_oxnas_remove(struct platform_device *ofdev) -{ - struct ata_host *host = dev_get_drvdata(&ofdev->dev); - struct sata_oxnas_host_priv *host_priv = host->private_data; - - ata_host_detach(host); - - irq_dispose_mapping(host_priv->irq); - iounmap(host_priv->port_base); - iounmap(host_priv->sgdma_base); - iounmap(host_priv->core_base); - - /* reset Controller, Link and PHY */ - reset_control_assert(host_priv->rst_sata); - reset_control_assert(host_priv->rst_link); - reset_control_assert(host_priv->rst_phy); - - /* Disable the clock to the SATA block */ - clk_disable_unprepare(host_priv->clk); - clk_put(host_priv->clk); - - return 0; -} - -#ifdef CONFIG_PM -static int sata_oxnas_suspend(struct platform_device *op, pm_message_t state) -{ - struct ata_host *host = dev_get_drvdata(&op->dev); - - return ata_host_suspend(host, state); -} - -static int sata_oxnas_resume(struct platform_device *op) -{ - struct ata_host *host = dev_get_drvdata(&op->dev); - int ret; - - ret = sata_oxnas_init_controller(host); - if (ret) { - dev_err(&op->dev, "Error initializing hardware\n"); - return ret; - } - ata_host_resume(host); - return 0; -} -#endif - - - -static struct of_device_id oxnas_sata_match[] = { - { - .compatible = "plxtech,nas782x-sata", - }, - {}, -}; - -MODULE_DEVICE_TABLE(of, oxnas_sata_match); - -static struct platform_driver oxnas_sata_driver = { - .driver = { - .name = "oxnas-sata", - .owner = THIS_MODULE, - .of_match_table = oxnas_sata_match, - }, - .probe = sata_oxnas_probe, - .remove = sata_oxnas_remove, -#ifdef CONFIG_PM - .suspend = sata_oxnas_suspend, - .resume = sata_oxnas_resume, -#endif -}; - -module_platform_driver(oxnas_sata_driver); - -MODULE_LICENSE("GPL"); -MODULE_VERSION("1.0"); -MODULE_AUTHOR("Oxford Semiconductor Ltd."); -MODULE_DESCRIPTION("low-level driver for Oxford 934 SATA core"); diff --git a/target/linux/oxnas/files/drivers/clk/clk-oxnas.c b/target/linux/oxnas/files/drivers/clk/clk-oxnas.c deleted file mode 100644 index 4dc6c44992..0000000000 --- a/target/linux/oxnas/files/drivers/clk/clk-oxnas.c +++ /dev/null @@ -1,297 +0,0 @@ -/* - * Copyright (C) 2010 Broadcom - * Copyright (C) 2012 Stephen Warren - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <linux/clk.h> -#include <linux/clkdev.h> -#include <linux/clk-provider.h> -#include <linux/of.h> -#include <linux/delay.h> -#include <linux/stringify.h> -#include <linux/reset.h> -#include <linux/io.h> -#include <mach/hardware.h> -#include <mach/utils.h> - -#define MHZ (1000 * 1000) - -struct clk_oxnas_pllb { - struct clk_hw hw; - struct device_node *devnode; - struct reset_control *rstc; -}; - -#define to_clk_oxnas_pllb(_hw) container_of(_hw, struct clk_oxnas_pllb, hw) - -static unsigned long plla_clk_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - unsigned long fin = parent_rate; - unsigned long pll0; - unsigned long fbdiv, refdiv, outdiv; - - pll0 = readl_relaxed(SYS_CTRL_PLLA_CTRL0); - refdiv = (pll0 >> PLLA_REFDIV_SHIFT) & PLLA_REFDIV_MASK; - refdiv += 1; - outdiv = (pll0 >> PLLA_OUTDIV_SHIFT) & PLLA_OUTDIV_MASK; - outdiv += 1; - fbdiv = readl_relaxed(SYS_CTRL_PLLA_CTRL1); - - /* seems we will not be here when pll is bypassed, so ignore this - * case */ - - return fin / MHZ * fbdiv / (refdiv * outdiv) / 32768 * MHZ; -} - -static const char *pll_clk_parents[] = { - "oscillator", -}; - -static struct clk_ops plla_ops = { - .recalc_rate = plla_clk_recalc_rate, -}; - -static struct clk_init_data clk_plla_init = { - .name = "plla", - .ops = &plla_ops, - .parent_names = pll_clk_parents, - .num_parents = ARRAY_SIZE(pll_clk_parents), -}; - -static struct clk_hw plla_hw = { - .init = &clk_plla_init, -}; - -static int pllb_clk_is_prepared(struct clk_hw *hw) -{ - struct clk_oxnas_pllb *pllb = to_clk_oxnas_pllb(hw); - - return !!pllb->rstc; -} - -static int pllb_clk_prepare(struct clk_hw *hw) -{ - struct clk_oxnas_pllb *pllb = to_clk_oxnas_pllb(hw); - - pllb->rstc = of_reset_control_get(pllb->devnode, NULL); - - return IS_ERR(pllb->rstc) ? PTR_ERR(pllb->rstc) : 0; -} - -static void pllb_clk_unprepare(struct clk_hw *hw) -{ - struct clk_oxnas_pllb *pllb = to_clk_oxnas_pllb(hw); - - BUG_ON(IS_ERR(pllb->rstc)); - - reset_control_put(pllb->rstc); - pllb->rstc = NULL; -} - -static int pllb_clk_enable(struct clk_hw *hw) -{ - struct clk_oxnas_pllb *pllb = to_clk_oxnas_pllb(hw); - - BUG_ON(IS_ERR(pllb->rstc)); - - /* put PLL into bypass */ - oxnas_register_set_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS)); - wmb(); - udelay(10); - reset_control_assert(pllb->rstc); - udelay(10); - /* set PLL B control information */ - writel((1 << PLLB_ENSAT) | (1 << PLLB_OUTDIV) | (2 << PLLB_REFDIV), - SEC_CTRL_PLLB_CTRL0); - reset_control_deassert(pllb->rstc); - udelay(100); - oxnas_register_clear_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS)); - - return 0; -} - -static void pllb_clk_disable(struct clk_hw *hw) -{ - struct clk_oxnas_pllb *pllb = to_clk_oxnas_pllb(hw); - - BUG_ON(IS_ERR(pllb->rstc)); - - /* put PLL into bypass */ - oxnas_register_set_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS)); - wmb(); - udelay(10); - - reset_control_assert(pllb->rstc); -} - -static struct clk_ops pllb_ops = { - .prepare = pllb_clk_prepare, - .unprepare = pllb_clk_unprepare, - .is_prepared = pllb_clk_is_prepared, - .enable = pllb_clk_enable, - .disable = pllb_clk_disable, -}; - -static struct clk_init_data clk_pllb_init = { - .name = "pllb", - .ops = &pllb_ops, - .parent_names = pll_clk_parents, - .num_parents = ARRAY_SIZE(pll_clk_parents), -}; - - -/* standard gate clock */ -struct clk_std { - struct clk_hw hw; - signed char bit; -}; - -#define NUM_STD_CLKS 17 -#define to_stdclk(_hw) container_of(_hw, struct clk_std, hw) - -static int std_clk_is_enabled(struct clk_hw *hw) -{ - struct clk_std *std = to_stdclk(hw); - - return readl_relaxed(SYSCTRL_CLK_STAT) & BIT(std->bit); -} - -static int std_clk_enable(struct clk_hw *hw) -{ - struct clk_std *std = to_stdclk(hw); - - writel(BIT(std->bit), SYS_CTRL_CLK_SET_CTRL); - return 0; -} - -static void std_clk_disable(struct clk_hw *hw) -{ - struct clk_std *std = to_stdclk(hw); - - writel(BIT(std->bit), SYS_CTRL_CLK_CLR_CTRL); -} - -static struct clk_ops std_clk_ops = { - .enable = std_clk_enable, - .disable = std_clk_disable, - .is_enabled = std_clk_is_enabled, -}; - -static const char *std_clk_parents[] = { - "oscillator", -}; - -static const char *eth_parents[] = { - "gmacclk", -}; - -#define DECLARE_STD_CLKP(__clk, __bit, __parent) \ -static struct clk_init_data clk_##__clk##_init = { \ - .name = __stringify(__clk), \ - .ops = &std_clk_ops, \ - .parent_names = __parent, \ - .num_parents = ARRAY_SIZE(__parent), \ -}; \ - \ -static struct clk_std clk_##__clk = { \ - .bit = __bit, \ - .hw = { \ - .init = &clk_##__clk##_init, \ - }, \ -} - -#define DECLARE_STD_CLK(__clk, __bit) DECLARE_STD_CLKP(__clk, __bit, \ - std_clk_parents) - -DECLARE_STD_CLK(leon, 0); -DECLARE_STD_CLK(dma_sgdma, 1); -DECLARE_STD_CLK(cipher, 2); -DECLARE_STD_CLK(sd, 3); -DECLARE_STD_CLK(sata, 4); -DECLARE_STD_CLK(audio, 5); -DECLARE_STD_CLK(usbmph, 6); -DECLARE_STD_CLKP(etha, 7, eth_parents); -DECLARE_STD_CLK(pciea, 8); -DECLARE_STD_CLK(static, 9); -DECLARE_STD_CLK(ethb, 10); -DECLARE_STD_CLK(pcieb, 11); -DECLARE_STD_CLK(ref600, 12); -DECLARE_STD_CLK(usbdev, 13); - -struct clk_hw *std_clk_hw_tbl[] = { - &clk_leon.hw, - &clk_dma_sgdma.hw, - &clk_cipher.hw, - &clk_sd.hw, - &clk_sata.hw, - &clk_audio.hw, - &clk_usbmph.hw, - &clk_etha.hw, - &clk_pciea.hw, - &clk_static.hw, - &clk_ethb.hw, - &clk_pcieb.hw, - &clk_ref600.hw, - &clk_usbdev.hw, -}; - -struct clk *std_clk_tbl[ARRAY_SIZE(std_clk_hw_tbl)]; - -static struct clk_onecell_data std_clk_data; - -void __init oxnas_init_stdclk(struct device_node *np) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(std_clk_hw_tbl); i++) { - std_clk_tbl[i] = clk_register(NULL, std_clk_hw_tbl[i]); - BUG_ON(IS_ERR(std_clk_tbl[i])); - } - std_clk_data.clks = std_clk_tbl; - std_clk_data.clk_num = ARRAY_SIZE(std_clk_tbl); - of_clk_add_provider(np, of_clk_src_onecell_get, &std_clk_data); -} -CLK_OF_DECLARE(oxnas_pllstd, "plxtech,nas782x-stdclk", oxnas_init_stdclk); - -void __init oxnas_init_plla(struct device_node *np) -{ - struct clk *clk; - - clk = clk_register(NULL, &plla_hw); - BUG_ON(IS_ERR(clk)); - /* mark it as enabled */ - clk_prepare_enable(clk); - of_clk_add_provider(np, of_clk_src_simple_get, clk); -} -CLK_OF_DECLARE(oxnas_plla, "plxtech,nas782x-plla", oxnas_init_plla); - -void __init oxnas_init_pllb(struct device_node *np) -{ - struct clk *clk; - struct clk_oxnas_pllb *pllb; - - pllb = kmalloc(sizeof(*pllb), GFP_KERNEL); - BUG_ON(!pllb); - - pllb->hw.init = &clk_pllb_init; - pllb->devnode = np; - pllb->rstc = NULL; - - clk = clk_register(NULL, &pllb->hw); - BUG_ON(IS_ERR(clk)); - of_clk_add_provider(np, of_clk_src_simple_get, clk); -} -CLK_OF_DECLARE(oxnas_pllb, "plxtech,nas782x-pllb", oxnas_init_pllb); diff --git a/target/linux/oxnas/files/drivers/clocksource/oxnas_rps_timer.c b/target/linux/oxnas/files/drivers/clocksource/oxnas_rps_timer.c deleted file mode 100644 index 7c8c4cf435..0000000000 --- a/target/linux/oxnas/files/drivers/clocksource/oxnas_rps_timer.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * arch/arm/mach-ox820/rps-time.c - * - * Copyright (C) 2009 Oxford Semiconductor Ltd - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/io.h> -#include <linux/clockchips.h> -#include <linux/clk.h> -#include <linux/of_irq.h> -#include <linux/of_address.h> -#include <linux/sched_clock.h> -#include <mach/hardware.h> - -enum { - TIMER_LOAD = 0, - TIMER_CURR = 4, - TIMER_CTRL = 8, - TIMER_CLRINT = 0xC, - - TIMER_BITS = 24, - - TIMER_MAX_VAL = (1 << TIMER_BITS) - 1, - - TIMER_PERIODIC = (1 << 6), - TIMER_ENABLE = (1 << 7), - - TIMER_DIV1 = (0 << 2), - TIMER_DIV16 = (1 << 2), - TIMER_DIV256 = (2 << 2), - - TIMER1_OFFSET = 0, - TIMER2_OFFSET = 0x20, - -}; - -static u64 notrace rps_read_sched_clock(void) -{ - return ~readl_relaxed(RPSA_TIMER2_VAL); -} - -static void __init rps_clocksource_init(void __iomem *base, ulong ref_rate) -{ - int ret; - ulong clock_rate; - /* use prescale 16 */ - clock_rate = ref_rate / 16; - - iowrite32(TIMER_MAX_VAL, base + TIMER_LOAD); - iowrite32(TIMER_PERIODIC | TIMER_ENABLE | TIMER_DIV16, - base + TIMER_CTRL); - - ret = clocksource_mmio_init(base + TIMER_CURR, "rps_clocksource_timer", - clock_rate, 250, TIMER_BITS, - clocksource_mmio_readl_down); - if (ret) - panic("can't register clocksource\n"); - - sched_clock_register(rps_read_sched_clock, TIMER_BITS, clock_rate); -} - -static void __init rps_timer_init(struct device_node *np) -{ - struct clk *refclk; - unsigned long ref_rate; - void __iomem *base; - - refclk = of_clk_get(np, 0); - - if (IS_ERR(refclk) || clk_prepare_enable(refclk)) - panic("rps_timer_init: failed to get refclk\n"); - ref_rate = clk_get_rate(refclk); - - base = of_iomap(np, 0); - if (!base) - panic("rps_timer_init: failed to map io\n"); - - rps_clocksource_init(base + TIMER2_OFFSET, ref_rate); -} - -CLOCKSOURCE_OF_DECLARE(nas782x, "plxtech,nas782x-rps-timer", rps_timer_init); diff --git a/target/linux/oxnas/files/drivers/irqchip/irq-rps.c b/target/linux/oxnas/files/drivers/irqchip/irq-rps.c deleted file mode 100644 index f2b0829de6..0000000000 --- a/target/linux/oxnas/files/drivers/irqchip/irq-rps.c +++ /dev/null @@ -1,145 +0,0 @@ -#include <linux/irqdomain.h> -#include <linux/irq.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_irq.h> -#include <linux/irqchip/chained_irq.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/irqchip.h> - -struct rps_chip_data { - void __iomem *base; - struct irq_chip chip; - struct irq_domain *domain; -} rps_data; - -enum { - RPS_IRQ_BASE = 64, - RPS_IRQ_COUNT = 32, - PRS_HWIRQ_BASE = 0, - - RPS_STATUS = 0, - RPS_RAW_STATUS = 4, - RPS_UNMASK = 8, - RPS_MASK = 0xc, -}; - -/* - * Routines to acknowledge, disable and enable interrupts - */ -static void rps_mask_irq(struct irq_data *d) -{ - struct rps_chip_data *chip_data = irq_data_get_irq_chip_data(d); - u32 mask = BIT(d->hwirq); - - iowrite32(mask, chip_data->base + RPS_MASK); -} - -static void rps_unmask_irq(struct irq_data *d) -{ - struct rps_chip_data *chip_data = irq_data_get_irq_chip_data(d); - u32 mask = BIT(d->hwirq); - - iowrite32(mask, chip_data->base + RPS_UNMASK); -} - -static struct irq_chip rps_chip = { - .name = "RPS", - .irq_mask = rps_mask_irq, - .irq_unmask = rps_unmask_irq, -}; - -static int rps_irq_domain_xlate(struct irq_domain *d, - struct device_node *controller, - const u32 *intspec, unsigned int intsize, - unsigned long *out_hwirq, - unsigned int *out_type) -{ - if (irq_domain_get_of_node(d) != controller) - return -EINVAL; - if (intsize < 1) - return -EINVAL; - - *out_hwirq = intspec[0]; - /* Honestly I do not know the type */ - *out_type = IRQ_TYPE_LEVEL_HIGH; - - return 0; -} - -static int rps_irq_domain_map(struct irq_domain *d, unsigned int irq, - irq_hw_number_t hw) -{ - irq_set_chip_and_handler(irq, &rps_chip, handle_level_irq); - irq_set_probe(irq); - irq_set_chip_data(irq, d->host_data); - return 0; -} - -const struct irq_domain_ops rps_irq_domain_ops = { - .map = rps_irq_domain_map, - .xlate = rps_irq_domain_xlate, -}; - -static void rps_handle_cascade_irq(struct irq_desc *desc) -{ - struct rps_chip_data *chip_data = irq_desc_get_handler_data(desc); - struct irq_chip *chip = irq_desc_get_chip(desc); - unsigned int cascade_irq, rps_irq; - u32 status; - - chained_irq_enter(chip, desc); - - status = ioread32(chip_data->base + RPS_STATUS); - rps_irq = __ffs(status); - cascade_irq = irq_find_mapping(chip_data->domain, rps_irq); - - if (unlikely(rps_irq >= RPS_IRQ_COUNT)) - handle_bad_irq(desc); - else - generic_handle_irq(cascade_irq); - - chained_irq_exit(chip, desc); -} - -#ifdef CONFIG_OF -int __init rps_of_init(struct device_node *node, struct device_node *parent) -{ - void __iomem *rps_base; - int irq_start = RPS_IRQ_BASE; - int irq_base; - int irq; - - if (WARN_ON(!node)) - return -ENODEV; - - rps_base = of_iomap(node, 0); - WARN(!rps_base, "unable to map rps registers\n"); - rps_data.base = rps_base; - - irq_base = irq_alloc_descs(irq_start, 0, RPS_IRQ_COUNT, numa_node_id()); - if (IS_ERR_VALUE(irq_base)) { - WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", - irq_start); - irq_base = irq_start; - } - - rps_data.domain = irq_domain_add_legacy(node, RPS_IRQ_COUNT, irq_base, - PRS_HWIRQ_BASE, &rps_irq_domain_ops, &rps_data); - - if (WARN_ON(!rps_data.domain)) - return -ENOMEM; - - if (parent) { - irq = irq_of_parse_and_map(node, 0); - if (irq_set_handler_data(irq, &rps_data) != 0) - BUG(); - irq_set_chained_handler(irq, rps_handle_cascade_irq); - } - return 0; - -} - -IRQCHIP_DECLARE(nas782x, "plxtech,nas782x-rps", rps_of_init); -#endif diff --git a/target/linux/oxnas/files/drivers/mtd/nand/oxnas_nand.c b/target/linux/oxnas/files/drivers/mtd/nand/oxnas_nand.c deleted file mode 100644 index 36807b7767..0000000000 --- a/target/linux/oxnas/files/drivers/mtd/nand/oxnas_nand.c +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Oxford Semiconductor OXNAS NAND driver - - * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com> - * Heavily based on plat_nand.c : - * Author: Vitaly Wool <vitalywool@gmail.com> - * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com> - * Copyright (C) 2012 John Crispin <blogic@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include <linux/err.h> -#include <linux/io.h> -#include <linux/module.h> -#include <linux/platform_device.h> -#include <linux/slab.h> -#include <linux/clk.h> -#include <linux/reset.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/nand.h> -#include <linux/mtd/partitions.h> -#include <linux/of.h> - -/* Nand commands */ -#define OXNAS_NAND_CMD_ALE BIT(18) -#define OXNAS_NAND_CMD_CLE BIT(19) - -#define OXNAS_NAND_MAX_CHIPS 1 - -struct oxnas_nand { - struct nand_hw_control base; - void __iomem *io_base; - struct clk *clk; - struct nand_chip *chips[OXNAS_NAND_MAX_CHIPS]; - unsigned long ctrl; - struct mtd_partition *partitions; - int nr_partitions; -}; - -static uint8_t oxnas_nand_read_byte(struct mtd_info *mtd) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct oxnas_nand *oxnas = nand_get_controller_data(chip); - - return readb(oxnas->io_base); -} - -static void oxnas_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct oxnas_nand *oxnas = nand_get_controller_data(chip); - - ioread8_rep(oxnas->io_base, buf, len); -} - -static void oxnas_nand_write_buf(struct mtd_info *mtd, - const uint8_t *buf, int len) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct oxnas_nand *oxnas = nand_get_controller_data(chip); - - iowrite8_rep(oxnas->io_base + oxnas->ctrl, buf, len); -} - -/* Single CS command control */ -static void oxnas_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, - unsigned int ctrl) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct oxnas_nand *oxnas = nand_get_controller_data(chip); - - if (ctrl & NAND_CTRL_CHANGE) { - if (ctrl & NAND_CLE) - oxnas->ctrl = OXNAS_NAND_CMD_CLE; - else if (ctrl & NAND_ALE) - oxnas->ctrl = OXNAS_NAND_CMD_ALE; - else - oxnas->ctrl = 0; - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, oxnas->io_base + oxnas->ctrl); -} - -/* - * Probe for the NAND device. - */ -static int oxnas_nand_probe(struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node; - struct device_node *nand_np; - struct oxnas_nand *oxnas; - struct nand_chip *chip; - struct mtd_info *mtd; - struct resource *res; - int nchips = 0; - int count = 0; - int err = 0; - - /* Allocate memory for the device structure (and zero it) */ - oxnas = devm_kzalloc(&pdev->dev, sizeof(struct nand_chip), - GFP_KERNEL); - if (!oxnas) - return -ENOMEM; - - nand_hw_control_init(&oxnas->base); - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - oxnas->io_base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(oxnas->io_base)) - return PTR_ERR(oxnas->io_base); - - oxnas->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(oxnas->clk)) - oxnas->clk = NULL; - - /* Only a single chip node is supported */ - count = of_get_child_count(np); - if (count > 1) - return -EINVAL; - - clk_prepare_enable(oxnas->clk); - device_reset_optional(&pdev->dev); - - for_each_child_of_node(np, nand_np) { - chip = devm_kzalloc(&pdev->dev, sizeof(struct nand_chip), - GFP_KERNEL); - if (!chip) - return -ENOMEM; - - chip->controller = &oxnas->base; - - nand_set_flash_node(chip, nand_np); - nand_set_controller_data(chip, oxnas); - - mtd = nand_to_mtd(chip); - mtd->dev.parent = &pdev->dev; - mtd->priv = chip; - - chip->cmd_ctrl = oxnas_nand_cmd_ctrl; - chip->read_buf = oxnas_nand_read_buf; - chip->read_byte = oxnas_nand_read_byte; - chip->write_buf = oxnas_nand_write_buf; - chip->chip_delay = 30; - - /* Scan to find existence of the device */ - err = nand_scan(mtd, 1); - if (err) - return err; - - err = mtd_device_register(mtd, NULL, 0); - if (err) { - nand_release(mtd); - return err; - } - - oxnas->chips[nchips] = chip; - ++nchips; - } - - /* Exit if no chips found */ - if (!nchips) - return -ENODEV; - - platform_set_drvdata(pdev, oxnas); - - return 0; -} - -static int oxnas_nand_remove(struct platform_device *pdev) -{ - struct oxnas_nand *oxnas = platform_get_drvdata(pdev); - - if (oxnas->chips[0]) - nand_release(nand_to_mtd(oxnas->chips[0])); - - clk_disable_unprepare(oxnas->clk); - - return 0; -} - -static const struct of_device_id oxnas_nand_match[] = { - { .compatible = "oxsemi,ox820-nand" }, - {}, -}; -MODULE_DEVICE_TABLE(of, oxnas_nand_match); - -static struct platform_driver oxnas_nand_driver = { - .probe = oxnas_nand_probe, - .remove = oxnas_nand_remove, - .driver = { - .name = "oxnas_nand", - .of_match_table = oxnas_nand_match, - }, -}; - -module_platform_driver(oxnas_nand_driver); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>"); -MODULE_DESCRIPTION("Oxnas NAND driver"); -MODULE_ALIAS("platform:oxnas_nand"); diff --git a/target/linux/oxnas/files/drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c b/target/linux/oxnas/files/drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c deleted file mode 100644 index aafb118144..0000000000 --- a/target/linux/oxnas/files/drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c +++ /dev/null @@ -1,145 +0,0 @@ -/* Copyright OpenWrt.org (C) 2015. - * Copyright Altera Corporation (C) 2014. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, version 2, - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - * - * Adopted from dwmac-socfpga.c - * Based on code found in mach-oxnas.c - */ - -#include <linux/mfd/syscon.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_net.h> -#include <linux/phy.h> -#include <linux/regmap.h> -#include <linux/reset.h> -#include <linux/stmmac.h> - -#include <mach/hardware.h> - -#include "stmmac.h" -#include "stmmac_platform.h" - -struct oxnas_gmac { - struct clk *clk; -}; - -static int oxnas_gmac_init(struct platform_device *pdev, void *priv) -{ - struct oxnas_gmac *bsp_priv = priv; - int ret = 0; - unsigned value; - - ret = device_reset(&pdev->dev); - if (ret) - return ret; - - if (IS_ERR(bsp_priv->clk)) - return PTR_ERR(bsp_priv->clk); - clk_prepare_enable(bsp_priv->clk); - - value = readl(SYS_CTRL_GMAC_CTRL); - - /* Enable GMII_GTXCLK to follow GMII_REFCLK, required for gigabit PHY */ - value |= BIT(SYS_CTRL_GMAC_CKEN_GTX); - /* Use simple mux for 25/125 Mhz clock switching */ - value |= BIT(SYS_CTRL_GMAC_SIMPLE_MUX); - /* set auto switch tx clock source */ - value |= BIT(SYS_CTRL_GMAC_AUTO_TX_SOURCE); - /* enable tx & rx vardelay */ - value |= BIT(SYS_CTRL_GMAC_CKEN_TX_OUT); - value |= BIT(SYS_CTRL_GMAC_CKEN_TXN_OUT); - value |= BIT(SYS_CTRL_GMAC_CKEN_TX_IN); - value |= BIT(SYS_CTRL_GMAC_CKEN_RX_OUT); - value |= BIT(SYS_CTRL_GMAC_CKEN_RXN_OUT); - value |= BIT(SYS_CTRL_GMAC_CKEN_RX_IN); - writel(value, SYS_CTRL_GMAC_CTRL); - - /* set tx & rx vardelay */ - value = 0; - value |= SYS_CTRL_GMAC_TX_VARDELAY(4); - value |= SYS_CTRL_GMAC_TXN_VARDELAY(2); - value |= SYS_CTRL_GMAC_RX_VARDELAY(10); - value |= SYS_CTRL_GMAC_RXN_VARDELAY(8); - writel(value, SYS_CTRL_GMAC_DELAY_CTRL); - - return 0; -} - -static void oxnas_gmac_exit(struct platform_device *pdev, void *priv) -{ - struct reset_control *rstc; - - clk_disable_unprepare(priv); - devm_clk_put(&pdev->dev, priv); - - rstc = reset_control_get(&pdev->dev, NULL); - if (!IS_ERR(rstc)) { - reset_control_assert(rstc); - reset_control_put(rstc); - } -} - -static int oxnas_gmac_probe(struct platform_device *pdev) -{ - struct plat_stmmacenet_data *plat_dat; - struct stmmac_resources stmmac_res; - int ret; - struct device *dev = &pdev->dev; - struct oxnas_gmac *bsp_priv; - - bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL); - if (!bsp_priv) - return -ENOMEM; - bsp_priv->clk = devm_clk_get(dev, "gmac"); - if (IS_ERR(bsp_priv->clk)) - return PTR_ERR(bsp_priv->clk); - - ret = stmmac_get_platform_resources(pdev, &stmmac_res); - if (ret) - return ret; - - plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); - if (IS_ERR(plat_dat)) - return PTR_ERR(plat_dat); - - plat_dat->bsp_priv = bsp_priv; - plat_dat->init = oxnas_gmac_init; - plat_dat->exit = oxnas_gmac_exit; - - ret = oxnas_gmac_init(pdev, bsp_priv); - if (ret) - return ret; - - return stmmac_dvr_probe(dev, plat_dat, &stmmac_res); -} - -static const struct of_device_id oxnas_gmac_match[] = { - { .compatible = "plxtech,nas782x-gmac" }, - { } -}; -MODULE_DEVICE_TABLE(of, oxnas_gmac_match); - -static struct platform_driver oxnas_gmac_driver = { - .probe = oxnas_gmac_probe, - .remove = stmmac_pltfr_remove, - .driver = { - .name = "oxnas-gmac", - .pm = &stmmac_pltfr_pm_ops, - .of_match_table = oxnas_gmac_match, - }, -}; -module_platform_driver(oxnas_gmac_driver); - -MODULE_LICENSE("GPL v2"); diff --git a/target/linux/oxnas/files/drivers/pci/host/pcie-oxnas.c b/target/linux/oxnas/files/drivers/pci/host/pcie-oxnas.c deleted file mode 100644 index 9e8d6d9f93..0000000000 --- a/target/linux/oxnas/files/drivers/pci/host/pcie-oxnas.c +++ /dev/null @@ -1,676 +0,0 @@ -/* - * PCIe driver for PLX NAS782X SoCs - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/pci.h> -#include <linux/clk.h> -#include <linux/module.h> -#include <linux/mbus.h> -#include <linux/slab.h> -#include <linux/platform_device.h> -#include <linux/of_address.h> -#include <linux/of_pci.h> -#include <linux/of_irq.h> -#include <linux/of_platform.h> -#include <linux/of_gpio.h> -#include <linux/gpio.h> -#include <linux/delay.h> -#include <linux/clk.h> -#include <linux/reset.h> -#include <mach/iomap.h> -#include <mach/hardware.h> -#include <mach/utils.h> - -#define VERSION_ID_MAGIC 0x082510b5 -#define LINK_UP_TIMEOUT_SECONDS 1 -#define NUM_CONTROLLERS 1 - -enum { - PCIE_DEVICE_TYPE_MASK = 0x0F, - PCIE_DEVICE_TYPE_ENDPOINT = 0, - PCIE_DEVICE_TYPE_LEGACY_ENDPOINT = 1, - PCIE_DEVICE_TYPE_ROOT = 4, - - PCIE_LTSSM = BIT(4), - PCIE_READY_ENTR_L23 = BIT(9), - PCIE_LINK_UP = BIT(11), - PCIE_OBTRANS = BIT(12), -}; - -enum { - HCSL_BIAS_ON = BIT(0), - HCSL_PCIE_EN = BIT(1), - HCSL_PCIEA_EN = BIT(2), - HCSL_PCIEB_EN = BIT(3), -}; - -enum { - /* pcie phy reg offset */ - PHY_ADDR = 0, - PHY_DATA = 4, - /* phy data reg bits */ - READ_EN = BIT(16), - WRITE_EN = BIT(17), - CAP_DATA = BIT(18), -}; - -/* core config registers */ -enum { - PCI_CONFIG_VERSION_DEVICEID = 0, - PCI_CONFIG_COMMAND_STATUS = 4, -}; - -/* inbound config registers */ -enum { - IB_ADDR_XLATE_ENABLE = 0xFC, - - /* bits */ - ENABLE_IN_ADDR_TRANS = BIT(0), -}; - -/* outbound config registers, offset relative to PCIE_POM0_MEM_ADDR */ -enum { - PCIE_POM0_MEM_ADDR = 0, - PCIE_POM1_MEM_ADDR = 4, - PCIE_IN0_MEM_ADDR = 8, - PCIE_IN1_MEM_ADDR = 12, - PCIE_IN_IO_ADDR = 16, - PCIE_IN_CFG0_ADDR = 20, - PCIE_IN_CFG1_ADDR = 24, - PCIE_IN_MSG_ADDR = 28, - PCIE_IN0_MEM_LIMIT = 32, - PCIE_IN1_MEM_LIMIT = 36, - PCIE_IN_IO_LIMIT = 40, - PCIE_IN_CFG0_LIMIT = 44, - PCIE_IN_CFG1_LIMIT = 48, - PCIE_IN_MSG_LIMIT = 52, - PCIE_AHB_SLAVE_CTRL = 56, - - PCIE_SLAVE_BE_SHIFT = 22, -}; - -#define ADDR_VAL(val) ((val) & 0xFFFF) -#define DATA_VAL(val) ((val) & 0xFFFF) - -#define PCIE_SLAVE_BE(val) ((val) << PCIE_SLAVE_BE_SHIFT) -#define PCIE_SLAVE_BE_MASK PCIE_SLAVE_BE(0xF) - -struct oxnas_pcie_shared { - /* seems all access are serialized, no lock required */ - int refcount; -}; - -/* Structure representing one PCIe interfaces */ -struct oxnas_pcie { - void __iomem *cfgbase; - void __iomem *base; - void __iomem *inbound; - void __iomem *outbound; - void __iomem *pcie_ctrl; - - int haslink; - struct platform_device *pdev; - struct resource io; - struct resource cfg; - struct resource pre_mem; /* prefetchable */ - struct resource non_mem; /* non-prefetchable */ - struct resource busn; /* max available bus numbers */ - int card_reset; /* gpio pin, optional */ - unsigned hcsl_en; /* hcsl pci enable bit */ - struct clk *clk; - struct clk *busclk; /* for pcie bus, actually the PLLB */ - void *private_data[1]; - spinlock_t lock; -}; - -static struct oxnas_pcie_shared pcie_shared = { - .refcount = 0, -}; - -static inline struct oxnas_pcie *sys_to_pcie(struct pci_sys_data *sys) -{ - return sys->private_data; -} - - -static inline void set_out_lanes(struct oxnas_pcie *pcie, unsigned lanes) -{ - oxnas_register_value_mask(pcie->outbound + PCIE_AHB_SLAVE_CTRL, - PCIE_SLAVE_BE_MASK, PCIE_SLAVE_BE(lanes)); - wmb(); -} - -static int oxnas_pcie_link_up(struct oxnas_pcie *pcie) -{ - unsigned long end; - - /* Poll for PCIE link up */ - end = jiffies + (LINK_UP_TIMEOUT_SECONDS * HZ); - while (!time_after(jiffies, end)) { - if (readl(pcie->pcie_ctrl) & PCIE_LINK_UP) - return 1; - } - return 0; -} - -static void __init oxnas_pcie_setup_hw(struct oxnas_pcie *pcie) -{ - /* We won't have any inbound address translation. This allows PCI - * devices to access anywhere in the AHB address map. Might be regarded - * as a bit dangerous, but let's get things working before we worry - * about that - */ - oxnas_register_clear_mask(pcie->inbound + IB_ADDR_XLATE_ENABLE, - ENABLE_IN_ADDR_TRANS); - wmb(); - - /* - * Program outbound translation windows - * - * Outbound window is what is referred to as "PCI client" region in HRM - * - * Could use the larger alternative address space to get >>64M regions - * for graphics cards etc., but will not bother at this point. - * - * IP bug means that AMBA window size must be a power of 2 - * - * Set mem0 window for first 16MB of outbound window non-prefetchable - * Set mem1 window for second 16MB of outbound window prefetchable - * Set io window for next 16MB of outbound window - * Set cfg0 for final 1MB of outbound window - * - * Ignore mem1, cfg1 and msg windows for now as no obvious use cases for - * 820 that would need them - * - * Probably ideally want no offset between mem0 window start as seen by - * ARM and as seen on PCI bus and get Linux to assign memory regions to - * PCI devices using the same "PCI client" region start address as seen - * by ARM - */ - - /* Set PCIeA mem0 region to be 1st 16MB of the 64MB PCIeA window */ - writel_relaxed(pcie->non_mem.start, pcie->outbound + PCIE_IN0_MEM_ADDR); - writel_relaxed(pcie->non_mem.end, pcie->outbound + PCIE_IN0_MEM_LIMIT); - writel_relaxed(pcie->non_mem.start, pcie->outbound + PCIE_POM0_MEM_ADDR); - - /* Set PCIeA mem1 region to be 2nd 16MB of the 64MB PCIeA window */ - writel_relaxed(pcie->pre_mem.start, pcie->outbound + PCIE_IN1_MEM_ADDR); - writel_relaxed(pcie->pre_mem.end, pcie->outbound + PCIE_IN1_MEM_LIMIT); - writel_relaxed(pcie->pre_mem.start, pcie->outbound + PCIE_POM1_MEM_ADDR); - - /* Set PCIeA io to be third 16M region of the 64MB PCIeA window*/ - writel_relaxed(pcie->io.start, pcie->outbound + PCIE_IN_IO_ADDR); - writel_relaxed(pcie->io.end, pcie->outbound + PCIE_IN_IO_LIMIT); - - /* Set PCIeA cgf0 to be last 16M region of the 64MB PCIeA window*/ - writel_relaxed(pcie->cfg.start, pcie->outbound + PCIE_IN_CFG0_ADDR); - writel_relaxed(pcie->cfg.end, pcie->outbound + PCIE_IN_CFG0_LIMIT); - wmb(); - - /* Enable outbound address translation */ - oxnas_register_set_mask(pcie->pcie_ctrl, PCIE_OBTRANS); - wmb(); - - /* - * Program PCIe command register for core to: - * enable memory space - * enable bus master - * enable io - */ - writel_relaxed(7, pcie->base + PCI_CONFIG_COMMAND_STATUS); - /* which is which */ - wmb(); -} - -static unsigned oxnas_pcie_cfg_to_offset( - struct pci_sys_data *sys, - unsigned char bus_number, - unsigned int devfn, - int where) -{ - unsigned int function = PCI_FUNC(devfn); - unsigned int slot = PCI_SLOT(devfn); - unsigned char bus_number_offset; - - bus_number_offset = bus_number - sys->busnr; - - /* - * We'll assume for now that the offset, function, slot, bus encoding - * should map onto linear, contiguous addresses in PCIe config space, - * albeit that the majority will be unused as only slot 0 is valid for - * any PCIe bus and most devices have only function 0 - * - * Could be that PCIe in fact works by not encoding the slot number into - * the config space address as it's known that only slot 0 is valid. - * We'll have to experiment if/when we get a PCIe switch connected to - * the PCIe host - */ - return (bus_number_offset << 20) | (slot << 15) | (function << 12) | - (where & ~3); -} - -/* PCI configuration space write function */ -static int oxnas_pcie_wr_conf(struct pci_bus *bus, u32 devfn, - int where, int size, u32 val) -{ - unsigned long flags; - struct oxnas_pcie *pcie = sys_to_pcie(bus->sysdata); - unsigned offset; - u32 value; - u32 lanes; - - /* Only a single device per bus for PCIe point-to-point links */ - if (PCI_SLOT(devfn) > 0) - return PCIBIOS_DEVICE_NOT_FOUND; - - if (!pcie->haslink) - return PCIBIOS_DEVICE_NOT_FOUND; - - offset = oxnas_pcie_cfg_to_offset(bus->sysdata, bus->number, devfn, - where); - - value = val << (8 * (where & 3)); - lanes = (0xf >> (4-size)) << (where & 3); - /* it race with mem and io write, but the possibility is low, normally - * all config writes happens at driver initialize stage, wont interleave - * with others. - * and many pcie cards use dword (4bytes) access mem/io access only, - * so not bother to copy that ugly work-around now. */ - spin_lock_irqsave(&pcie->lock, flags); - set_out_lanes(pcie, lanes); - writel_relaxed(value, pcie->cfgbase + offset); - set_out_lanes(pcie, 0xf); - spin_unlock_irqrestore(&pcie->lock, flags); - - return PCIBIOS_SUCCESSFUL; -} - -/* PCI configuration space read function */ -static int oxnas_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, - int size, u32 *val) -{ - struct oxnas_pcie *pcie = sys_to_pcie(bus->sysdata); - unsigned offset; - u32 value; - u32 left_bytes, right_bytes; - - /* Only a single device per bus for PCIe point-to-point links */ - if (PCI_SLOT(devfn) > 0) { - *val = 0xffffffff; - return PCIBIOS_DEVICE_NOT_FOUND; - } - - if (!pcie->haslink) { - *val = 0xffffffff; - return PCIBIOS_DEVICE_NOT_FOUND; - } - - offset = oxnas_pcie_cfg_to_offset(bus->sysdata, bus->number, devfn, - where); - value = readl_relaxed(pcie->cfgbase + offset); - left_bytes = where & 3; - right_bytes = 4 - left_bytes - size; - value <<= right_bytes * 8; - value >>= (left_bytes + right_bytes) * 8; - *val = value; - - return PCIBIOS_SUCCESSFUL; -} - -static struct pci_ops oxnas_pcie_ops = { - .read = oxnas_pcie_rd_conf, - .write = oxnas_pcie_wr_conf, -}; - -static int __init oxnas_pcie_setup(int nr, struct pci_sys_data *sys) -{ - struct oxnas_pcie *pcie = sys_to_pcie(sys); - - pci_add_resource_offset(&sys->resources, &pcie->non_mem, sys->mem_offset); - pci_add_resource_offset(&sys->resources, &pcie->pre_mem, sys->mem_offset); - pci_add_resource_offset(&sys->resources, &pcie->io, sys->io_offset); - pci_add_resource(&sys->resources, &pcie->busn); - if (sys->busnr == 0) { /* default one */ - sys->busnr = pcie->busn.start; - } - /* do not use devm_ioremap_resource, it does not like cfg resource */ - pcie->cfgbase = devm_ioremap(&pcie->pdev->dev, pcie->cfg.start, - resource_size(&pcie->cfg)); - if (!pcie->cfgbase) - return -ENOMEM; - - oxnas_pcie_setup_hw(pcie); - - return 1; -} - -static void __init oxnas_pcie_enable(struct device *dev, struct oxnas_pcie *pcie) -{ - struct hw_pci hw; - int i; - - memset(&hw, 0, sizeof(hw)); - for (i = 0; i < NUM_CONTROLLERS; i++) - pcie->private_data[i] = pcie; - - hw.nr_controllers = NUM_CONTROLLERS; -/* I think use stack pointer is a bad idea though it is valid in this case */ - hw.private_data = pcie->private_data; - hw.setup = oxnas_pcie_setup; - hw.map_irq = of_irq_parse_and_map_pci; - hw.ops = &oxnas_pcie_ops; - - /* pass dev to maintain of tree, interrupt mapping rely on this */ - pci_common_init_dev(dev, &hw); -} - -void oxnas_pcie_init_shared_hw(struct platform_device *pdev, - void __iomem *phybase) -{ - struct reset_control *rstc; - int ret; - - /* generate clocks from HCSL buffers, shared parts */ - writel(HCSL_BIAS_ON|HCSL_PCIE_EN, SYS_CTRL_HCSL_CTRL); - - /* Ensure PCIe PHY is properly reset */ - rstc = reset_control_get(&pdev->dev, "phy"); - if (IS_ERR(rstc)) { - ret = PTR_ERR(rstc); - } else { - ret = reset_control_reset(rstc); - reset_control_put(rstc); - } - - if (ret) { - dev_err(&pdev->dev, "phy reset failed %d\n", ret); - return; - } - - /* Enable PCIe Pre-Emphasis: What these value means? */ - - writel(ADDR_VAL(0x0014), phybase + PHY_ADDR); - writel(DATA_VAL(0xce10) | CAP_DATA, phybase + PHY_DATA); - writel(DATA_VAL(0xce10) | WRITE_EN, phybase + PHY_DATA); - - writel(ADDR_VAL(0x2004), phybase + PHY_ADDR); - writel(DATA_VAL(0x82c7) | CAP_DATA, phybase + PHY_DATA); - writel(DATA_VAL(0x82c7) | WRITE_EN, phybase + PHY_DATA); -} - -static int oxnas_pcie_shared_init(struct platform_device *pdev) -{ - if (++pcie_shared.refcount == 1) { - /* we are the first */ - struct device_node *np = pdev->dev.of_node; - void __iomem *phy = of_iomap(np, 2); - if (!phy) { - --pcie_shared.refcount; - return -ENOMEM; - } - oxnas_pcie_init_shared_hw(pdev, phy); - iounmap(phy); - return 0; - } else { - return 0; - } -} - -#if 0 -/* maybe we will call it when enter low power state */ -static void oxnas_pcie_shared_deinit(struct platform_device *pdev) -{ - if (--pcie_shared.refcount == 0) { - /* no cleanup needed */; - } -} -#endif - -static int __init -oxnas_pcie_map_registers(struct platform_device *pdev, - struct device_node *np, - struct oxnas_pcie *pcie) -{ - struct resource regs; - int ret = 0; - u32 outbound_ctrl_offset; - u32 pcie_ctrl_offset; - - /* 2 is reserved for shared phy */ - ret = of_address_to_resource(np, 0, ®s); - if (ret) - return -EINVAL; - pcie->base = devm_ioremap_resource(&pdev->dev, ®s); - if (!pcie->base) - return -ENOMEM; - - ret = of_address_to_resource(np, 1, ®s); - if (ret) - return -EINVAL; - pcie->inbound = devm_ioremap_resource(&pdev->dev, ®s); - if (!pcie->inbound) - return -ENOMEM; - - - if (of_property_read_u32(np, "plxtech,pcie-outbound-offset", - &outbound_ctrl_offset)) - return -EINVAL; - /* SYSCRTL is shared by too many drivers, so is mapped by board file */ - pcie->outbound = IOMEM(OXNAS_SYSCRTL_BASE_VA + outbound_ctrl_offset); - - if (of_property_read_u32(np, "plxtech,pcie-ctrl-offset", - &pcie_ctrl_offset)) - return -EINVAL; - pcie->pcie_ctrl = IOMEM(OXNAS_SYSCRTL_BASE_VA + pcie_ctrl_offset); - - return 0; -} - -static int __init oxnas_pcie_init_res(struct platform_device *pdev, - struct oxnas_pcie *pcie, - struct device_node *np) -{ - struct of_pci_range range; - struct of_pci_range_parser parser; - int ret; - - if (of_pci_range_parser_init(&parser, np)) - return -EINVAL; - - /* Get the I/O and memory ranges from DT */ - for_each_of_pci_range(&parser, &range) { - - unsigned long restype = range.flags & IORESOURCE_TYPE_BITS; - if (restype == IORESOURCE_IO) { - of_pci_range_to_resource(&range, np, &pcie->io); - pcie->io.name = "I/O"; - } - if (restype == IORESOURCE_MEM) { - if (range.flags & IORESOURCE_PREFETCH) { - of_pci_range_to_resource(&range, np, &pcie->pre_mem); - pcie->pre_mem.name = "PRE MEM"; - } else { - of_pci_range_to_resource(&range, np, &pcie->non_mem); - pcie->non_mem.name = "NON MEM"; - } - - } - if (restype == 0) - of_pci_range_to_resource(&range, np, &pcie->cfg); - } - - /* Get the bus range */ - ret = of_pci_parse_bus_range(np, &pcie->busn); - - if (ret) { - dev_err(&pdev->dev, "failed to parse bus-range property: %d\n", - ret); - return ret; - } - - pcie->card_reset = of_get_gpio(np, 0); - if (pcie->card_reset < 0) - dev_info(&pdev->dev, "card reset gpio pin not exists\n"); - - if (of_property_read_u32(np, "plxtech,pcie-hcsl-bit", &pcie->hcsl_en)) - return -EINVAL; - - pcie->clk = of_clk_get_by_name(np, "pcie"); - if (IS_ERR(pcie->clk)) { - return PTR_ERR(pcie->clk); - } - - pcie->busclk = of_clk_get_by_name(np, "busclk"); - if (IS_ERR(pcie->busclk)) { - clk_put(pcie->clk); - return PTR_ERR(pcie->busclk); - } - - return 0; -} - -static void oxnas_pcie_init_hw(struct platform_device *pdev, - struct oxnas_pcie *pcie) -{ - u32 version_id; - int ret; - - clk_prepare_enable(pcie->busclk); - - /* reset PCIe cards use hard-wired gpio pin */ - if (pcie->card_reset >= 0 && - !gpio_direction_output(pcie->card_reset, 0)) { - wmb(); - mdelay(10); - /* must tri-state the pin to pull it up */ - gpio_direction_input(pcie->card_reset); - wmb(); - mdelay(100); - } - - oxnas_register_set_mask(SYS_CTRL_HCSL_CTRL, BIT(pcie->hcsl_en)); - - /* core */ - ret = device_reset(&pdev->dev); - if (ret) { - dev_err(&pdev->dev, "core reset failed %d\n", ret); - return; - } - - /* Start PCIe core clocks */ - clk_prepare_enable(pcie->clk); - - version_id = readl_relaxed(pcie->base + PCI_CONFIG_VERSION_DEVICEID); - dev_info(&pdev->dev, "PCIe version/deviceID 0x%x\n", version_id); - - if (version_id != VERSION_ID_MAGIC) { - dev_info(&pdev->dev, "PCIe controller not found\n"); - pcie->haslink = 0; - return; - } - - /* allow entry to L23 state */ - oxnas_register_set_mask(pcie->pcie_ctrl, PCIE_READY_ENTR_L23); - - /* Set PCIe core into RootCore mode */ - oxnas_register_value_mask(pcie->pcie_ctrl, PCIE_DEVICE_TYPE_MASK, - PCIE_DEVICE_TYPE_ROOT); - wmb(); - - /* Bring up the PCI core */ - oxnas_register_set_mask(pcie->pcie_ctrl, PCIE_LTSSM); - wmb(); -} - -static int __init oxnas_pcie_probe(struct platform_device *pdev) -{ - struct oxnas_pcie *pcie; - struct device_node *np = pdev->dev.of_node; - int ret; - - pcie = devm_kzalloc(&pdev->dev, sizeof(struct oxnas_pcie), - GFP_KERNEL); - if (!pcie) - return -ENOMEM; - - pcie->pdev = pdev; - pcie->haslink = 1; - spin_lock_init(&pcie->lock); - - ret = oxnas_pcie_init_res(pdev, pcie, np); - if (ret) - return ret; - if (pcie->card_reset >= 0) { - ret = gpio_request_one(pcie->card_reset, GPIOF_DIR_IN, - dev_name(&pdev->dev)); - if (ret) { - dev_err(&pdev->dev, "cannot request gpio pin %d\n", - pcie->card_reset); - return ret; - } - } - - ret = oxnas_pcie_map_registers(pdev, np, pcie); - if (ret) { - dev_err(&pdev->dev, "cannot map registers\n"); - goto err_free_gpio; - } - - ret = oxnas_pcie_shared_init(pdev); - if (ret) - goto err_free_gpio; - - /* if hw not found, haslink cleared */ - oxnas_pcie_init_hw(pdev, pcie); - - if (pcie->haslink && oxnas_pcie_link_up(pcie)) { - pcie->haslink = 1; - dev_info(&pdev->dev, "link up\n"); - } else { - pcie->haslink = 0; - dev_info(&pdev->dev, "link down\n"); - } - /* should we register our controller even when pcie->haslink is 0 ? */ - /* register the controller with framework */ - oxnas_pcie_enable(&pdev->dev, pcie); - - return 0; - -err_free_gpio: - if (pcie->card_reset) - gpio_free(pcie->card_reset); - - return ret; -} - -static const struct of_device_id oxnas_pcie_of_match_table[] = { - { .compatible = "plxtech,nas782x-pcie", }, - {}, -}; -MODULE_DEVICE_TABLE(of, oxnas_pcie_of_match_table); - -static struct platform_driver oxnas_pcie_driver = { - .driver = { - .owner = THIS_MODULE, - .name = "oxnas-pcie", - .of_match_table = - of_match_ptr(oxnas_pcie_of_match_table), - }, -}; - -static int __init oxnas_pcie_init(void) -{ - return platform_driver_probe(&oxnas_pcie_driver, - oxnas_pcie_probe); -} - -subsys_initcall(oxnas_pcie_init); - -MODULE_AUTHOR("Ma Haijun <mahaijuns@gmail.com>"); -MODULE_DESCRIPTION("NAS782x PCIe driver"); -MODULE_LICENSE("GPLv2"); diff --git a/target/linux/oxnas/files/drivers/pinctrl/pinctrl-oxnas.c b/target/linux/oxnas/files/drivers/pinctrl/pinctrl-oxnas.c deleted file mode 100644 index 38a8cbb451..0000000000 --- a/target/linux/oxnas/files/drivers/pinctrl/pinctrl-oxnas.c +++ /dev/null @@ -1,1461 +0,0 @@ -/* - * oxnas pinctrl driver based on at91 pinctrl driver - * - * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * Under GPLv2 only - */ -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/init.h> -#include <linux/module.h> -#include <linux/of.h> -#include <linux/of_device.h> -#include <linux/of_address.h> -#include <linux/of_irq.h> -#include <linux/slab.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/irqdomain.h> -#include <linux/irqchip/chained_irq.h> -#include <linux/io.h> -#include <linux/gpio.h> -#include <linux/pinctrl/machine.h> -#include <linux/pinctrl/pinconf.h> -#include <linux/pinctrl/pinctrl.h> -#include <linux/pinctrl/pinmux.h> -/* Since we request GPIOs from ourself */ -#include <linux/pinctrl/consumer.h> -#include <linux/spinlock.h> - -#include "core.h" - -#include <mach/utils.h> - -#define MAX_NB_GPIO_PER_BANK 32 -#define MAX_GPIO_BANKS 2 - -struct oxnas_gpio_chip { - struct gpio_chip chip; - struct pinctrl_gpio_range range; - void __iomem *regbase; /* GPIOA/B virtual address */ - void __iomem *ctrlbase; /* SYS/SEC_CTRL virtual address */ - struct irq_domain *domain; /* associated irq domain */ - spinlock_t lock; -}; - -#define to_oxnas_gpio_chip(c) container_of(c, struct oxnas_gpio_chip, chip) - -static struct oxnas_gpio_chip *gpio_chips[MAX_GPIO_BANKS]; - -static int gpio_banks; - -#define PULL_UP (1 << 0) -#define PULL_DOWN (1 << 1) -#define DEBOUNCE (1 << 2) - -/** - * struct oxnas_pmx_func - describes pinmux functions - * @name: the name of this specific function - * @groups: corresponding pin groups - * @ngroups: the number of groups - */ -struct oxnas_pmx_func { - const char *name; - const char **groups; - unsigned ngroups; -}; - -enum oxnas_mux { - OXNAS_PINMUX_GPIO, - OXNAS_PINMUX_FUNC2, - OXNAS_PINMUX_FUNC3, - OXNAS_PINMUX_FUNC4, - OXNAS_PINMUX_DEBUG, - OXNAS_PINMUX_ALT, -}; - -enum { - INPUT_VALUE = 0, - OUTPUT_ENABLE = 4, - IRQ_PENDING = 0xC, - OUTPUT_VALUE = 0x10, - OUTPUT_SET = 0x14, - OUTPUT_CLEAR = 0x18, - OUTPUT_EN_SET = 0x1C, - OUTPUT_EN_CLEAR = 0x20, - DEBOUNCE_ENABLE = 0x24, - RE_IRQ_ENABLE = 0x28, /* rising edge */ - FE_IRQ_ENABLE = 0x2C, /* falling edge */ - RE_IRQ_PENDING = 0x30, /* rising edge */ - FE_IRQ_PENDING = 0x34, /* falling edge */ - CLOCK_DIV = 0x48, - PULL_ENABLE = 0x50, - PULL_SENSE = 0x54, /* 1 up, 0 down */ - - - DEBOUNCE_MASK = 0x3FFF0000, - /* put hw debounce and soft config at same bit position*/ - DEBOUNCE_SHIFT = 16 -}; - -enum { - PINMUX_SECONDARY_SEL = 0x14, - PINMUX_TERTIARY_SEL = 0x8c, - PINMUX_QUATERNARY_SEL = 0x94, - PINMUX_DEBUG_SEL = 0x9c, - PINMUX_ALTERNATIVE_SEL = 0xa4, - PINMUX_PULLUP_SEL = 0xac, -}; - -/** - * struct oxnas_pmx_pin - describes an pin mux - * @bank: the bank of the pin - * @pin: the pin number in the @bank - * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function. - * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc... - */ -struct oxnas_pmx_pin { - uint32_t bank; - uint32_t pin; - enum oxnas_mux mux; - unsigned long conf; -}; - -/** - * struct oxnas_pin_group - describes an pin group - * @name: the name of this specific pin group - * @pins_conf: the mux mode for each pin in this group. The size of this - * array is the same as pins. - * @pins: an array of discrete physical pins used in this group, taken - * from the driver-local pin enumeration space - * @npins: the number of pins in this group array, i.e. the number of - * elements in .pins so we can iterate over that array - */ -struct oxnas_pin_group { - const char *name; - struct oxnas_pmx_pin *pins_conf; - unsigned int *pins; - unsigned npins; -}; - -struct oxnas_pinctrl { - struct device *dev; - struct pinctrl_dev *pctl; - - int nbanks; - - uint32_t *mux_mask; - int nmux; - - struct oxnas_pmx_func *functions; - int nfunctions; - - struct oxnas_pin_group *groups; - int ngroups; -}; - -static const inline struct oxnas_pin_group *oxnas_pinctrl_find_group_by_name( - const struct oxnas_pinctrl *info, - const char *name) -{ - const struct oxnas_pin_group *grp = NULL; - int i; - - for (i = 0; i < info->ngroups; i++) { - if (strcmp(info->groups[i].name, name)) - continue; - - grp = &info->groups[i]; - dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, - grp->pins[0]); - break; - } - - return grp; -} - -static int oxnas_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); - - return info->ngroups; -} - -static const char *oxnas_get_group_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); - - return info->groups[selector].name; -} - -static int oxnas_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, - const unsigned **pins, - unsigned *npins) -{ - struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); - - if (selector >= info->ngroups) - return -EINVAL; - - *pins = info->groups[selector].pins; - *npins = info->groups[selector].npins; - - return 0; -} - -static void oxnas_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, - unsigned offset) -{ - seq_printf(s, "%s", dev_name(pctldev->dev)); -} - -static int oxnas_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np, - struct pinctrl_map **map, unsigned *num_maps) -{ - struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); - const struct oxnas_pin_group *grp; - struct pinctrl_map *new_map; - struct device_node *parent; - int map_num = 1; - int i; - - /* - * first find the group of this node and check if we need create - * config maps for pins - */ - grp = oxnas_pinctrl_find_group_by_name(info, np->name); - if (!grp) { - dev_err(info->dev, "unable to find group for node %s\n", - np->name); - return -EINVAL; - } - - map_num += grp->npins; - new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, - GFP_KERNEL); - if (!new_map) - return -ENOMEM; - - *map = new_map; - *num_maps = map_num; - - /* create mux map */ - parent = of_get_parent(np); - if (!parent) { - devm_kfree(pctldev->dev, new_map); - return -EINVAL; - } - new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; - new_map[0].data.mux.function = parent->name; - new_map[0].data.mux.group = np->name; - of_node_put(parent); - - /* create config map */ - new_map++; - for (i = 0; i < grp->npins; i++) { - new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; - new_map[i].data.configs.group_or_pin = - pin_get_name(pctldev, grp->pins[i]); - new_map[i].data.configs.configs = &grp->pins_conf[i].conf; - new_map[i].data.configs.num_configs = 1; - } - - dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", - (*map)->data.mux.function, (*map)->data.mux.group, map_num); - - return 0; -} - -static void oxnas_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, unsigned num_maps) -{ -} - -static const struct pinctrl_ops oxnas_pctrl_ops = { - .get_groups_count = oxnas_get_groups_count, - .get_group_name = oxnas_get_group_name, - .get_group_pins = oxnas_get_group_pins, - .pin_dbg_show = oxnas_pin_dbg_show, - .dt_node_to_map = oxnas_dt_node_to_map, - .dt_free_map = oxnas_dt_free_map, -}; - -static void __iomem *pin_to_gpioctrl(struct oxnas_pinctrl *info, - unsigned int bank) -{ - return gpio_chips[bank]->regbase; -} - -static void __iomem *pin_to_muxctrl(struct oxnas_pinctrl *info, - unsigned int bank) -{ - return gpio_chips[bank]->ctrlbase; -} - - -static inline int pin_to_bank(unsigned pin) -{ - return pin / MAX_NB_GPIO_PER_BANK; -} - -static unsigned pin_to_mask(unsigned int pin) -{ - return 1 << pin; -} - -static void oxnas_mux_disable_interrupt(void __iomem *pio, unsigned mask) -{ - oxnas_register_clear_mask(pio + RE_IRQ_ENABLE, mask); - oxnas_register_clear_mask(pio + FE_IRQ_ENABLE, mask); -} - -static unsigned oxnas_mux_get_pullup(void __iomem *pio, unsigned pin) -{ - return (readl_relaxed(pio + PULL_ENABLE) & BIT(pin)) && - (readl_relaxed(pio + PULL_SENSE) & BIT(pin)); -} - -static void oxnas_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) -{ - if (on) { - oxnas_register_set_mask(pio + PULL_SENSE, mask); - oxnas_register_set_mask(pio + PULL_ENABLE, mask); - } else { - oxnas_register_clear_mask(pio + PULL_ENABLE, mask); - } -} - -static bool oxnas_mux_get_pulldown(void __iomem *pio, unsigned pin) -{ - return (readl_relaxed(pio + PULL_ENABLE) & BIT(pin)) && - (!(readl_relaxed(pio + PULL_SENSE) & BIT(pin))); -} - -static void oxnas_mux_set_pulldown(void __iomem *pio, unsigned mask, bool on) -{ - if (on) { - oxnas_register_clear_mask(pio + PULL_SENSE, mask); - oxnas_register_set_mask(pio + PULL_ENABLE, mask); - } else { - oxnas_register_clear_mask(pio + PULL_ENABLE, mask); - }; -} - -/* unfortunately debounce control are shared */ -static bool oxnas_mux_get_debounce(void __iomem *pio, unsigned pin, u32 *div) -{ - *div = __raw_readl(pio + CLOCK_DIV) & DEBOUNCE_MASK; - return __raw_readl(pio + DEBOUNCE_ENABLE) & BIT(pin); -} - -static void oxnas_mux_set_debounce(void __iomem *pio, unsigned mask, - bool is_on, u32 div) -{ - if (is_on) { - oxnas_register_value_mask(pio + CLOCK_DIV, DEBOUNCE_MASK, div); - oxnas_register_set_mask(pio + DEBOUNCE_ENABLE, mask); - } else { - oxnas_register_clear_mask(pio + DEBOUNCE_ENABLE, mask); - } -} - - -static void oxnas_mux_set_func2(void __iomem *cio, unsigned mask) -{ -/* in fact, SECONDARY takes precedence, so clear others is not necessary */ - oxnas_register_set_mask(cio + PINMUX_SECONDARY_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask); -} - -static void oxnas_mux_set_func3(void __iomem *cio, unsigned mask) -{ - oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask); - oxnas_register_set_mask(cio + PINMUX_TERTIARY_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask); -} - -static void oxnas_mux_set_func4(void __iomem *cio, unsigned mask) -{ - oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask); - oxnas_register_set_mask(cio + PINMUX_QUATERNARY_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask); -} - -static void oxnas_mux_set_func_dbg(void __iomem *cio, unsigned mask) -{ - oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask); - oxnas_register_set_mask(cio + PINMUX_DEBUG_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask); -} - -static void oxnas_mux_set_func_alt(void __iomem *cio, unsigned mask) -{ - oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask); - oxnas_register_set_mask(cio + PINMUX_ALTERNATIVE_SEL, mask); -} - -static void oxnas_mux_set_gpio(void __iomem *cio, unsigned mask) -{ - oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask); -} - -static enum oxnas_mux oxnas_mux_get_func(void __iomem *cio, unsigned mask) -{ - if (readl_relaxed(cio + PINMUX_SECONDARY_SEL) & mask) - return OXNAS_PINMUX_FUNC2; - if (readl_relaxed(cio + PINMUX_TERTIARY_SEL) & mask) - return OXNAS_PINMUX_FUNC3; - if (readl_relaxed(cio + PINMUX_QUATERNARY_SEL) & mask) - return OXNAS_PINMUX_FUNC4; - if (readl_relaxed(cio + PINMUX_DEBUG_SEL) & mask) - return OXNAS_PINMUX_DEBUG; - if (readl_relaxed(cio + PINMUX_ALTERNATIVE_SEL) & mask) - return OXNAS_PINMUX_ALT; - return OXNAS_PINMUX_GPIO; -} - - -static void oxnas_pin_dbg(const struct device *dev, - const struct oxnas_pmx_pin *pin) -{ - if (pin->mux) { - dev_dbg(dev, - "MF_%c%d configured as periph%c with conf = 0x%lu\n", - pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', - pin->conf); - } else { - dev_dbg(dev, "MF_%c%d configured as gpio with conf = 0x%lu\n", - pin->bank + 'A', pin->pin, pin->conf); - } -} - -static int pin_check_config(struct oxnas_pinctrl *info, const char *name, - int index, const struct oxnas_pmx_pin *pin) -{ - int mux; - - /* check if it's a valid config */ - if (pin->bank >= info->nbanks) { - dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n", - name, index, pin->bank, info->nbanks); - return -EINVAL; - } - - if (pin->pin >= MAX_NB_GPIO_PER_BANK) { - dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n", - name, index, pin->pin, MAX_NB_GPIO_PER_BANK); - return -EINVAL; - } - /* gpio always allowed */ - if (!pin->mux) - return 0; - - mux = pin->mux - 1; - - if (mux >= info->nmux) { - dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n", - name, index, mux, info->nmux); - return -EINVAL; - } - - if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) { - dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for MF_%c%d\n", - name, index, mux, pin->bank + 'A', pin->pin); - return -EINVAL; - } - - return 0; -} - -static void oxnas_mux_gpio_enable(void __iomem *cio, void __iomem *pio, - unsigned mask, bool input) -{ - oxnas_mux_set_gpio(cio, mask); - if (input) - writel_relaxed(mask, pio + OUTPUT_EN_CLEAR); - else - writel_relaxed(mask, pio + OUTPUT_EN_SET); -} - -static void oxnas_mux_gpio_disable(void __iomem *cio, void __iomem *pio, - unsigned mask) -{ - /* when switch to other function, gpio is disabled automatically */ - return; -} - -static int oxnas_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group) -{ - struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); - const struct oxnas_pmx_pin *pins_conf = info->groups[group].pins_conf; - const struct oxnas_pmx_pin *pin; - uint32_t npins = info->groups[group].npins; - int i, ret; - unsigned mask; - void __iomem *pio; - void __iomem *cio; - - dev_dbg(info->dev, "enable function %s group %s\n", - info->functions[selector].name, info->groups[group].name); - - /* first check that all the pins of the group are valid with a valid - * paramter */ - for (i = 0; i < npins; i++) { - pin = &pins_conf[i]; - ret = pin_check_config(info, info->groups[group].name, i, pin); - if (ret) - return ret; - } - - for (i = 0; i < npins; i++) { - pin = &pins_conf[i]; - oxnas_pin_dbg(info->dev, pin); - - pio = pin_to_gpioctrl(info, pin->bank); - cio = pin_to_muxctrl(info, pin->bank); - - mask = pin_to_mask(pin->pin); - oxnas_mux_disable_interrupt(pio, mask); - - switch (pin->mux) { - case OXNAS_PINMUX_GPIO: - oxnas_mux_gpio_enable(cio, pio, mask, 1); - break; - case OXNAS_PINMUX_FUNC2: - oxnas_mux_set_func2(cio, mask); - break; - case OXNAS_PINMUX_FUNC3: - oxnas_mux_set_func3(cio, mask); - break; - case OXNAS_PINMUX_FUNC4: - oxnas_mux_set_func4(cio, mask); - break; - case OXNAS_PINMUX_DEBUG: - oxnas_mux_set_func_dbg(cio, mask); - break; - case OXNAS_PINMUX_ALT: - oxnas_mux_set_func_alt(cio, mask); - break; - } - if (pin->mux) - oxnas_mux_gpio_disable(cio, pio, mask); - } - - return 0; -} - -static int oxnas_pmx_get_funcs_count(struct pinctrl_dev *pctldev) -{ - struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); - - return info->nfunctions; -} - -static const char *oxnas_pmx_get_func_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); - - return info->functions[selector].name; -} - -static int oxnas_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, - const char * const **groups, - unsigned * const num_groups) -{ - struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); - - *groups = info->functions[selector].groups; - *num_groups = info->functions[selector].ngroups; - - return 0; -} - -static int oxnas_gpio_request_enable(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned offset) -{ - struct oxnas_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - struct oxnas_gpio_chip *oxnas_chip; - struct gpio_chip *chip; - unsigned mask; - - if (!range) { - dev_err(npct->dev, "invalid range\n"); - return -EINVAL; - } - if (!range->gc) { - dev_err(npct->dev, "missing GPIO chip in range\n"); - return -EINVAL; - } - chip = range->gc; - oxnas_chip = container_of(chip, struct oxnas_gpio_chip, chip); - - dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); - - mask = 1 << (offset - chip->base); - - dev_dbg(npct->dev, "enable pin %u as MF_%c%d 0x%x\n", - offset, 'A' + range->id, offset - chip->base, mask); - - oxnas_mux_set_gpio(oxnas_chip->ctrlbase, mask); - - return 0; -} - -static void oxnas_gpio_disable_free(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned offset) -{ - struct oxnas_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - - dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); - /* Set the pin to some default state, GPIO is usually default */ -} - -static const struct pinmux_ops oxnas_pmx_ops = { - .get_functions_count = oxnas_pmx_get_funcs_count, - .get_function_name = oxnas_pmx_get_func_name, - .get_function_groups = oxnas_pmx_get_groups, - .set_mux = oxnas_pmx_set_mux, - .gpio_request_enable = oxnas_gpio_request_enable, - .gpio_disable_free = oxnas_gpio_disable_free, -}; - -static int oxnas_pinconf_get(struct pinctrl_dev *pctldev, - unsigned pin_id, unsigned long *config) -{ - struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); - void __iomem *pio; - unsigned pin; - int div; - - dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, - __LINE__, pin_id, *config); - pio = pin_to_gpioctrl(info, pin_to_bank(pin_id)); - pin = pin_id % MAX_NB_GPIO_PER_BANK; - - if (oxnas_mux_get_pullup(pio, pin)) - *config |= PULL_UP; - - if (oxnas_mux_get_pulldown(pio, pin)) - *config |= PULL_DOWN; - - if (oxnas_mux_get_debounce(pio, pin, &div)) - *config |= DEBOUNCE | div; - return 0; -} - -static int oxnas_pinconf_set(struct pinctrl_dev *pctldev, - unsigned pin_id, unsigned long *configs, - unsigned num_configs) -{ - struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); - unsigned mask; - void __iomem *pio; - int i; - unsigned long config; - - pio = pin_to_gpioctrl(info, pin_to_bank(pin_id)); - mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK); - - for (i = 0; i < num_configs; i++) { - config = configs[i]; - - dev_dbg(info->dev, - "%s:%d, pin_id=%d, config=0x%lx", - __func__, __LINE__, pin_id, config); - - if ((config & PULL_UP) && (config & PULL_DOWN)) - return -EINVAL; - - oxnas_mux_set_pullup(pio, mask, config & PULL_UP); - oxnas_mux_set_pulldown(pio, mask, config & PULL_DOWN); - oxnas_mux_set_debounce(pio, mask, config & DEBOUNCE, - config & DEBOUNCE_MASK); - - } /* for each config */ - - return 0; -} - -static void oxnas_pinconf_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned pin_id) -{ - -} - -static void oxnas_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned group) -{ -} - -static const struct pinconf_ops oxnas_pinconf_ops = { - .pin_config_get = oxnas_pinconf_get, - .pin_config_set = oxnas_pinconf_set, - .pin_config_dbg_show = oxnas_pinconf_dbg_show, - .pin_config_group_dbg_show = oxnas_pinconf_group_dbg_show, -}; - -static struct pinctrl_desc oxnas_pinctrl_desc = { - .pctlops = &oxnas_pctrl_ops, - .pmxops = &oxnas_pmx_ops, - .confops = &oxnas_pinconf_ops, - .owner = THIS_MODULE, -}; - -static const char *gpio_compat = "plxtech,nas782x-gpio"; - -static void oxnas_pinctrl_child_count(struct oxnas_pinctrl *info, - struct device_node *np) -{ - struct device_node *child; - - for_each_child_of_node(np, child) { - if (of_device_is_compatible(child, gpio_compat)) { - info->nbanks++; - } else { - info->nfunctions++; - info->ngroups += of_get_child_count(child); - } - } -} - -static int oxnas_pinctrl_mux_mask(struct oxnas_pinctrl *info, - struct device_node *np) -{ - int ret = 0; - int size; - const __be32 *list; - - list = of_get_property(np, "plxtech,mux-mask", &size); - if (!list) { - dev_err(info->dev, "can not read the mux-mask of %d\n", size); - return -EINVAL; - } - - size /= sizeof(*list); - if (!size || size % info->nbanks) { - dev_err(info->dev, "wrong mux mask array should be by %d\n", - info->nbanks); - return -EINVAL; - } - info->nmux = size / info->nbanks; - - info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL); - if (!info->mux_mask) { - dev_err(info->dev, "could not alloc mux_mask\n"); - return -ENOMEM; - } - - ret = of_property_read_u32_array(np, "plxtech,mux-mask", - info->mux_mask, size); - if (ret) - dev_err(info->dev, "can not read the mux-mask of %d\n", size); - return ret; -} - -static int oxnas_pinctrl_parse_groups(struct device_node *np, - struct oxnas_pin_group *grp, - struct oxnas_pinctrl *info, u32 index) -{ - struct oxnas_pmx_pin *pin; - int size; - const __be32 *list; - int i, j; - - dev_dbg(info->dev, "group(%d): %s\n", index, np->name); - - /* Initialise group */ - grp->name = np->name; - - /* - * the binding format is plxtech,pins = <bank pin mux CONFIG ...>, - * do sanity check and calculate pins number - */ - list = of_get_property(np, "plxtech,pins", &size); - /* we do not check return since it's safe node passed down */ - size /= sizeof(*list); - if (!size || size % 4) { - dev_err(info->dev, "wrong pins number or pins and configs" - " should be divisible by 4\n"); - return -EINVAL; - } - - grp->npins = size / 4; - pin = grp->pins_conf = devm_kzalloc(info->dev, - grp->npins * sizeof(struct oxnas_pmx_pin), - GFP_KERNEL); - grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), - GFP_KERNEL); - if (!grp->pins_conf || !grp->pins) - return -ENOMEM; - - for (i = 0, j = 0; i < size; i += 4, j++) { - pin->bank = be32_to_cpu(*list++); - pin->pin = be32_to_cpu(*list++); - grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin; - pin->mux = be32_to_cpu(*list++); - pin->conf = be32_to_cpu(*list++); - - oxnas_pin_dbg(info->dev, pin); - pin++; - } - - return 0; -} - -static int oxnas_pinctrl_parse_functions(struct device_node *np, - struct oxnas_pinctrl *info, u32 index) -{ - struct device_node *child; - struct oxnas_pmx_func *func; - struct oxnas_pin_group *grp; - int ret; - static u32 grp_index; - u32 i = 0; - - dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); - - func = &info->functions[index]; - - /* Initialise function */ - func->name = np->name; - func->ngroups = of_get_child_count(np); - if (func->ngroups <= 0) { - dev_err(info->dev, "no groups defined\n"); - return -EINVAL; - } - func->groups = devm_kzalloc(info->dev, - func->ngroups * sizeof(char *), GFP_KERNEL); - if (!func->groups) - return -ENOMEM; - - for_each_child_of_node(np, child) { - func->groups[i] = child->name; - grp = &info->groups[grp_index++]; - ret = oxnas_pinctrl_parse_groups(child, grp, info, i++); - if (ret) - return ret; - } - - return 0; -} - -static struct of_device_id oxnas_pinctrl_of_match[] = { - { .compatible = "plxtech,nas782x-pinctrl"}, - { /* sentinel */ } -}; - -static int oxnas_pinctrl_probe_dt(struct platform_device *pdev, - struct oxnas_pinctrl *info) -{ - int ret = 0; - int i, j; - uint32_t *tmp; - struct device_node *np = pdev->dev.of_node; - struct device_node *child; - - if (!np) - return -ENODEV; - - info->dev = &pdev->dev; - - oxnas_pinctrl_child_count(info, np); - - if (info->nbanks < 1) { - dev_err(&pdev->dev, "you need to specify atleast one gpio-controller\n"); - return -EINVAL; - } - - ret = oxnas_pinctrl_mux_mask(info, np); - if (ret) - return ret; - - dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux); - - dev_dbg(&pdev->dev, "mux-mask\n"); - tmp = info->mux_mask; - for (i = 0; i < info->nbanks; i++) - for (j = 0; j < info->nmux; j++, tmp++) - dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]); - - dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); - dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); - info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * - sizeof(struct oxnas_pmx_func), - GFP_KERNEL); - if (!info->functions) - return -ENOMEM; - - info->groups = devm_kzalloc(&pdev->dev, info->ngroups * - sizeof(struct oxnas_pin_group), - GFP_KERNEL); - if (!info->groups) - return -ENOMEM; - - dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks); - dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); - dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); - - i = 0; - - for_each_child_of_node(np, child) { - if (of_device_is_compatible(child, gpio_compat)) - continue; - ret = oxnas_pinctrl_parse_functions(child, info, i++); - if (ret) { - dev_err(&pdev->dev, "failed to parse function\n"); - return ret; - } - } - - return 0; -} - -static int oxnas_pinctrl_probe(struct platform_device *pdev) -{ - struct oxnas_pinctrl *info; - struct pinctrl_pin_desc *pdesc; - int ret, i, j, k; - - info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); - if (!info) - return -ENOMEM; - - ret = oxnas_pinctrl_probe_dt(pdev, info); - if (ret) - return ret; - - /* - * We need all the GPIO drivers to probe FIRST, or we will not be able - * to obtain references to the struct gpio_chip * for them, and we - * need this to proceed. - */ - for (i = 0; i < info->nbanks; i++) { - if (!gpio_chips[i]) { - dev_warn(&pdev->dev, - "GPIO chip %d not registered yet\n", i); - devm_kfree(&pdev->dev, info); - return -EPROBE_DEFER; - } - } - - oxnas_pinctrl_desc.name = dev_name(&pdev->dev); - oxnas_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK; - oxnas_pinctrl_desc.pins = pdesc = - devm_kzalloc(&pdev->dev, sizeof(*pdesc) * - oxnas_pinctrl_desc.npins, GFP_KERNEL); - - if (!oxnas_pinctrl_desc.pins) - return -ENOMEM; - - for (i = 0 , k = 0; i < info->nbanks; i++) { - for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) { - pdesc->number = k; - pdesc->name = kasprintf(GFP_KERNEL, "MF_%c%d", i + 'A', - j); - pdesc++; - } - } - - platform_set_drvdata(pdev, info); - info->pctl = pinctrl_register(&oxnas_pinctrl_desc, &pdev->dev, info); - - if (!info->pctl) { - dev_err(&pdev->dev, "could not register OX820 pinctrl driver\n"); - ret = -EINVAL; - goto err; - } - - /* We will handle a range of GPIO pins */ - for (i = 0; i < info->nbanks; i++) - pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range); - - dev_info(&pdev->dev, "initialized OX820 pinctrl driver\n"); - - return 0; - -err: - return ret; -} - -static int oxnas_pinctrl_remove(struct platform_device *pdev) -{ - struct oxnas_pinctrl *info = platform_get_drvdata(pdev); - - pinctrl_unregister(info->pctl); - - return 0; -} - -static int oxnas_gpio_request(struct gpio_chip *chip, unsigned offset) -{ - /* - * Map back to global GPIO space and request muxing, the direction - * parameter does not matter for this controller. - */ - int gpio = chip->base + offset; - int bank = chip->base / chip->ngpio; - - dev_dbg(chip->dev, "%s:%d MF_%c%d(%d)\n", __func__, __LINE__, - 'A' + bank, offset, gpio); - - return pinctrl_request_gpio(gpio); -} - -static void oxnas_gpio_free(struct gpio_chip *chip, unsigned offset) -{ - int gpio = chip->base + offset; - - pinctrl_free_gpio(gpio); -} - -static int oxnas_gpio_direction_input(struct gpio_chip *chip, unsigned offset) -{ - struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip); - void __iomem *pio = oxnas_gpio->regbase; - - writel_relaxed(BIT(offset), pio + OUTPUT_EN_CLEAR); - return 0; -} - -static int oxnas_gpio_get(struct gpio_chip *chip, unsigned offset) -{ - struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip); - void __iomem *pio = oxnas_gpio->regbase; - unsigned mask = 1 << offset; - u32 pdsr; - - pdsr = readl_relaxed(pio + INPUT_VALUE); - return (pdsr & mask) != 0; -} - -static void oxnas_gpio_set(struct gpio_chip *chip, unsigned offset, - int val) -{ - struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip); - void __iomem *pio = oxnas_gpio->regbase; - - if (val) - writel_relaxed(BIT(offset), pio + OUTPUT_SET); - else - writel_relaxed(BIT(offset), pio + OUTPUT_CLEAR); - -} - -static int oxnas_gpio_direction_output(struct gpio_chip *chip, unsigned offset, - int val) -{ - struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip); - void __iomem *pio = oxnas_gpio->regbase; - - if (val) - writel_relaxed(BIT(offset), pio + OUTPUT_SET); - else - writel_relaxed(BIT(offset), pio + OUTPUT_CLEAR); - - writel_relaxed(BIT(offset), pio + OUTPUT_EN_SET); - - return 0; -} - -static int oxnas_gpio_to_irq(struct gpio_chip *chip, unsigned offset) -{ - struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip); - int virq; - - if (offset < chip->ngpio) - virq = irq_create_mapping(oxnas_gpio->domain, offset); - else - virq = -ENXIO; - - dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n", - chip->label, offset + chip->base, virq); - return virq; -} - -#ifdef CONFIG_DEBUG_FS -static void oxnas_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) -{ - enum oxnas_mux mode; - int i; - struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip); - void __iomem *pio = oxnas_gpio->regbase; - void __iomem *cio = oxnas_gpio->ctrlbase; - - for (i = 0; i < chip->ngpio; i++) { - unsigned pin = chip->base + i; - unsigned mask = pin_to_mask(pin); - const char *gpio_label; - u32 pdsr; - - gpio_label = gpiochip_is_requested(chip, i); - if (!gpio_label) - continue; - /* FIXME */ - mode = oxnas_mux_get_func(cio, mask); - seq_printf(s, "[%s] GPIO%s%d: ", - gpio_label, chip->label, i); - if (mode == OXNAS_PINMUX_GPIO) { - pdsr = readl_relaxed(pio + INPUT_VALUE); - - seq_printf(s, "[gpio] %s\n", - pdsr & mask ? - "set" : "clear"); - } else { - seq_printf(s, "[periph %c]\n", - mode + 'A' - 1); - } - } -} -#else -#define oxnas_gpio_dbg_show NULL -#endif - -/* Several AIC controller irqs are dispatched through this GPIO handler. - * To use any AT91_PIN_* as an externally triggered IRQ, first call - * oxnas_set_gpio_input() then maybe enable its glitch filter. - * Then just request_irq() with the pin ID; it works like any ARM IRQ - * handler. - */ - -static void gpio_irq_mask(struct irq_data *d) -{ - struct oxnas_gpio_chip *oxnas_gpio = irq_data_get_irq_chip_data(d); - void __iomem *pio = oxnas_gpio->regbase; - unsigned mask = 1 << d->hwirq; - unsigned type = irqd_get_trigger_type(d); - unsigned long flags; - - if (!(type & IRQ_TYPE_EDGE_BOTH)) - return; - - spin_lock_irqsave(&oxnas_gpio->lock, flags); - if (type & IRQ_TYPE_EDGE_RISING) - oxnas_register_clear_mask(pio + RE_IRQ_ENABLE, mask); - if (type & IRQ_TYPE_EDGE_FALLING) - oxnas_register_clear_mask(pio + FE_IRQ_ENABLE, mask); - spin_unlock_irqrestore(&oxnas_gpio->lock, flags); -} - -static void gpio_irq_unmask(struct irq_data *d) -{ - struct oxnas_gpio_chip *oxnas_gpio = irq_data_get_irq_chip_data(d); - void __iomem *pio = oxnas_gpio->regbase; - unsigned mask = 1 << d->hwirq; - unsigned type = irqd_get_trigger_type(d); - unsigned long flags; - - if (!(type & IRQ_TYPE_EDGE_BOTH)) - return; - - spin_lock_irqsave(&oxnas_gpio->lock, flags); - if (type & IRQ_TYPE_EDGE_RISING) - oxnas_register_set_mask(pio + RE_IRQ_ENABLE, mask); - if (type & IRQ_TYPE_EDGE_FALLING) - oxnas_register_set_mask(pio + FE_IRQ_ENABLE, mask); - spin_unlock_irqrestore(&oxnas_gpio->lock, flags); -} - - -static int gpio_irq_type(struct irq_data *d, unsigned type) -{ - if ((type & IRQ_TYPE_EDGE_BOTH) == 0) { - pr_warn("OX820: Unsupported type for irq %d\n", - gpio_to_irq(d->irq)); - return -EINVAL; - } - /* seems no way to set trigger type without enable irq, so leave it to unmask time */ - - return 0; -} - -static struct irq_chip gpio_irqchip = { - .name = "GPIO", - .irq_disable = gpio_irq_mask, - .irq_mask = gpio_irq_mask, - .irq_unmask = gpio_irq_unmask, - .irq_set_type = gpio_irq_type, -}; - -static void gpio_irq_handler(struct irq_desc *desc) -{ - struct irq_chip *chip = irq_desc_get_chip(desc); - struct irq_data *idata = irq_desc_get_irq_data(desc); - struct oxnas_gpio_chip *oxnas_gpio = irq_data_get_irq_chip_data(idata); - void __iomem *pio = oxnas_gpio->regbase; - unsigned long isr; - int n; - - chained_irq_enter(chip, desc); - for (;;) { - /* TODO: see if it works */ - isr = readl_relaxed(pio + IRQ_PENDING); - if (!isr) - break; - /* acks pending interrupts */ - writel_relaxed(isr, pio + IRQ_PENDING); - - for_each_set_bit(n, &isr, BITS_PER_LONG) { - generic_handle_irq(irq_find_mapping(oxnas_gpio->domain, - n)); - } - } - chained_irq_exit(chip, desc); - /* now it may re-trigger */ -} - -/* - * This lock class tells lockdep that GPIO irqs are in a different - * category than their parents, so it won't report false recursion. - */ -static struct lock_class_key gpio_lock_class; - -static int oxnas_gpio_irq_map(struct irq_domain *h, unsigned int virq, - irq_hw_number_t hw) -{ - struct oxnas_gpio_chip *oxnas_gpio = h->host_data; - - irq_set_lockdep_class(virq, &gpio_lock_class); - - irq_set_chip_and_handler(virq, &gpio_irqchip, handle_edge_irq); - irq_set_chip_data(virq, oxnas_gpio); - - return 0; -} - -static int oxnas_gpio_irq_domain_xlate(struct irq_domain *d, - struct device_node *ctrlr, - const u32 *intspec, - unsigned int intsize, - irq_hw_number_t *out_hwirq, - unsigned int *out_type) -{ - struct oxnas_gpio_chip *oxnas_gpio = d->host_data; - int ret; - int pin = oxnas_gpio->chip.base + intspec[0]; - - if (WARN_ON(intsize < 2)) - return -EINVAL; - *out_hwirq = intspec[0]; - *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK; - - ret = gpio_request(pin, ctrlr->full_name); - if (ret) - return ret; - - ret = gpio_direction_input(pin); - if (ret) - return ret; - - return 0; -} - -static struct irq_domain_ops oxnas_gpio_ops = { - .map = oxnas_gpio_irq_map, - .xlate = oxnas_gpio_irq_domain_xlate, -}; - -static int oxnas_gpio_of_irq_setup(struct device_node *node, - struct oxnas_gpio_chip *oxnas_gpio, - unsigned int irq) -{ - /* Disable irqs of this controller */ - writel_relaxed(0, oxnas_gpio->regbase + RE_IRQ_ENABLE); - writel_relaxed(0, oxnas_gpio->regbase + FE_IRQ_ENABLE); - - /* Setup irq domain */ - oxnas_gpio->domain = irq_domain_add_linear(node, oxnas_gpio->chip.ngpio, - &oxnas_gpio_ops, oxnas_gpio); - if (!oxnas_gpio->domain) - panic("oxnas_gpio: couldn't allocate irq domain (DT).\n"); - - irq_set_chip_data(irq, oxnas_gpio); - irq_set_chained_handler(irq, gpio_irq_handler); - - return 0; -} - -/* This structure is replicated for each GPIO block allocated at probe time */ -static struct gpio_chip oxnas_gpio_template = { - .request = oxnas_gpio_request, - .free = oxnas_gpio_free, - .direction_input = oxnas_gpio_direction_input, - .get = oxnas_gpio_get, - .direction_output = oxnas_gpio_direction_output, - .set = oxnas_gpio_set, - .to_irq = oxnas_gpio_to_irq, - .dbg_show = oxnas_gpio_dbg_show, - .can_sleep = 0, - .ngpio = MAX_NB_GPIO_PER_BANK, -}; - -static struct of_device_id oxnas_gpio_of_match[] = { - { .compatible = "plxtech,nas782x-gpio"}, - { /* sentinel */ } -}; - -static int oxnas_gpio_probe(struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node; - struct resource *res; - struct oxnas_gpio_chip *oxnas_chip = NULL; - struct gpio_chip *chip; - struct pinctrl_gpio_range *range; - int ret = 0; - int irq, i; - int alias_idx = of_alias_get_id(np, "gpio"); - uint32_t ngpio; - char **names; - - BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips)); - if (gpio_chips[alias_idx]) { - ret = -EBUSY; - goto err; - } - - irq = platform_get_irq(pdev, 0); - if (irq < 0) { - ret = irq; - goto err; - } - - oxnas_chip = devm_kzalloc(&pdev->dev, sizeof(*oxnas_chip), GFP_KERNEL); - if (!oxnas_chip) { - ret = -ENOMEM; - goto err; - } - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - oxnas_chip->regbase = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(oxnas_chip->regbase)) { - ret = PTR_ERR(oxnas_chip->regbase); - goto err; - } - - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - oxnas_chip->ctrlbase = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(oxnas_chip->ctrlbase)) { - ret = PTR_ERR(oxnas_chip->ctrlbase); - goto err; - } - - oxnas_chip->chip = oxnas_gpio_template; - - spin_lock_init(&oxnas_chip->lock); - - chip = &oxnas_chip->chip; - chip->of_node = np; - chip->label = dev_name(&pdev->dev); - chip->dev = &pdev->dev; - chip->owner = THIS_MODULE; - chip->base = alias_idx * MAX_NB_GPIO_PER_BANK; - - if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) { - if (ngpio > MAX_NB_GPIO_PER_BANK) - pr_err("oxnas_gpio.%d, gpio-nb >= %d failback to %d\n", - alias_idx, MAX_NB_GPIO_PER_BANK, - MAX_NB_GPIO_PER_BANK); - else - chip->ngpio = ngpio; - } - - names = devm_kzalloc(&pdev->dev, sizeof(char *) * chip->ngpio, - GFP_KERNEL); - - if (!names) { - ret = -ENOMEM; - goto err; - } - - for (i = 0; i < chip->ngpio; i++) - names[i] = kasprintf(GFP_KERNEL, "MF_%c%d", alias_idx + 'A', i); - - chip->names = (const char *const *)names; - - range = &oxnas_chip->range; - range->name = chip->label; - range->id = alias_idx; - range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK; - - range->npins = chip->ngpio; - range->gc = chip; - - ret = gpiochip_add(chip); - if (ret) - goto err; - - gpio_chips[alias_idx] = oxnas_chip; - gpio_banks = max(gpio_banks, alias_idx + 1); - - oxnas_gpio_of_irq_setup(np, oxnas_chip, irq); - - dev_info(&pdev->dev, "at address %p\n", oxnas_chip->regbase); - - return 0; -err: - dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx); - - return ret; -} - -static struct platform_driver oxnas_gpio_driver = { - .driver = { - .name = "gpio-oxnas", - .owner = THIS_MODULE, - .of_match_table = of_match_ptr(oxnas_gpio_of_match), - }, - .probe = oxnas_gpio_probe, -}; - -static struct platform_driver oxnas_pinctrl_driver = { - .driver = { - .name = "pinctrl-oxnas", - .owner = THIS_MODULE, - .of_match_table = of_match_ptr(oxnas_pinctrl_of_match), - }, - .probe = oxnas_pinctrl_probe, - .remove = oxnas_pinctrl_remove, -}; - -static int __init oxnas_pinctrl_init(void) -{ - int ret; - - ret = platform_driver_register(&oxnas_gpio_driver); - if (ret) - return ret; - return platform_driver_register(&oxnas_pinctrl_driver); -} -arch_initcall(oxnas_pinctrl_init); - -static void __exit oxnas_pinctrl_exit(void) -{ - platform_driver_unregister(&oxnas_pinctrl_driver); -} - -module_exit(oxnas_pinctrl_exit); -MODULE_AUTHOR("Ma Hajun <mahaijuns@gmail.com>"); -MODULE_DESCRIPTION("Plxtech Nas782x pinctrl driver"); -MODULE_LICENSE("GPL v2"); diff --git a/target/linux/oxnas/files/drivers/reset/reset-ox820.c b/target/linux/oxnas/files/drivers/reset/reset-ox820.c deleted file mode 100644 index 0a28de55f4..0000000000 --- a/target/linux/oxnas/files/drivers/reset/reset-ox820.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include <linux/err.h> -#include <linux/io.h> -#include <linux/module.h> -#include <linux/of.h> -#include <linux/platform_device.h> -#include <linux/reset-controller.h> -#include <linux/slab.h> -#include <linux/types.h> -#include <mach/hardware.h> - -static int ox820_reset_reset(struct reset_controller_dev *rcdev, - unsigned long id) -{ - writel(BIT(id), SYS_CTRL_RST_SET_CTRL); - writel(BIT(id), SYS_CTRL_RST_CLR_CTRL); - return 0; -} - -static int ox820_reset_assert(struct reset_controller_dev *rcdev, - unsigned long id) -{ - writel(BIT(id), SYS_CTRL_RST_SET_CTRL); - - return 0; -} - -static int ox820_reset_deassert(struct reset_controller_dev *rcdev, - unsigned long id) -{ - writel(BIT(id), SYS_CTRL_RST_CLR_CTRL); - - return 0; -} - -static struct reset_control_ops ox820_reset_ops = { - .reset = ox820_reset_reset, - .assert = ox820_reset_assert, - .deassert = ox820_reset_deassert, -}; - -static const struct of_device_id ox820_reset_dt_ids[] = { - { .compatible = "plxtech,nas782x-reset", }, - { /* sentinel */ }, -}; -MODULE_DEVICE_TABLE(of, ox820_reset_dt_ids); - -struct reset_controller_dev rcdev; - -static int ox820_reset_probe(struct platform_device *pdev) -{ - struct reset_controller_dev *rcdev; - - rcdev = devm_kzalloc(&pdev->dev, sizeof(*rcdev), GFP_KERNEL); - if (!rcdev) - return -ENOMEM; - - /* note: reset controller is statically mapped */ - - rcdev->owner = THIS_MODULE; - rcdev->nr_resets = 32; - rcdev->ops = &ox820_reset_ops; - rcdev->of_node = pdev->dev.of_node; - reset_controller_register(rcdev); - platform_set_drvdata(pdev, rcdev); - - return 0; -} - -static int ox820_reset_remove(struct platform_device *pdev) -{ - struct reset_controller_dev *rcdev = platform_get_drvdata(pdev); - - reset_controller_unregister(rcdev); - - return 0; -} - -static struct platform_driver ox820_reset_driver = { - .probe = ox820_reset_probe, - .remove = ox820_reset_remove, - .driver = { - .name = "ox820-reset", - .owner = THIS_MODULE, - .of_match_table = ox820_reset_dt_ids, - }, -}; - -static int __init ox820_reset_init(void) -{ - return platform_driver_probe(&ox820_reset_driver, - ox820_reset_probe); -} -/* - * reset controller does not support probe deferral, so it has to be - * initialized before any user, in particular, PCIE uses subsys_initcall. - */ -arch_initcall(ox820_reset_init); - -MODULE_AUTHOR("Ma Haijun"); -MODULE_LICENSE("GPL"); diff --git a/target/linux/oxnas/files/drivers/usb/host/ehci-oxnas.c b/target/linux/oxnas/files/drivers/usb/host/ehci-oxnas.c deleted file mode 100644 index 15578a3027..0000000000 --- a/target/linux/oxnas/files/drivers/usb/host/ehci-oxnas.c +++ /dev/null @@ -1,316 +0,0 @@ -/* - * drivers/usb/host/ehci-oxnas.c - * - * Tzachi Perelstein <tzachi@marvell.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/platform_device.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_irq.h> -#include <linux/usb.h> -#include <linux/usb/hcd.h> -#include <linux/dma-mapping.h> -#include <linux/clk.h> -#include <linux/reset.h> -#include <mach/hardware.h> -#include <mach/utils.h> - -#include "ehci.h" - -struct oxnas_hcd { - struct clk *clk; - struct clk *refsrc; - struct clk *phyref; - int use_pllb; - int use_phya; - struct reset_control *rst_host; - struct reset_control *rst_phya; - struct reset_control *rst_phyb; -}; - -#define DRIVER_DESC "Oxnas On-Chip EHCI Host Controller" - -static struct hc_driver __read_mostly oxnas_hc_driver; - -static void start_oxnas_usb_ehci(struct oxnas_hcd *oxnas) -{ - u32 reg; - - if (oxnas->use_pllb) { - /* enable pllb */ - clk_prepare_enable(oxnas->refsrc); - /* enable ref600 */ - clk_prepare_enable(oxnas->phyref); - /* 600MHz pllb divider for 12MHz */ - writel(PLLB_DIV_INT(50) | PLLB_DIV_FRAC(0), - SEC_CTRL_PLLB_DIV_CTRL); - - } else { - /* ref 300 divider for 12MHz */ - writel(REF300_DIV_INT(25) | REF300_DIV_FRAC(0), - SYS_CTRL_REF300_DIV); - } - - /* Ensure the USB block is properly reset */ - reset_control_reset(oxnas->rst_host); - reset_control_reset(oxnas->rst_phya); - reset_control_reset(oxnas->rst_phyb); - - /* Force the high speed clock to be generated all the time, via serial - programming of the USB HS PHY */ - writel((2UL << USBHSPHY_TEST_ADD) | - (0xe0UL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL); - - writel((1UL << USBHSPHY_TEST_CLK) | - (2UL << USBHSPHY_TEST_ADD) | - (0xe0UL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL); - - writel((0xfUL << USBHSPHY_TEST_ADD) | - (0xaaUL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL); - - writel((1UL << USBHSPHY_TEST_CLK) | - (0xfUL << USBHSPHY_TEST_ADD) | - (0xaaUL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL); - - if (oxnas->use_pllb) /* use pllb clock */ - writel(USB_CLK_INTERNAL | USB_INT_CLK_PLLB, SYS_CTRL_USB_CTRL); - else /* use ref300 derived clock */ - writel(USB_CLK_INTERNAL | USB_INT_CLK_REF300, - SYS_CTRL_USB_CTRL); - - if (oxnas->use_phya) { - /* Configure USB PHYA as a host */ - reg = readl(SYS_CTRL_USB_CTRL); - reg &= ~USBAMUX_DEVICE; - writel(reg, SYS_CTRL_USB_CTRL); - } - - /* Enable the clock to the USB block */ - clk_prepare_enable(oxnas->clk); -} - -static void stop_oxnas_usb_ehci(struct oxnas_hcd *oxnas) -{ - reset_control_assert(oxnas->rst_host); - reset_control_assert(oxnas->rst_phya); - reset_control_assert(oxnas->rst_phyb); - - if (oxnas->use_pllb) { - clk_disable_unprepare(oxnas->phyref); - clk_disable_unprepare(oxnas->refsrc); - } - clk_disable_unprepare(oxnas->clk); -} - -static int ehci_oxnas_reset(struct usb_hcd *hcd) -{ - #define txttfill_tuning reserved2[0] - - struct ehci_hcd *ehci; - u32 tmp; - int retval = ehci_setup(hcd); - if (retval) - return retval; - - ehci = hcd_to_ehci(hcd); - tmp = ehci_readl(ehci, &ehci->regs->txfill_tuning); - tmp &= ~0x00ff0000; - tmp |= 0x003f0000; /* set burst pre load count to 0x40 (63 * 4 bytes) */ - tmp |= 0x16; /* set sheduler overhead to 22 * 1.267us (HS) or 22 * 6.33us (FS/LS)*/ - ehci_writel(ehci, tmp, &ehci->regs->txfill_tuning); - - tmp = ehci_readl(ehci, &ehci->regs->txttfill_tuning); - tmp |= 0x2; /* set sheduler overhead to 2 * 6.333us */ - ehci_writel(ehci, tmp, &ehci->regs->txttfill_tuning); - - return retval; -} - -static int ehci_oxnas_drv_probe(struct platform_device *ofdev) -{ - struct device_node *np = ofdev->dev.of_node; - struct usb_hcd *hcd; - struct ehci_hcd *ehci; - struct resource res; - struct oxnas_hcd *oxnas; - int irq, err; - struct reset_control *rstc; - - if (usb_disabled()) - return -ENODEV; - - if (!ofdev->dev.dma_mask) - ofdev->dev.dma_mask = &ofdev->dev.coherent_dma_mask; - if (!ofdev->dev.coherent_dma_mask) - ofdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); - - hcd = usb_create_hcd(&oxnas_hc_driver, &ofdev->dev, - dev_name(&ofdev->dev)); - if (!hcd) - return -ENOMEM; - - err = of_address_to_resource(np, 0, &res); - if (err) - goto err_res; - - hcd->rsrc_start = res.start; - hcd->rsrc_len = resource_size(&res); - - hcd->regs = devm_ioremap_resource(&ofdev->dev, &res); - if (IS_ERR(hcd->regs)) { - dev_err(&ofdev->dev, "devm_ioremap_resource failed\n"); - err = PTR_ERR(hcd->regs); - goto err_ioremap; - } - - oxnas = (struct oxnas_hcd *)hcd_to_ehci(hcd)->priv; - - oxnas->use_pllb = of_property_read_bool(np, "plxtech,ehci_use_pllb"); - oxnas->use_phya = of_property_read_bool(np, "plxtech,ehci_use_phya"); - - oxnas->clk = of_clk_get_by_name(np, "usb"); - if (IS_ERR(oxnas->clk)) { - err = PTR_ERR(oxnas->clk); - goto err_clk; - } - - if (oxnas->use_pllb) { - oxnas->refsrc = of_clk_get_by_name(np, "refsrc"); - if (IS_ERR(oxnas->refsrc)) { - err = PTR_ERR(oxnas->refsrc); - goto err_refsrc; - } - oxnas->phyref = of_clk_get_by_name(np, "phyref"); - if (IS_ERR(oxnas->refsrc)) { - err = PTR_ERR(oxnas->refsrc); - goto err_phyref; - } - - } else { - oxnas->refsrc = NULL; - oxnas->phyref = NULL; - } - - rstc = devm_reset_control_get(&ofdev->dev, "host"); - if (IS_ERR(rstc)) { - err = PTR_ERR(rstc); - goto err_rst; - } - oxnas->rst_host = rstc; - - rstc = devm_reset_control_get(&ofdev->dev, "phya"); - if (IS_ERR(rstc)) { - err = PTR_ERR(rstc); - goto err_rst; - } - oxnas->rst_phya = rstc; - - rstc = devm_reset_control_get(&ofdev->dev, "phyb"); - if (IS_ERR(rstc)) { - err = PTR_ERR(rstc); - goto err_rst; - } - oxnas->rst_phyb = rstc; - - irq = irq_of_parse_and_map(np, 0); - if (!irq) { - dev_err(&ofdev->dev, "irq_of_parse_and_map failed\n"); - err = -EBUSY; - goto err_irq; - } - - hcd->has_tt = 1; - ehci = hcd_to_ehci(hcd); - ehci->caps = hcd->regs; - - start_oxnas_usb_ehci(oxnas); - - err = usb_add_hcd(hcd, irq, IRQF_SHARED); - if (err) - goto err_hcd; - - return 0; - -err_hcd: - stop_oxnas_usb_ehci(oxnas); -err_irq: -err_rst: - if (oxnas->phyref) - clk_put(oxnas->phyref); -err_phyref: - if (oxnas->refsrc) - clk_put(oxnas->refsrc); -err_refsrc: - clk_put(oxnas->clk); -err_clk: -err_ioremap: -err_res: - usb_put_hcd(hcd); - - return err; -} - -static int ehci_oxnas_drv_remove(struct platform_device *pdev) -{ - struct usb_hcd *hcd = platform_get_drvdata(pdev); - struct oxnas_hcd *oxnas = (struct oxnas_hcd *)hcd_to_ehci(hcd)->priv; - - usb_remove_hcd(hcd); - if (oxnas->use_pllb) { - clk_disable_unprepare(oxnas->phyref); - clk_put(oxnas->phyref); - clk_disable_unprepare(oxnas->refsrc); - clk_put(oxnas->refsrc); - } - clk_disable_unprepare(oxnas->clk); - usb_put_hcd(hcd); - - return 0; -} - -static const struct of_device_id oxnas_ehci_dt_ids[] = { - { .compatible = "plxtech,nas782x-ehci" }, - { /* sentinel */ } -}; - -MODULE_DEVICE_TABLE(of, oxnas_ehci_dt_ids); - -static struct platform_driver ehci_oxnas_driver = { - .probe = ehci_oxnas_drv_probe, - .remove = ehci_oxnas_drv_remove, - .shutdown = usb_hcd_platform_shutdown, - .driver.name = "oxnas-ehci", - .driver.of_match_table = oxnas_ehci_dt_ids, -}; - -static const struct ehci_driver_overrides oxnas_overrides __initconst = { - .reset = ehci_oxnas_reset, - .extra_priv_size = sizeof(struct oxnas_hcd), -}; - -static int __init ehci_oxnas_init(void) -{ - if (usb_disabled()) - return -ENODEV; - - ehci_init_driver(&oxnas_hc_driver, &oxnas_overrides); - return platform_driver_register(&ehci_oxnas_driver); -} -module_init(ehci_oxnas_init); - -static void __exit ehci_oxnas_cleanup(void) -{ - platform_driver_unregister(&ehci_oxnas_driver); -} -module_exit(ehci_oxnas_cleanup); - -MODULE_DESCRIPTION(DRIVER_DESC); -MODULE_ALIAS("platform:oxnas-ehci"); -MODULE_LICENSE("GPL"); diff --git a/target/linux/oxnas/image/Makefile b/target/linux/oxnas/image/Makefile deleted file mode 100644 index bfa0f0cca7..0000000000 --- a/target/linux/oxnas/image/Makefile +++ /dev/null @@ -1,107 +0,0 @@ -# -# Copyright (C) 2013-2016 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/image.mk - -UBIFS_OPTS = -m 2048 -e 126KiB -c 4096 - -DEVICE_VARS += DTS UBIFS_OPTS - -KERNEL_LOADADDR := 0x60008000 - -define Build/ubootable - (dd if="$(STAGING_DIR_IMAGE)/u-boot.bin" bs=128k conv=sync; \ - dd if="$@" bs=128k conv=sync ) >> $@.new - @mv "$@.new" "$@" -endef - -define Device/Default - KERNEL_DEPENDS = $$(wildcard $$(DTS_DIR)/ox820-$$(DTS).dts) - KERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/ox820-$$(DTS).dtb - KERNEL_NAME := zImage - KERNEL_SUFFIX := -uImage - KERNEL_INSTALL := 1 - KERNEL_INITRAMFS = kernel-bin | lzma | fit lzma $$(DTS_DIR)/ox820-$$(DTS).dtb | ubootable - KERNEL_INITRAMFS_PREFIX = $$(IMAGE_PREFIX)-u-boot-initramfs - KERNEL_INITRAMFS_SUFFIX := .bin - BLOCKSIZE := 128k - PAGESIZE := 2048 - SUBPAGESIZE := 512 - FILESYSTEMS := squashfs ubifs - PROFILES = Default $$(DTS) - IMAGES := ubinized.bin sysupgrade.tar - IMAGE/ubinized.bin := append-ubi - IMAGE/sysupgrade.tar := sysupgrade-tar | append-metadata - KERNEL_IN_UBI := 1 - UBOOTENV_IN_UBI := 1 -endef - -define Device/akitio - DTS := akitio - DEVICE_TITLE := Akitio MyCloud mini / Silverstone DC01 - DEVICE_PACKAGES := kmod-i2c-gpio kmod-rtc-ds1307 -endef -TARGET_DEVICES += akitio - -define Build/omninas-factory - rm -rf $@.tmp $@.dummy $@.dummy.gz - mkdir -p $@.tmp - $(CP) $@ $@.tmp/uImage - dd if=/dev/zero bs=64k count=4 of=$@.dummy - gzip $@.dummy - mkimage -A arm -T ramdisk -C gzip -n "dummy" \ - -d $@.dummy.gz \ - $@.tmp/rdimg.gz - echo 2.35.20140102 > $@.tmp/version ; echo >> $@.tmp/version - chmod 0744 $@.tmp/* - $(TAR) -C $@.tmp -czvf $@ \ - $(if $(SOURCE_DATE_EPOCH),--mtime="@$(SOURCE_DATE_EPOCH)") . -endef - -define Build/encrypt-3des - openssl enc -des3 -a -k $(1) -in $@ -out $@.new && mv $@.new $@ -endef - -define Device/kd20 - DEVICE_DTS := ox820-kd20 - DEVICE_TITLE := Shuttle KD20 - KERNEL := kernel-bin | append-dtb | uImage none - KERNEL_INITRAMFS_PREFIX = $$(IMAGE_PREFIX)-factory - KERNEL_INITRAMFS_SUFFIX := .tar.gz - KERNEL_INITRAMFS = kernel-bin | append-dtb | uImage none | omninas-factory | encrypt-3des sohmuntitnlaes - KERNEL_IMAGE := zImage - DEVICE_PACKAGES := kmod-usb3 kmod-i2c-gpio kmod-rtc-pcf8563 kmod-gpio-beeper \ - kmod-hwmon-core kmod-hwmon-gpiofan \ - kmod-md-mod kmod-md-raid0 kmod-md-raid1 kmod-fs-ext4 kmod-fs-xfs - KERNEL_IN_UBI := - UBOOTENV_IN_UBI := -endef -TARGET_DEVICES += kd20 - -define Device/pogoplug-pro - DTS := pogoplug-pro - DEVICE_TITLE := Cloud Engines Pogoplug Pro (with mPCIe) -endef -TARGET_DEVICES += pogoplug-pro - -define Device/pogoplug-v3 - DTS := pogoplug-v3 - DEVICE_TITLE := Cloud Engines Pogoplug V3 (no mPCIe) -endef -TARGET_DEVICES += pogoplug-v3 - -define Device/stg212 - DTS := stg212 - DEVICE_TITLE := MitraStar STG-212 -endef -TARGET_DEVICES += stg212 - -VMLINUX:=$(BIN_DIR)/$(IMG_PREFIX)-vmlinux -UIMAGE:=$(BIN_DIR)/$(IMG_PREFIX)-uImage - -$(eval $(call BuildImage)) diff --git a/target/linux/oxnas/modules.mk b/target/linux/oxnas/modules.mk deleted file mode 100644 index 7016398619..0000000000 --- a/target/linux/oxnas/modules.mk +++ /dev/null @@ -1,41 +0,0 @@ -# -# Copyright (C) 2006-2014 OpenWrt.org -# Copyright (C) 2016 LEDE project -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -define KernelPackage/ata-oxnas-sata - SUBMENU:=$(BLOCK_MENU) - TITLE:=oxnas Serial ATA support - KCONFIG:=CONFIG_SATA_OXNAS - DEPENDS:=@TARGET_oxnas - FILES:=$(LINUX_DIR)/drivers/ata/sata_oxnas.ko - AUTOLOAD:=$(call AutoLoad,41,sata_oxnas,1) - $(call AddDepends/ata) -endef - -define KernelPackage/ata-oxnas-sata/description - SATA support for OX934 core found in the OX82x/PLX782x SoCs -endef - -$(eval $(call KernelPackage,ata-oxnas-sata)) - - -define KernelPackage/usb2-oxnas - SUBMENU:=$(BLOCK_MENU) - TITLE:=OXNAS USB controller driver - DEPENDS:=@TARGET_oxnas +kmod-usb2 - KCONFIG:=CONFIG_USB_EHCI_OXNAS - FILES:=$(LINUX_DIR)/drivers/usb/host/ehci-oxnas.ko - AUTOLOAD:=$(call AutoLoad,55,ehci-oxnas,1) - $(call AddDepends/usb) -endef - -define KernelPackage/usb2-oxnas/description - This driver provides USB Device Controller support for the - EHCI USB host built-in to the PLXTECH NAS782x SoC -endef - -$(eval $(call KernelPackage,usb2-oxnas)) diff --git a/target/linux/oxnas/patches-4.4/0072-mtd-backport-v4.7-0day-patches-from-Boris.patch b/target/linux/oxnas/patches-4.4/0072-mtd-backport-v4.7-0day-patches-from-Boris.patch deleted file mode 100644 index 204d6e0bc7..0000000000 --- a/target/linux/oxnas/patches-4.4/0072-mtd-backport-v4.7-0day-patches-from-Boris.patch +++ /dev/null @@ -1,5281 +0,0 @@ -From a369af5149e6eb442b22ce89b564dd7a76e03638 Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Tue, 26 Apr 2016 19:05:01 +0200 -Subject: [PATCH 072/102] mtd: backport v4.7-0day patches from Boris - -Signed-off-by: John Crispin <blogic@openwrt.org> ---- - drivers/mtd/Kconfig | 4 +- - drivers/mtd/cmdlinepart.c | 3 +- - drivers/mtd/devices/m25p80.c | 44 +-- - drivers/mtd/maps/physmap_of.c | 6 +- - drivers/mtd/mtdchar.c | 123 ++++++-- - drivers/mtd/mtdconcat.c | 2 +- - drivers/mtd/mtdcore.c | 428 ++++++++++++++++++++++++-- - drivers/mtd/mtdcore.h | 7 +- - drivers/mtd/mtdpart.c | 161 ++++++---- - drivers/mtd/mtdswap.c | 24 +- - drivers/mtd/nand/Kconfig | 21 +- - drivers/mtd/nand/Makefile | 2 + - drivers/mtd/nand/nand_base.c | 571 +++++++++++++++++++---------------- - drivers/mtd/nand/nand_bbt.c | 34 +-- - drivers/mtd/nand/nand_bch.c | 52 ++-- - drivers/mtd/nand/nand_ecc.c | 6 +- - drivers/mtd/nand/nand_ids.c | 4 +- - drivers/mtd/nand/nandsim.c | 43 +-- - drivers/mtd/ofpart.c | 53 ++-- - drivers/mtd/spi-nor/Kconfig | 10 +- - drivers/mtd/spi-nor/Makefile | 1 + - drivers/mtd/spi-nor/mtk-quadspi.c | 485 +++++++++++++++++++++++++++++ - drivers/mtd/spi-nor/spi-nor.c | 321 +++++++++++++------- - drivers/mtd/tests/mtd_nandecctest.c | 2 +- - drivers/mtd/tests/oobtest.c | 49 ++- - drivers/mtd/tests/pagetest.c | 3 +- - include/linux/mtd/bbm.h | 1 - - include/linux/mtd/fsmc.h | 18 -- - include/linux/mtd/inftl.h | 1 - - include/linux/mtd/map.h | 9 +- - include/linux/mtd/mtd.h | 80 ++++- - include/linux/mtd/nand.h | 94 ++++-- - include/linux/mtd/nand_bch.h | 10 +- - include/linux/mtd/nftl.h | 1 - - include/linux/mtd/onenand.h | 2 - - include/linux/mtd/partitions.h | 27 +- - include/linux/mtd/sh_flctl.h | 4 +- - include/linux/mtd/sharpsl.h | 2 +- - include/linux/mtd/spi-nor.h | 23 +- - include/uapi/mtd/mtd-abi.h | 2 +- - 45 files changed, 2077 insertions(+), 748 deletions(-) - create mode 100644 drivers/mtd/spi-nor/mtk-quadspi.c - ---- a/drivers/mtd/Kconfig -+++ b/drivers/mtd/Kconfig -@@ -131,7 +131,7 @@ config MTD_CMDLINE_PARTS - - config MTD_AFS_PARTS - tristate "ARM Firmware Suite partition parsing" -- depends on ARM -+ depends on (ARM || ARM64) - ---help--- - The ARM Firmware Suite allows the user to divide flash devices into - multiple 'images'. Each such image has a header containing its name -@@ -161,7 +161,7 @@ config MTD_AR7_PARTS - - config MTD_BCM63XX_PARTS - tristate "BCM63XX CFE partitioning support" -- depends on BCM63XX -+ depends on BCM63XX || BMIPS_GENERIC || COMPILE_TEST - select CRC32 - help - This provides partions parsing for BCM63xx devices with CFE ---- a/drivers/mtd/cmdlinepart.c -+++ b/drivers/mtd/cmdlinepart.c -@@ -304,7 +304,7 @@ static int mtdpart_setup_real(char *s) - * the first one in the chain if a NULL mtd_id is passed in. - */ - static int parse_cmdline_partitions(struct mtd_info *master, -- struct mtd_partition **pparts, -+ const struct mtd_partition **pparts, - struct mtd_part_parser_data *data) - { - unsigned long long offset; -@@ -382,7 +382,6 @@ static int __init mtdpart_setup(char *s) - __setup("mtdparts=", mtdpart_setup); - - static struct mtd_part_parser cmdline_parser = { -- .owner = THIS_MODULE, - .parse_fn = parse_cmdline_partitions, - .name = "cmdlinepart", - }; ---- a/drivers/mtd/devices/m25p80.c -+++ b/drivers/mtd/devices/m25p80.c -@@ -174,22 +174,6 @@ static int m25p80_read(struct spi_nor *n - return 0; - } - --static int m25p80_erase(struct spi_nor *nor, loff_t offset) --{ -- struct m25p *flash = nor->priv; -- -- dev_dbg(nor->dev, "%dKiB at 0x%08x\n", -- flash->spi_nor.mtd.erasesize / 1024, (u32)offset); -- -- /* Set up command buffer. */ -- flash->command[0] = nor->erase_opcode; -- m25p_addr2cmd(nor, offset, flash->command); -- -- spi_write(flash->spi, flash->command, m25p_cmdsz(nor)); -- -- return 0; --} -- - /* - * board specific setup should have ensured the SPI clock used here - * matches what the READ command supports, at least until this driver -@@ -197,12 +181,11 @@ static int m25p80_erase(struct spi_nor * - */ - static int m25p_probe(struct spi_device *spi) - { -- struct mtd_part_parser_data ppdata; - struct flash_platform_data *data; - struct m25p *flash; - struct spi_nor *nor; - enum read_mode mode = SPI_NOR_NORMAL; -- char *flash_name = NULL; -+ char *flash_name; - int ret; - - data = dev_get_platdata(&spi->dev); -@@ -216,12 +199,11 @@ static int m25p_probe(struct spi_device - /* install the hooks */ - nor->read = m25p80_read; - nor->write = m25p80_write; -- nor->erase = m25p80_erase; - nor->write_reg = m25p80_write_reg; - nor->read_reg = m25p80_read_reg; - - nor->dev = &spi->dev; -- nor->flash_node = spi->dev.of_node; -+ spi_nor_set_flash_node(nor, spi->dev.of_node); - nor->priv = flash; - - spi_set_drvdata(spi, flash); -@@ -242,6 +224,8 @@ static int m25p_probe(struct spi_device - */ - if (data && data->type) - flash_name = data->type; -+ else if (!strcmp(spi->modalias, "spi-nor")) -+ flash_name = NULL; /* auto-detect */ - else - flash_name = spi->modalias; - -@@ -249,11 +233,8 @@ static int m25p_probe(struct spi_device - if (ret) - return ret; - -- ppdata.of_node = spi->dev.of_node; -- -- return mtd_device_parse_register(&nor->mtd, NULL, &ppdata, -- data ? data->parts : NULL, -- data ? data->nr_parts : 0); -+ return mtd_device_register(&nor->mtd, data ? data->parts : NULL, -+ data ? data->nr_parts : 0); - } - - -@@ -279,14 +260,21 @@ static int m25p_remove(struct spi_device - */ - static const struct spi_device_id m25p_ids[] = { - /* -+ * Allow non-DT platform devices to bind to the "spi-nor" modalias, and -+ * hack around the fact that the SPI core does not provide uevent -+ * matching for .of_match_table -+ */ -+ {"spi-nor"}, -+ -+ /* - * Entries not used in DTs that should be safe to drop after replacing -- * them with "nor-jedec" in platform data. -+ * them with "spi-nor" in platform data. - */ - {"s25sl064a"}, {"w25x16"}, {"m25p10"}, {"m25px64"}, - - /* -- * Entries that were used in DTs without "nor-jedec" fallback and should -- * be kept for backward compatibility. -+ * Entries that were used in DTs without "jedec,spi-nor" fallback and -+ * should be kept for backward compatibility. - */ - {"at25df321a"}, {"at25df641"}, {"at26df081a"}, - {"mr25h256"}, ---- a/drivers/mtd/maps/physmap_of.c -+++ b/drivers/mtd/maps/physmap_of.c -@@ -128,7 +128,6 @@ static int of_flash_probe(struct platfor - int reg_tuple_size; - struct mtd_info **mtd_list = NULL; - resource_size_t res_size; -- struct mtd_part_parser_data ppdata; - bool map_indirect; - const char *mtd_name = NULL; - -@@ -272,8 +271,9 @@ static int of_flash_probe(struct platfor - if (err) - goto err_out; - -- ppdata.of_node = dp; -- mtd_device_parse_register(info->cmtd, part_probe_types_def, &ppdata, -+ info->cmtd->dev.parent = &dev->dev; -+ mtd_set_of_node(info->cmtd, dp); -+ mtd_device_parse_register(info->cmtd, part_probe_types_def, NULL, - NULL, 0); - - kfree(mtd_list); ---- a/drivers/mtd/mtdchar.c -+++ b/drivers/mtd/mtdchar.c -@@ -465,38 +465,111 @@ static int mtdchar_readoob(struct file * - } - - /* -- * Copies (and truncates, if necessary) data from the larger struct, -- * nand_ecclayout, to the smaller, deprecated layout struct, -- * nand_ecclayout_user. This is necessary only to support the deprecated -- * API ioctl ECCGETLAYOUT while allowing all new functionality to use -- * nand_ecclayout flexibly (i.e. the struct may change size in new -- * releases without requiring major rewrites). -+ * Copies (and truncates, if necessary) OOB layout information to the -+ * deprecated layout struct, nand_ecclayout_user. This is necessary only to -+ * support the deprecated API ioctl ECCGETLAYOUT while allowing all new -+ * functionality to use mtd_ooblayout_ops flexibly (i.e. mtd_ooblayout_ops -+ * can describe any kind of OOB layout with almost zero overhead from a -+ * memory usage point of view). - */ --static int shrink_ecclayout(const struct nand_ecclayout *from, -- struct nand_ecclayout_user *to) -+static int shrink_ecclayout(struct mtd_info *mtd, -+ struct nand_ecclayout_user *to) - { -- int i; -+ struct mtd_oob_region oobregion; -+ int i, section = 0, ret; - -- if (!from || !to) -+ if (!mtd || !to) - return -EINVAL; - - memset(to, 0, sizeof(*to)); - -- to->eccbytes = min((int)from->eccbytes, MTD_MAX_ECCPOS_ENTRIES); -- for (i = 0; i < to->eccbytes; i++) -- to->eccpos[i] = from->eccpos[i]; -+ to->eccbytes = 0; -+ for (i = 0; i < MTD_MAX_ECCPOS_ENTRIES;) { -+ u32 eccpos; -+ -+ ret = mtd_ooblayout_ecc(mtd, section, &oobregion); -+ if (ret < 0) { -+ if (ret != -ERANGE) -+ return ret; -+ -+ break; -+ } -+ -+ eccpos = oobregion.offset; -+ for (; i < MTD_MAX_ECCPOS_ENTRIES && -+ eccpos < oobregion.offset + oobregion.length; i++) { -+ to->eccpos[i] = eccpos++; -+ to->eccbytes++; -+ } -+ } - - for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES; i++) { -- if (from->oobfree[i].length == 0 && -- from->oobfree[i].offset == 0) -+ ret = mtd_ooblayout_free(mtd, i, &oobregion); -+ if (ret < 0) { -+ if (ret != -ERANGE) -+ return ret; -+ - break; -- to->oobavail += from->oobfree[i].length; -- to->oobfree[i] = from->oobfree[i]; -+ } -+ -+ to->oobfree[i].offset = oobregion.offset; -+ to->oobfree[i].length = oobregion.length; -+ to->oobavail += to->oobfree[i].length; - } - - return 0; - } - -+static int get_oobinfo(struct mtd_info *mtd, struct nand_oobinfo *to) -+{ -+ struct mtd_oob_region oobregion; -+ int i, section = 0, ret; -+ -+ if (!mtd || !to) -+ return -EINVAL; -+ -+ memset(to, 0, sizeof(*to)); -+ -+ to->eccbytes = 0; -+ for (i = 0; i < ARRAY_SIZE(to->eccpos);) { -+ u32 eccpos; -+ -+ ret = mtd_ooblayout_ecc(mtd, section, &oobregion); -+ if (ret < 0) { -+ if (ret != -ERANGE) -+ return ret; -+ -+ break; -+ } -+ -+ if (oobregion.length + i > ARRAY_SIZE(to->eccpos)) -+ return -EINVAL; -+ -+ eccpos = oobregion.offset; -+ for (; eccpos < oobregion.offset + oobregion.length; i++) { -+ to->eccpos[i] = eccpos++; -+ to->eccbytes++; -+ } -+ } -+ -+ for (i = 0; i < 8; i++) { -+ ret = mtd_ooblayout_free(mtd, i, &oobregion); -+ if (ret < 0) { -+ if (ret != -ERANGE) -+ return ret; -+ -+ break; -+ } -+ -+ to->oobfree[i][0] = oobregion.offset; -+ to->oobfree[i][1] = oobregion.length; -+ } -+ -+ to->useecc = MTD_NANDECC_AUTOPLACE; -+ -+ return 0; -+} -+ - static int mtdchar_blkpg_ioctl(struct mtd_info *mtd, - struct blkpg_ioctl_arg *arg) - { -@@ -815,16 +888,12 @@ static int mtdchar_ioctl(struct file *fi - { - struct nand_oobinfo oi; - -- if (!mtd->ecclayout) -+ if (!mtd->ooblayout) - return -EOPNOTSUPP; -- if (mtd->ecclayout->eccbytes > ARRAY_SIZE(oi.eccpos)) -- return -EINVAL; - -- oi.useecc = MTD_NANDECC_AUTOPLACE; -- memcpy(&oi.eccpos, mtd->ecclayout->eccpos, sizeof(oi.eccpos)); -- memcpy(&oi.oobfree, mtd->ecclayout->oobfree, -- sizeof(oi.oobfree)); -- oi.eccbytes = mtd->ecclayout->eccbytes; -+ ret = get_oobinfo(mtd, &oi); -+ if (ret) -+ return ret; - - if (copy_to_user(argp, &oi, sizeof(struct nand_oobinfo))) - return -EFAULT; -@@ -913,14 +982,14 @@ static int mtdchar_ioctl(struct file *fi - { - struct nand_ecclayout_user *usrlay; - -- if (!mtd->ecclayout) -+ if (!mtd->ooblayout) - return -EOPNOTSUPP; - - usrlay = kmalloc(sizeof(*usrlay), GFP_KERNEL); - if (!usrlay) - return -ENOMEM; - -- shrink_ecclayout(mtd->ecclayout, usrlay); -+ shrink_ecclayout(mtd, usrlay); - - if (copy_to_user(argp, usrlay, sizeof(*usrlay))) - ret = -EFAULT; ---- a/drivers/mtd/mtdconcat.c -+++ b/drivers/mtd/mtdconcat.c -@@ -777,7 +777,7 @@ struct mtd_info *mtd_concat_create(struc - - } - -- concat->mtd.ecclayout = subdev[0]->ecclayout; -+ mtd_set_ooblayout(&concat->mtd, subdev[0]->ooblayout); - - concat->num_subdev = num_devs; - concat->mtd.name = name; ---- a/drivers/mtd/mtdcore.c -+++ b/drivers/mtd/mtdcore.c -@@ -32,6 +32,7 @@ - #include <linux/err.h> - #include <linux/ioctl.h> - #include <linux/init.h> -+#include <linux/of.h> - #include <linux/proc_fs.h> - #include <linux/idr.h> - #include <linux/backing-dev.h> -@@ -446,6 +447,7 @@ int add_mtd_device(struct mtd_info *mtd) - mtd->dev.devt = MTD_DEVT(i); - dev_set_name(&mtd->dev, "mtd%d", i); - dev_set_drvdata(&mtd->dev, mtd); -+ of_node_get(mtd_get_of_node(mtd)); - error = device_register(&mtd->dev); - if (error) - goto fail_added; -@@ -477,6 +479,7 @@ int add_mtd_device(struct mtd_info *mtd) - return 0; - - fail_added: -+ of_node_put(mtd_get_of_node(mtd)); - idr_remove(&mtd_idr, i); - fail_locked: - mutex_unlock(&mtd_table_mutex); -@@ -518,6 +521,7 @@ int del_mtd_device(struct mtd_info *mtd) - device_unregister(&mtd->dev); - - idr_remove(&mtd_idr, mtd->index); -+ of_node_put(mtd_get_of_node(mtd)); - - module_put(THIS_MODULE); - ret = 0; -@@ -529,9 +533,10 @@ out_error: - } - - static int mtd_add_device_partitions(struct mtd_info *mtd, -- struct mtd_partition *real_parts, -- int nbparts) -+ struct mtd_partitions *parts) - { -+ const struct mtd_partition *real_parts = parts->parts; -+ int nbparts = parts->nr_parts; - int ret; - - if (nbparts == 0 || IS_ENABLED(CONFIG_MTD_PARTITIONED_MASTER)) { -@@ -600,29 +605,29 @@ int mtd_device_parse_register(struct mtd - const struct mtd_partition *parts, - int nr_parts) - { -+ struct mtd_partitions parsed; - int ret; -- struct mtd_partition *real_parts = NULL; - - mtd_set_dev_defaults(mtd); - -- ret = parse_mtd_partitions(mtd, types, &real_parts, parser_data); -- if (ret <= 0 && nr_parts && parts) { -- real_parts = kmemdup(parts, sizeof(*parts) * nr_parts, -- GFP_KERNEL); -- if (!real_parts) -- ret = -ENOMEM; -- else -- ret = nr_parts; -- } -- /* Didn't come up with either parsed OR fallback partitions */ -- if (ret < 0) { -- pr_info("mtd: failed to find partitions; one or more parsers reports errors (%d)\n", -+ memset(&parsed, 0, sizeof(parsed)); -+ -+ ret = parse_mtd_partitions(mtd, types, &parsed, parser_data); -+ if ((ret < 0 || parsed.nr_parts == 0) && parts && nr_parts) { -+ /* Fall back to driver-provided partitions */ -+ parsed = (struct mtd_partitions){ -+ .parts = parts, -+ .nr_parts = nr_parts, -+ }; -+ } else if (ret < 0) { -+ /* Didn't come up with parsed OR fallback partitions */ -+ pr_info("mtd: failed to find partitions; one or more parsers reports errors (%d)\n", - ret); - /* Don't abort on errors; we can still use unpartitioned MTD */ -- ret = 0; -+ memset(&parsed, 0, sizeof(parsed)); - } - -- ret = mtd_add_device_partitions(mtd, real_parts, ret); -+ ret = mtd_add_device_partitions(mtd, &parsed); - if (ret) - goto out; - -@@ -642,7 +647,8 @@ int mtd_device_parse_register(struct mtd - } - - out: -- kfree(real_parts); -+ /* Cleanup any parsed partitions */ -+ mtd_part_parser_cleanup(&parsed); - return ret; - } - EXPORT_SYMBOL_GPL(mtd_device_parse_register); -@@ -767,7 +773,6 @@ out: - } - EXPORT_SYMBOL_GPL(get_mtd_device); - -- - int __get_mtd_device(struct mtd_info *mtd) - { - int err; -@@ -1001,6 +1006,366 @@ int mtd_read_oob(struct mtd_info *mtd, l - } - EXPORT_SYMBOL_GPL(mtd_read_oob); - -+/** -+ * mtd_ooblayout_ecc - Get the OOB region definition of a specific ECC section -+ * @mtd: MTD device structure -+ * @section: ECC section. Depending on the layout you may have all the ECC -+ * bytes stored in a single contiguous section, or one section -+ * per ECC chunk (and sometime several sections for a single ECC -+ * ECC chunk) -+ * @oobecc: OOB region struct filled with the appropriate ECC position -+ * information -+ * -+ * This functions return ECC section information in the OOB area. I you want -+ * to get all the ECC bytes information, then you should call -+ * mtd_ooblayout_ecc(mtd, section++, oobecc) until it returns -ERANGE. -+ * -+ * Returns zero on success, a negative error code otherwise. -+ */ -+int mtd_ooblayout_ecc(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobecc) -+{ -+ memset(oobecc, 0, sizeof(*oobecc)); -+ -+ if (!mtd || section < 0) -+ return -EINVAL; -+ -+ if (!mtd->ooblayout || !mtd->ooblayout->ecc) -+ return -ENOTSUPP; -+ -+ return mtd->ooblayout->ecc(mtd, section, oobecc); -+} -+EXPORT_SYMBOL_GPL(mtd_ooblayout_ecc); -+ -+/** -+ * mtd_ooblayout_free - Get the OOB region definition of a specific free -+ * section -+ * @mtd: MTD device structure -+ * @section: Free section you are interested in. Depending on the layout -+ * you may have all the free bytes stored in a single contiguous -+ * section, or one section per ECC chunk plus an extra section -+ * for the remaining bytes (or other funky layout). -+ * @oobfree: OOB region struct filled with the appropriate free position -+ * information -+ * -+ * This functions return free bytes position in the OOB area. I you want -+ * to get all the free bytes information, then you should call -+ * mtd_ooblayout_free(mtd, section++, oobfree) until it returns -ERANGE. -+ * -+ * Returns zero on success, a negative error code otherwise. -+ */ -+int mtd_ooblayout_free(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobfree) -+{ -+ memset(oobfree, 0, sizeof(*oobfree)); -+ -+ if (!mtd || section < 0) -+ return -EINVAL; -+ -+ if (!mtd->ooblayout || !mtd->ooblayout->free) -+ return -ENOTSUPP; -+ -+ return mtd->ooblayout->free(mtd, section, oobfree); -+} -+EXPORT_SYMBOL_GPL(mtd_ooblayout_free); -+ -+/** -+ * mtd_ooblayout_find_region - Find the region attached to a specific byte -+ * @mtd: mtd info structure -+ * @byte: the byte we are searching for -+ * @sectionp: pointer where the section id will be stored -+ * @oobregion: used to retrieve the ECC position -+ * @iter: iterator function. Should be either mtd_ooblayout_free or -+ * mtd_ooblayout_ecc depending on the region type you're searching for -+ * -+ * This functions returns the section id and oobregion information of a -+ * specific byte. For example, say you want to know where the 4th ECC byte is -+ * stored, you'll use: -+ * -+ * mtd_ooblayout_find_region(mtd, 3, §ion, &oobregion, mtd_ooblayout_ecc); -+ * -+ * Returns zero on success, a negative error code otherwise. -+ */ -+static int mtd_ooblayout_find_region(struct mtd_info *mtd, int byte, -+ int *sectionp, struct mtd_oob_region *oobregion, -+ int (*iter)(struct mtd_info *, -+ int section, -+ struct mtd_oob_region *oobregion)) -+{ -+ int pos = 0, ret, section = 0; -+ -+ memset(oobregion, 0, sizeof(*oobregion)); -+ -+ while (1) { -+ ret = iter(mtd, section, oobregion); -+ if (ret) -+ return ret; -+ -+ if (pos + oobregion->length > byte) -+ break; -+ -+ pos += oobregion->length; -+ section++; -+ } -+ -+ /* -+ * Adjust region info to make it start at the beginning at the -+ * 'start' ECC byte. -+ */ -+ oobregion->offset += byte - pos; -+ oobregion->length -= byte - pos; -+ *sectionp = section; -+ -+ return 0; -+} -+ -+/** -+ * mtd_ooblayout_find_eccregion - Find the ECC region attached to a specific -+ * ECC byte -+ * @mtd: mtd info structure -+ * @eccbyte: the byte we are searching for -+ * @sectionp: pointer where the section id will be stored -+ * @oobregion: OOB region information -+ * -+ * Works like mtd_ooblayout_find_region() except it searches for a specific ECC -+ * byte. -+ * -+ * Returns zero on success, a negative error code otherwise. -+ */ -+int mtd_ooblayout_find_eccregion(struct mtd_info *mtd, int eccbyte, -+ int *section, -+ struct mtd_oob_region *oobregion) -+{ -+ return mtd_ooblayout_find_region(mtd, eccbyte, section, oobregion, -+ mtd_ooblayout_ecc); -+} -+EXPORT_SYMBOL_GPL(mtd_ooblayout_find_eccregion); -+ -+/** -+ * mtd_ooblayout_get_bytes - Extract OOB bytes from the oob buffer -+ * @mtd: mtd info structure -+ * @buf: destination buffer to store OOB bytes -+ * @oobbuf: OOB buffer -+ * @start: first byte to retrieve -+ * @nbytes: number of bytes to retrieve -+ * @iter: section iterator -+ * -+ * Extract bytes attached to a specific category (ECC or free) -+ * from the OOB buffer and copy them into buf. -+ * -+ * Returns zero on success, a negative error code otherwise. -+ */ -+static int mtd_ooblayout_get_bytes(struct mtd_info *mtd, u8 *buf, -+ const u8 *oobbuf, int start, int nbytes, -+ int (*iter)(struct mtd_info *, -+ int section, -+ struct mtd_oob_region *oobregion)) -+{ -+ struct mtd_oob_region oobregion = { }; -+ int section = 0, ret; -+ -+ ret = mtd_ooblayout_find_region(mtd, start, §ion, -+ &oobregion, iter); -+ -+ while (!ret) { -+ int cnt; -+ -+ cnt = oobregion.length > nbytes ? nbytes : oobregion.length; -+ memcpy(buf, oobbuf + oobregion.offset, cnt); -+ buf += cnt; -+ nbytes -= cnt; -+ -+ if (!nbytes) -+ break; -+ -+ ret = iter(mtd, ++section, &oobregion); -+ } -+ -+ return ret; -+} -+ -+/** -+ * mtd_ooblayout_set_bytes - put OOB bytes into the oob buffer -+ * @mtd: mtd info structure -+ * @buf: source buffer to get OOB bytes from -+ * @oobbuf: OOB buffer -+ * @start: first OOB byte to set -+ * @nbytes: number of OOB bytes to set -+ * @iter: section iterator -+ * -+ * Fill the OOB buffer with data provided in buf. The category (ECC or free) -+ * is selected by passing the appropriate iterator. -+ * -+ * Returns zero on success, a negative error code otherwise. -+ */ -+static int mtd_ooblayout_set_bytes(struct mtd_info *mtd, const u8 *buf, -+ u8 *oobbuf, int start, int nbytes, -+ int (*iter)(struct mtd_info *, -+ int section, -+ struct mtd_oob_region *oobregion)) -+{ -+ struct mtd_oob_region oobregion = { }; -+ int section = 0, ret; -+ -+ ret = mtd_ooblayout_find_region(mtd, start, §ion, -+ &oobregion, iter); -+ -+ while (!ret) { -+ int cnt; -+ -+ cnt = oobregion.length > nbytes ? nbytes : oobregion.length; -+ memcpy(oobbuf + oobregion.offset, buf, cnt); -+ buf += cnt; -+ nbytes -= cnt; -+ -+ if (!nbytes) -+ break; -+ -+ ret = iter(mtd, ++section, &oobregion); -+ } -+ -+ return ret; -+} -+ -+/** -+ * mtd_ooblayout_count_bytes - count the number of bytes in a OOB category -+ * @mtd: mtd info structure -+ * @iter: category iterator -+ * -+ * Count the number of bytes in a given category. -+ * -+ * Returns a positive value on success, a negative error code otherwise. -+ */ -+static int mtd_ooblayout_count_bytes(struct mtd_info *mtd, -+ int (*iter)(struct mtd_info *, -+ int section, -+ struct mtd_oob_region *oobregion)) -+{ -+ struct mtd_oob_region oobregion = { }; -+ int section = 0, ret, nbytes = 0; -+ -+ while (1) { -+ ret = iter(mtd, section++, &oobregion); -+ if (ret) { -+ if (ret == -ERANGE) -+ ret = nbytes; -+ break; -+ } -+ -+ nbytes += oobregion.length; -+ } -+ -+ return ret; -+} -+ -+/** -+ * mtd_ooblayout_get_eccbytes - extract ECC bytes from the oob buffer -+ * @mtd: mtd info structure -+ * @eccbuf: destination buffer to store ECC bytes -+ * @oobbuf: OOB buffer -+ * @start: first ECC byte to retrieve -+ * @nbytes: number of ECC bytes to retrieve -+ * -+ * Works like mtd_ooblayout_get_bytes(), except it acts on ECC bytes. -+ * -+ * Returns zero on success, a negative error code otherwise. -+ */ -+int mtd_ooblayout_get_eccbytes(struct mtd_info *mtd, u8 *eccbuf, -+ const u8 *oobbuf, int start, int nbytes) -+{ -+ return mtd_ooblayout_get_bytes(mtd, eccbuf, oobbuf, start, nbytes, -+ mtd_ooblayout_ecc); -+} -+EXPORT_SYMBOL_GPL(mtd_ooblayout_get_eccbytes); -+ -+/** -+ * mtd_ooblayout_set_eccbytes - set ECC bytes into the oob buffer -+ * @mtd: mtd info structure -+ * @eccbuf: source buffer to get ECC bytes from -+ * @oobbuf: OOB buffer -+ * @start: first ECC byte to set -+ * @nbytes: number of ECC bytes to set -+ * -+ * Works like mtd_ooblayout_set_bytes(), except it acts on ECC bytes. -+ * -+ * Returns zero on success, a negative error code otherwise. -+ */ -+int mtd_ooblayout_set_eccbytes(struct mtd_info *mtd, const u8 *eccbuf, -+ u8 *oobbuf, int start, int nbytes) -+{ -+ return mtd_ooblayout_set_bytes(mtd, eccbuf, oobbuf, start, nbytes, -+ mtd_ooblayout_ecc); -+} -+EXPORT_SYMBOL_GPL(mtd_ooblayout_set_eccbytes); -+ -+/** -+ * mtd_ooblayout_get_databytes - extract data bytes from the oob buffer -+ * @mtd: mtd info structure -+ * @databuf: destination buffer to store ECC bytes -+ * @oobbuf: OOB buffer -+ * @start: first ECC byte to retrieve -+ * @nbytes: number of ECC bytes to retrieve -+ * -+ * Works like mtd_ooblayout_get_bytes(), except it acts on free bytes. -+ * -+ * Returns zero on success, a negative error code otherwise. -+ */ -+int mtd_ooblayout_get_databytes(struct mtd_info *mtd, u8 *databuf, -+ const u8 *oobbuf, int start, int nbytes) -+{ -+ return mtd_ooblayout_get_bytes(mtd, databuf, oobbuf, start, nbytes, -+ mtd_ooblayout_free); -+} -+EXPORT_SYMBOL_GPL(mtd_ooblayout_get_databytes); -+ -+/** -+ * mtd_ooblayout_get_eccbytes - set data bytes into the oob buffer -+ * @mtd: mtd info structure -+ * @eccbuf: source buffer to get data bytes from -+ * @oobbuf: OOB buffer -+ * @start: first ECC byte to set -+ * @nbytes: number of ECC bytes to set -+ * -+ * Works like mtd_ooblayout_get_bytes(), except it acts on free bytes. -+ * -+ * Returns zero on success, a negative error code otherwise. -+ */ -+int mtd_ooblayout_set_databytes(struct mtd_info *mtd, const u8 *databuf, -+ u8 *oobbuf, int start, int nbytes) -+{ -+ return mtd_ooblayout_set_bytes(mtd, databuf, oobbuf, start, nbytes, -+ mtd_ooblayout_free); -+} -+EXPORT_SYMBOL_GPL(mtd_ooblayout_set_databytes); -+ -+/** -+ * mtd_ooblayout_count_freebytes - count the number of free bytes in OOB -+ * @mtd: mtd info structure -+ * -+ * Works like mtd_ooblayout_count_bytes(), except it count free bytes. -+ * -+ * Returns zero on success, a negative error code otherwise. -+ */ -+int mtd_ooblayout_count_freebytes(struct mtd_info *mtd) -+{ -+ return mtd_ooblayout_count_bytes(mtd, mtd_ooblayout_free); -+} -+EXPORT_SYMBOL_GPL(mtd_ooblayout_count_freebytes); -+ -+/** -+ * mtd_ooblayout_count_freebytes - count the number of ECC bytes in OOB -+ * @mtd: mtd info structure -+ * -+ * Works like mtd_ooblayout_count_bytes(), except it count ECC bytes. -+ * -+ * Returns zero on success, a negative error code otherwise. -+ */ -+int mtd_ooblayout_count_eccbytes(struct mtd_info *mtd) -+{ -+ return mtd_ooblayout_count_bytes(mtd, mtd_ooblayout_ecc); -+} -+EXPORT_SYMBOL_GPL(mtd_ooblayout_count_eccbytes); -+ - /* - * Method to access the protection register area, present in some flash - * devices. The user data is one time programmable but the factory data is read ---- a/drivers/mtd/mtdcore.h -+++ b/drivers/mtd/mtdcore.h -@@ -10,10 +10,15 @@ int add_mtd_device(struct mtd_info *mtd) - int del_mtd_device(struct mtd_info *mtd); - int add_mtd_partitions(struct mtd_info *, const struct mtd_partition *, int); - int del_mtd_partitions(struct mtd_info *); -+ -+struct mtd_partitions; -+ - int parse_mtd_partitions(struct mtd_info *master, const char * const *types, -- struct mtd_partition **pparts, -+ struct mtd_partitions *pparts, - struct mtd_part_parser_data *data); - -+void mtd_part_parser_cleanup(struct mtd_partitions *parts); -+ - int __init init_mtdchar(void); - void __exit cleanup_mtdchar(void); - ---- a/drivers/mtd/mtdpart.c -+++ b/drivers/mtd/mtdpart.c -@@ -55,9 +55,12 @@ static void mtd_partition_split(struct m - - /* - * Given a pointer to the MTD object in the mtd_part structure, we can retrieve -- * the pointer to that structure with this macro. -+ * the pointer to that structure. - */ --#define PART(x) ((struct mtd_part *)(x)) -+static inline struct mtd_part *mtd_to_part(const struct mtd_info *mtd) -+{ -+ return container_of(mtd, struct mtd_part, mtd); -+} - - - /* -@@ -68,7 +71,7 @@ static void mtd_partition_split(struct m - static int part_read(struct mtd_info *mtd, loff_t from, size_t len, - size_t *retlen, u_char *buf) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - struct mtd_ecc_stats stats; - int res; - -@@ -87,7 +90,7 @@ static int part_read(struct mtd_info *mt - static int part_point(struct mtd_info *mtd, loff_t from, size_t len, - size_t *retlen, void **virt, resource_size_t *phys) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - - return part->master->_point(part->master, from + part->offset, len, - retlen, virt, phys); -@@ -95,7 +98,7 @@ static int part_point(struct mtd_info *m - - static int part_unpoint(struct mtd_info *mtd, loff_t from, size_t len) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - - return part->master->_unpoint(part->master, from + part->offset, len); - } -@@ -105,7 +108,7 @@ static unsigned long part_get_unmapped_a - unsigned long offset, - unsigned long flags) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - - offset += part->offset; - return part->master->_get_unmapped_area(part->master, len, offset, -@@ -115,7 +118,7 @@ static unsigned long part_get_unmapped_a - static int part_read_oob(struct mtd_info *mtd, loff_t from, - struct mtd_oob_ops *ops) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - int res; - - if (from >= mtd->size) -@@ -130,10 +133,7 @@ static int part_read_oob(struct mtd_info - if (ops->oobbuf) { - size_t len, pages; - -- if (ops->mode == MTD_OPS_AUTO_OOB) -- len = mtd->oobavail; -- else -- len = mtd->oobsize; -+ len = mtd_oobavail(mtd, ops); - pages = mtd_div_by_ws(mtd->size, mtd); - pages -= mtd_div_by_ws(from, mtd); - if (ops->ooboffs + ops->ooblen > pages * len) -@@ -153,7 +153,7 @@ static int part_read_oob(struct mtd_info - static int part_read_user_prot_reg(struct mtd_info *mtd, loff_t from, - size_t len, size_t *retlen, u_char *buf) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - return part->master->_read_user_prot_reg(part->master, from, len, - retlen, buf); - } -@@ -161,7 +161,7 @@ static int part_read_user_prot_reg(struc - static int part_get_user_prot_info(struct mtd_info *mtd, size_t len, - size_t *retlen, struct otp_info *buf) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - return part->master->_get_user_prot_info(part->master, len, retlen, - buf); - } -@@ -169,7 +169,7 @@ static int part_get_user_prot_info(struc - static int part_read_fact_prot_reg(struct mtd_info *mtd, loff_t from, - size_t len, size_t *retlen, u_char *buf) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - return part->master->_read_fact_prot_reg(part->master, from, len, - retlen, buf); - } -@@ -177,7 +177,7 @@ static int part_read_fact_prot_reg(struc - static int part_get_fact_prot_info(struct mtd_info *mtd, size_t len, - size_t *retlen, struct otp_info *buf) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - return part->master->_get_fact_prot_info(part->master, len, retlen, - buf); - } -@@ -185,7 +185,7 @@ static int part_get_fact_prot_info(struc - static int part_write(struct mtd_info *mtd, loff_t to, size_t len, - size_t *retlen, const u_char *buf) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - return part->master->_write(part->master, to + part->offset, len, - retlen, buf); - } -@@ -193,7 +193,7 @@ static int part_write(struct mtd_info *m - static int part_panic_write(struct mtd_info *mtd, loff_t to, size_t len, - size_t *retlen, const u_char *buf) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - return part->master->_panic_write(part->master, to + part->offset, len, - retlen, buf); - } -@@ -201,7 +201,7 @@ static int part_panic_write(struct mtd_i - static int part_write_oob(struct mtd_info *mtd, loff_t to, - struct mtd_oob_ops *ops) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - - if (to >= mtd->size) - return -EINVAL; -@@ -213,7 +213,7 @@ static int part_write_oob(struct mtd_inf - static int part_write_user_prot_reg(struct mtd_info *mtd, loff_t from, - size_t len, size_t *retlen, u_char *buf) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - return part->master->_write_user_prot_reg(part->master, from, len, - retlen, buf); - } -@@ -221,21 +221,21 @@ static int part_write_user_prot_reg(stru - static int part_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, - size_t len) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - return part->master->_lock_user_prot_reg(part->master, from, len); - } - - static int part_writev(struct mtd_info *mtd, const struct kvec *vecs, - unsigned long count, loff_t to, size_t *retlen) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - return part->master->_writev(part->master, vecs, count, - to + part->offset, retlen); - } - - static int part_erase(struct mtd_info *mtd, struct erase_info *instr) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - int ret; - - -@@ -299,7 +299,7 @@ static int part_erase(struct mtd_info *m - void mtd_erase_callback(struct erase_info *instr) - { - if (instr->mtd->_erase == part_erase) { -- struct mtd_part *part = PART(instr->mtd); -+ struct mtd_part *part = mtd_to_part(instr->mtd); - size_t wrlen = 0; - - if (instr->mtd->flags & MTD_ERASE_PARTIAL) { -@@ -330,13 +330,13 @@ EXPORT_SYMBOL_GPL(mtd_erase_callback); - - static int part_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - return part->master->_lock(part->master, ofs + part->offset, len); - } - - static int part_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - - ofs += part->offset; - if (mtd->flags & MTD_ERASE_PARTIAL) { -@@ -349,45 +349,45 @@ static int part_unlock(struct mtd_info * - - static int part_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - return part->master->_is_locked(part->master, ofs + part->offset, len); - } - - static void part_sync(struct mtd_info *mtd) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - part->master->_sync(part->master); - } - - static int part_suspend(struct mtd_info *mtd) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - return part->master->_suspend(part->master); - } - - static void part_resume(struct mtd_info *mtd) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - part->master->_resume(part->master); - } - - static int part_block_isreserved(struct mtd_info *mtd, loff_t ofs) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - ofs += part->offset; - return part->master->_block_isreserved(part->master, ofs); - } - - static int part_block_isbad(struct mtd_info *mtd, loff_t ofs) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - ofs += part->offset; - return part->master->_block_isbad(part->master, ofs); - } - - static int part_block_markbad(struct mtd_info *mtd, loff_t ofs) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - int res; - - ofs += part->offset; -@@ -397,6 +397,27 @@ static int part_block_markbad(struct mtd - return res; - } - -+static int part_ooblayout_ecc(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobregion) -+{ -+ struct mtd_part *part = mtd_to_part(mtd); -+ -+ return mtd_ooblayout_ecc(part->master, section, oobregion); -+} -+ -+static int part_ooblayout_free(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobregion) -+{ -+ struct mtd_part *part = mtd_to_part(mtd); -+ -+ return mtd_ooblayout_free(part->master, section, oobregion); -+} -+ -+static const struct mtd_ooblayout_ops part_ooblayout_ops = { -+ .ecc = part_ooblayout_ecc, -+ .free = part_ooblayout_free, -+}; -+ - static inline void free_partition(struct mtd_part *p) - { - kfree(p->mtd.name); -@@ -614,7 +635,7 @@ static struct mtd_part *allocate_partiti - slave->mtd.erasesize = slave->mtd.size; - } - -- slave->mtd.ecclayout = master->ecclayout; -+ mtd_set_ooblayout(&slave->mtd, &part_ooblayout_ops); - slave->mtd.ecc_step_size = master->ecc_step_size; - slave->mtd.ecc_strength = master->ecc_strength; - slave->mtd.bitflip_threshold = master->bitflip_threshold; -@@ -639,7 +660,7 @@ static ssize_t mtd_partition_offset_show - struct device_attribute *attr, char *buf) - { - struct mtd_info *mtd = dev_get_drvdata(dev); -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - return snprintf(buf, PAGE_SIZE, "%lld\n", part->offset); - } - -@@ -677,11 +698,10 @@ int mtd_add_partition(struct mtd_info *m - if (length <= 0) - return -EINVAL; - -+ memset(&part, 0, sizeof(part)); - part.name = name; - part.size = length; - part.offset = offset; -- part.mask_flags = 0; -- part.ecclayout = NULL; - - new = allocate_partition(master, &part, -1, offset); - if (IS_ERR(new)) -@@ -845,7 +865,7 @@ int add_mtd_partitions(struct mtd_info * - static DEFINE_SPINLOCK(part_parser_lock); - static LIST_HEAD(part_parsers); - --static struct mtd_part_parser *get_partition_parser(const char *name) -+static struct mtd_part_parser *mtd_part_parser_get(const char *name) - { - struct mtd_part_parser *p, *ret = NULL; - -@@ -862,7 +882,20 @@ static struct mtd_part_parser *get_parti - return ret; - } - --#define put_partition_parser(p) do { module_put((p)->owner); } while (0) -+static inline void mtd_part_parser_put(const struct mtd_part_parser *p) -+{ -+ module_put(p->owner); -+} -+ -+/* -+ * Many partition parsers just expected the core to kfree() all their data in -+ * one chunk. Do that by default. -+ */ -+static void mtd_part_parser_cleanup_default(const struct mtd_partition *pparts, -+ int nr_parts) -+{ -+ kfree(pparts); -+} - - static struct mtd_part_parser * - get_partition_parser_by_type(enum mtd_parser_type type, -@@ -874,7 +907,7 @@ get_partition_parser_by_type(enum mtd_pa - - p = list_prepare_entry(start, &part_parsers, list); - if (start) -- put_partition_parser(start); -+ mtd_part_parser_put(start); - - list_for_each_entry_continue(p, &part_parsers, list) { - if (p->type == type && try_module_get(p->owner)) { -@@ -888,13 +921,19 @@ get_partition_parser_by_type(enum mtd_pa - return ret; - } - --void register_mtd_parser(struct mtd_part_parser *p) --{ -+int __register_mtd_parser(struct mtd_part_parser *p, struct module *owner) -+ { -+ p->owner = owner; -+ -+ if (!p->cleanup) -+ p->cleanup = &mtd_part_parser_cleanup_default; -+ - spin_lock(&part_parser_lock); - list_add(&p->list, &part_parsers); - spin_unlock(&part_parser_lock); -+ return 0; - } --EXPORT_SYMBOL_GPL(register_mtd_parser); -+EXPORT_SYMBOL_GPL(__register_mtd_parser); - - void deregister_mtd_parser(struct mtd_part_parser *p) - { -@@ -954,7 +993,7 @@ static const char * const default_mtd_pa - * parse_mtd_partitions - parse MTD partitions - * @master: the master partition (describes whole MTD device) - * @types: names of partition parsers to try or %NULL -- * @pparts: array of partitions found is returned here -+ * @pparts: info about partitions found is returned here - * @data: MTD partition parser-specific data - * - * This function tries to find partition on MTD device @master. It uses MTD -@@ -966,45 +1005,42 @@ static const char * const default_mtd_pa - * - * This function may return: - * o a negative error code in case of failure -- * o zero if no partitions were found -- * o a positive number of found partitions, in which case on exit @pparts will -- * point to an array containing this number of &struct mtd_info objects. -+ * o zero otherwise, and @pparts will describe the partitions, number of -+ * partitions, and the parser which parsed them. Caller must release -+ * resources with mtd_part_parser_cleanup() when finished with the returned -+ * data. - */ - int parse_mtd_partitions(struct mtd_info *master, const char *const *types, -- struct mtd_partition **pparts, -+ struct mtd_partitions *pparts, - struct mtd_part_parser_data *data) - { - struct mtd_part_parser *parser; - int ret, err = 0; - const char *const *types_of = NULL; - -- if (data && data->of_node) { -- types_of = of_get_probes(data->of_node); -- if (types_of != NULL) -- types = types_of; -- } -- - if (!types) - types = default_mtd_part_types; - - for ( ; *types; types++) { - pr_debug("%s: parsing partitions %s\n", master->name, *types); -- parser = get_partition_parser(*types); -+ parser = mtd_part_parser_get(*types); - if (!parser && !request_module("%s", *types)) -- parser = get_partition_parser(*types); -+ parser = mtd_part_parser_get(*types); - pr_debug("%s: got parser %s\n", master->name, - parser ? parser->name : NULL); - if (!parser) - continue; -- ret = (*parser->parse_fn)(master, pparts, data); -+ ret = (*parser->parse_fn)(master, &pparts->parts, data); - pr_debug("%s: parser %s: %i\n", - master->name, parser->name, ret); -- put_partition_parser(parser); - if (ret > 0) { - printk(KERN_NOTICE "%d %s partitions found on MTD device %s\n", - ret, parser->name, master->name); -- return ret; -+ pparts->nr_parts = ret; -+ pparts->parser = parser; -+ return 0; - } -+ mtd_part_parser_put(parser); - /* - * Stash the first error we see; only report it if no parser - * succeeds -@@ -1034,7 +1070,7 @@ int parse_mtd_partitions_by_type(struct - ret = (*parser->parse_fn)(master, pparts, data); - - if (ret > 0) { -- put_partition_parser(parser); -+ mtd_part_parser_put(parser); - printk(KERN_NOTICE - "%d %s partitions found on MTD device %s\n", - ret, parser->name, master->name); -@@ -1048,6 +1084,22 @@ int parse_mtd_partitions_by_type(struct - } - EXPORT_SYMBOL_GPL(parse_mtd_partitions_by_type); - -+void mtd_part_parser_cleanup(struct mtd_partitions *parts) -+{ -+ const struct mtd_part_parser *parser; -+ -+ if (!parts) -+ return; -+ -+ parser = parts->parser; -+ if (parser) { -+ if (parser->cleanup) -+ parser->cleanup(parts->parts, parts->nr_parts); -+ -+ mtd_part_parser_put(parser); -+ } -+} -+ - int mtd_is_partition(const struct mtd_info *mtd) - { - struct mtd_part *part; -@@ -1070,7 +1122,7 @@ struct mtd_info *mtdpart_get_master(cons - if (!mtd_is_partition(mtd)) - return (struct mtd_info *)mtd; - -- return PART(mtd)->master; -+ return mtd_to_part(mtd)->master; - } - EXPORT_SYMBOL_GPL(mtdpart_get_master); - -@@ -1079,7 +1131,7 @@ uint64_t mtdpart_get_offset(const struct - if (!mtd_is_partition(mtd)) - return 0; - -- return PART(mtd)->offset; -+ return mtd_to_part(mtd)->offset; - } - EXPORT_SYMBOL_GPL(mtdpart_get_offset); - -@@ -1089,6 +1141,6 @@ uint64_t mtd_get_device_size(const struc - if (!mtd_is_partition(mtd)) - return mtd->size; - -- return PART(mtd)->master->size; -+ return mtd_to_part(mtd)->master->size; - } - EXPORT_SYMBOL_GPL(mtd_get_device_size); ---- a/drivers/mtd/mtdswap.c -+++ b/drivers/mtd/mtdswap.c -@@ -346,7 +346,7 @@ static int mtdswap_read_markers(struct m - if (mtd_can_have_bb(d->mtd) && mtd_block_isbad(d->mtd, offset)) - return MTDSWAP_SCANNED_BAD; - -- ops.ooblen = 2 * d->mtd->ecclayout->oobavail; -+ ops.ooblen = 2 * d->mtd->oobavail; - ops.oobbuf = d->oob_buf; - ops.ooboffs = 0; - ops.datbuf = NULL; -@@ -359,7 +359,7 @@ static int mtdswap_read_markers(struct m - - data = (struct mtdswap_oobdata *)d->oob_buf; - data2 = (struct mtdswap_oobdata *) -- (d->oob_buf + d->mtd->ecclayout->oobavail); -+ (d->oob_buf + d->mtd->oobavail); - - if (le16_to_cpu(data->magic) == MTDSWAP_MAGIC_CLEAN) { - eb->erase_count = le32_to_cpu(data->count); -@@ -933,7 +933,7 @@ static unsigned int mtdswap_eblk_passes( - - ops.mode = MTD_OPS_AUTO_OOB; - ops.len = mtd->writesize; -- ops.ooblen = mtd->ecclayout->oobavail; -+ ops.ooblen = mtd->oobavail; - ops.ooboffs = 0; - ops.datbuf = d->page_buf; - ops.oobbuf = d->oob_buf; -@@ -945,7 +945,7 @@ static unsigned int mtdswap_eblk_passes( - for (i = 0; i < mtd_pages; i++) { - patt = mtdswap_test_patt(test + i); - memset(d->page_buf, patt, mtd->writesize); -- memset(d->oob_buf, patt, mtd->ecclayout->oobavail); -+ memset(d->oob_buf, patt, mtd->oobavail); - ret = mtd_write_oob(mtd, pos, &ops); - if (ret) - goto error; -@@ -964,7 +964,7 @@ static unsigned int mtdswap_eblk_passes( - if (p1[j] != patt) - goto error; - -- for (j = 0; j < mtd->ecclayout->oobavail; j++) -+ for (j = 0; j < mtd->oobavail; j++) - if (p2[j] != (unsigned char)patt) - goto error; - -@@ -1387,7 +1387,7 @@ static int mtdswap_init(struct mtdswap_d - if (!d->page_buf) - goto page_buf_fail; - -- d->oob_buf = kmalloc(2 * mtd->ecclayout->oobavail, GFP_KERNEL); -+ d->oob_buf = kmalloc(2 * mtd->oobavail, GFP_KERNEL); - if (!d->oob_buf) - goto oob_buf_fail; - -@@ -1417,7 +1417,6 @@ static void mtdswap_add_mtd(struct mtd_b - unsigned long part; - unsigned int eblocks, eavailable, bad_blocks, spare_cnt; - uint64_t swap_size, use_size, size_limit; -- struct nand_ecclayout *oinfo; - int ret; - - parts = &partitions[0]; -@@ -1447,17 +1446,10 @@ static void mtdswap_add_mtd(struct mtd_b - return; - } - -- oinfo = mtd->ecclayout; -- if (!oinfo) { -- printk(KERN_ERR "%s: mtd%d does not have OOB\n", -- MTDSWAP_PREFIX, mtd->index); -- return; -- } -- -- if (!mtd->oobsize || oinfo->oobavail < MTDSWAP_OOBSIZE) { -+ if (!mtd->oobsize || mtd->oobavail < MTDSWAP_OOBSIZE) { - printk(KERN_ERR "%s: Not enough free bytes in OOB, " - "%d available, %zu needed.\n", -- MTDSWAP_PREFIX, oinfo->oobavail, MTDSWAP_OOBSIZE); -+ MTDSWAP_PREFIX, mtd->oobavail, MTDSWAP_OOBSIZE); - return; - } - ---- a/drivers/mtd/nand/Kconfig -+++ b/drivers/mtd/nand/Kconfig -@@ -55,7 +55,7 @@ config MTD_NAND_DENALI_PCI - config MTD_NAND_DENALI_DT - tristate "Support Denali NAND controller as a DT device" - select MTD_NAND_DENALI -- depends on HAS_DMA && HAVE_CLK -+ depends on HAS_DMA && HAVE_CLK && OF - help - Enable the driver for NAND flash on platforms using a Denali NAND - controller as a DT device. -@@ -74,6 +74,7 @@ config MTD_NAND_DENALI_SCRATCH_REG_ADDR - config MTD_NAND_GPIO - tristate "GPIO assisted NAND Flash driver" - depends on GPIOLIB || COMPILE_TEST -+ depends on HAS_IOMEM - help - This enables a NAND flash driver where control signals are - connected to GPIO pins, and commands and data are communicated -@@ -310,6 +311,7 @@ config MTD_NAND_CAFE - config MTD_NAND_CS553X - tristate "NAND support for CS5535/CS5536 (AMD Geode companion chip)" - depends on X86_32 -+ depends on !UML && HAS_IOMEM - help - The CS553x companion chips for the AMD Geode processor - include NAND flash controllers with built-in hardware ECC -@@ -463,6 +465,7 @@ config MTD_NAND_MPC5121_NFC - config MTD_NAND_VF610_NFC - tristate "Support for Freescale NFC for VF610/MPC5125" - depends on (SOC_VF610 || COMPILE_TEST) -+ depends on HAS_IOMEM - help - Enables support for NAND Flash Controller on some Freescale - processors like the VF610, MPC5125, MCF54418 or Kinetis K70. -@@ -480,7 +483,7 @@ config MTD_NAND_MXC - - config MTD_NAND_SH_FLCTL - tristate "Support for NAND on Renesas SuperH FLCTL" -- depends on SUPERH || ARCH_SHMOBILE || COMPILE_TEST -+ depends on SUPERH || COMPILE_TEST - depends on HAS_IOMEM - depends on HAS_DMA - help -@@ -519,6 +522,13 @@ config MTD_NAND_JZ4740 - help - Enables support for NAND Flash on JZ4740 SoC based boards. - -+config MTD_NAND_JZ4780 -+ tristate "Support for NAND on JZ4780 SoC" -+ depends on MACH_JZ4780 && JZ4780_NEMC -+ help -+ Enables support for NAND Flash connected to the NEMC on JZ4780 SoC -+ based boards, using the BCH controller for hardware error correction. -+ - config MTD_NAND_FSMC - tristate "Support for NAND on ST Micros FSMC" - depends on PLAT_SPEAR || ARCH_NOMADIK || ARCH_U8500 || MACH_U300 -@@ -546,4 +556,11 @@ config MTD_NAND_HISI504 - help - Enables support for NAND controller on Hisilicon SoC Hip04. - -+config MTD_NAND_QCOM -+ tristate "Support for NAND on QCOM SoCs" -+ depends on ARCH_QCOM -+ help -+ Enables support for NAND flash chips on SoCs containing the EBI2 NAND -+ controller. This controller is found on IPQ806x SoC. -+ - endif # MTD_NAND ---- a/drivers/mtd/nand/Makefile -+++ b/drivers/mtd/nand/Makefile -@@ -49,11 +49,13 @@ obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mp - obj-$(CONFIG_MTD_NAND_VF610_NFC) += vf610_nfc.o - obj-$(CONFIG_MTD_NAND_RICOH) += r852.o - obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o -+obj-$(CONFIG_MTD_NAND_JZ4780) += jz4780_nand.o jz4780_bch.o - obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/ - obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o - obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/ - obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o - obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o - obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/ -+obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o - - nand-objs := nand_base.o nand_bbt.o nand_timings.o ---- a/drivers/mtd/nand/nand_base.c -+++ b/drivers/mtd/nand/nand_base.c -@@ -48,50 +48,6 @@ - #include <linux/mtd/partitions.h> - #include <linux/of_mtd.h> - --/* Define default oob placement schemes for large and small page devices */ --static struct nand_ecclayout nand_oob_8 = { -- .eccbytes = 3, -- .eccpos = {0, 1, 2}, -- .oobfree = { -- {.offset = 3, -- .length = 2}, -- {.offset = 6, -- .length = 2} } --}; -- --static struct nand_ecclayout nand_oob_16 = { -- .eccbytes = 6, -- .eccpos = {0, 1, 2, 3, 6, 7}, -- .oobfree = { -- {.offset = 8, -- . length = 8} } --}; -- --static struct nand_ecclayout nand_oob_64 = { -- .eccbytes = 24, -- .eccpos = { -- 40, 41, 42, 43, 44, 45, 46, 47, -- 48, 49, 50, 51, 52, 53, 54, 55, -- 56, 57, 58, 59, 60, 61, 62, 63}, -- .oobfree = { -- {.offset = 2, -- .length = 38} } --}; -- --static struct nand_ecclayout nand_oob_128 = { -- .eccbytes = 48, -- .eccpos = { -- 80, 81, 82, 83, 84, 85, 86, 87, -- 88, 89, 90, 91, 92, 93, 94, 95, -- 96, 97, 98, 99, 100, 101, 102, 103, -- 104, 105, 106, 107, 108, 109, 110, 111, -- 112, 113, 114, 115, 116, 117, 118, 119, -- 120, 121, 122, 123, 124, 125, 126, 127}, -- .oobfree = { -- {.offset = 2, -- .length = 78} } --}; -- - static int nand_get_device(struct mtd_info *mtd, int new_state); - - static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, -@@ -103,10 +59,96 @@ static int nand_do_write_oob(struct mtd_ - */ - DEFINE_LED_TRIGGER(nand_led_trigger); - -+/* Define default oob placement schemes for large and small page devices */ -+static int nand_ooblayout_ecc_sp(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobregion) -+{ -+ struct nand_chip *chip = mtd_to_nand(mtd); -+ struct nand_ecc_ctrl *ecc = &chip->ecc; -+ -+ if (section > 1) -+ return -ERANGE; -+ -+ if (!section) { -+ oobregion->offset = 0; -+ oobregion->length = 4; -+ } else { -+ oobregion->offset = 6; -+ oobregion->length = ecc->total - 4; -+ } -+ -+ return 0; -+} -+ -+static int nand_ooblayout_free_sp(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobregion) -+{ -+ if (section > 1) -+ return -ERANGE; -+ -+ if (mtd->oobsize == 16) { -+ if (section) -+ return -ERANGE; -+ -+ oobregion->length = 8; -+ oobregion->offset = 8; -+ } else { -+ oobregion->length = 2; -+ if (!section) -+ oobregion->offset = 3; -+ else -+ oobregion->offset = 6; -+ } -+ -+ return 0; -+} -+ -+const struct mtd_ooblayout_ops nand_ooblayout_sp_ops = { -+ .ecc = nand_ooblayout_ecc_sp, -+ .free = nand_ooblayout_free_sp, -+}; -+EXPORT_SYMBOL_GPL(nand_ooblayout_sp_ops); -+ -+static int nand_ooblayout_ecc_lp(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobregion) -+{ -+ struct nand_chip *chip = mtd_to_nand(mtd); -+ struct nand_ecc_ctrl *ecc = &chip->ecc; -+ -+ if (section) -+ return -ERANGE; -+ -+ oobregion->length = ecc->total; -+ oobregion->offset = mtd->oobsize - oobregion->length; -+ -+ return 0; -+} -+ -+static int nand_ooblayout_free_lp(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobregion) -+{ -+ struct nand_chip *chip = mtd_to_nand(mtd); -+ struct nand_ecc_ctrl *ecc = &chip->ecc; -+ -+ if (section) -+ return -ERANGE; -+ -+ oobregion->length = mtd->oobsize - ecc->total - 2; -+ oobregion->offset = 2; -+ -+ return 0; -+} -+ -+const struct mtd_ooblayout_ops nand_ooblayout_lp_ops = { -+ .ecc = nand_ooblayout_ecc_lp, -+ .free = nand_ooblayout_free_lp, -+}; -+EXPORT_SYMBOL_GPL(nand_ooblayout_lp_ops); -+ - static int check_offs_len(struct mtd_info *mtd, - loff_t ofs, uint64_t len) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - int ret = 0; - - /* Start address must align on block boundary */ -@@ -132,7 +174,7 @@ static int check_offs_len(struct mtd_inf - */ - static void nand_release_device(struct mtd_info *mtd) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - /* Release the controller and the chip */ - spin_lock(&chip->controller->lock); -@@ -150,7 +192,7 @@ static void nand_release_device(struct m - */ - static uint8_t nand_read_byte(struct mtd_info *mtd) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - return readb(chip->IO_ADDR_R); - } - -@@ -163,7 +205,7 @@ static uint8_t nand_read_byte(struct mtd - */ - static uint8_t nand_read_byte16(struct mtd_info *mtd) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); - } - -@@ -175,7 +217,7 @@ static uint8_t nand_read_byte16(struct m - */ - static u16 nand_read_word(struct mtd_info *mtd) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - return readw(chip->IO_ADDR_R); - } - -@@ -188,7 +230,7 @@ static u16 nand_read_word(struct mtd_inf - */ - static void nand_select_chip(struct mtd_info *mtd, int chipnr) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - switch (chipnr) { - case -1: -@@ -211,7 +253,7 @@ static void nand_select_chip(struct mtd_ - */ - static void nand_write_byte(struct mtd_info *mtd, uint8_t byte) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - chip->write_buf(mtd, &byte, 1); - } -@@ -225,7 +267,7 @@ static void nand_write_byte(struct mtd_i - */ - static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - uint16_t word = byte; - - /* -@@ -257,7 +299,7 @@ static void nand_write_byte16(struct mtd - */ - static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - iowrite8_rep(chip->IO_ADDR_W, buf, len); - } -@@ -272,7 +314,7 @@ static void nand_write_buf(struct mtd_in - */ - static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - ioread8_rep(chip->IO_ADDR_R, buf, len); - } -@@ -287,7 +329,7 @@ static void nand_read_buf(struct mtd_inf - */ - static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - u16 *p = (u16 *) buf; - - iowrite16_rep(chip->IO_ADDR_W, p, len >> 1); -@@ -303,7 +345,7 @@ static void nand_write_buf16(struct mtd_ - */ - static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - u16 *p = (u16 *) buf; - - ioread16_rep(chip->IO_ADDR_R, p, len >> 1); -@@ -313,14 +355,13 @@ static void nand_read_buf16(struct mtd_i - * nand_block_bad - [DEFAULT] Read bad block marker from the chip - * @mtd: MTD device structure - * @ofs: offset from device start -- * @getchip: 0, if the chip is already selected - * - * Check, if the block is bad. - */ --static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) -+static int nand_block_bad(struct mtd_info *mtd, loff_t ofs) - { -- int page, chipnr, res = 0, i = 0; -- struct nand_chip *chip = mtd->priv; -+ int page, res = 0, i = 0; -+ struct nand_chip *chip = mtd_to_nand(mtd); - u16 bad; - - if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) -@@ -328,15 +369,6 @@ static int nand_block_bad(struct mtd_inf - - page = (int)(ofs >> chip->page_shift) & chip->pagemask; - -- if (getchip) { -- chipnr = (int)(ofs >> chip->chip_shift); -- -- nand_get_device(mtd, FL_READING); -- -- /* Select the NAND device */ -- chip->select_chip(mtd, chipnr); -- } -- - do { - if (chip->options & NAND_BUSWIDTH_16) { - chip->cmdfunc(mtd, NAND_CMD_READOOB, -@@ -361,11 +393,6 @@ static int nand_block_bad(struct mtd_inf - i++; - } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE)); - -- if (getchip) { -- chip->select_chip(mtd, -1); -- nand_release_device(mtd); -- } -- - return res; - } - -@@ -380,7 +407,7 @@ static int nand_block_bad(struct mtd_inf - */ - static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - struct mtd_oob_ops ops; - uint8_t buf[2] = { 0, 0 }; - int ret = 0, res, i = 0; -@@ -430,7 +457,7 @@ static int nand_default_block_markbad(st - */ - static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - int res, ret = 0; - - if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) { -@@ -471,7 +498,7 @@ static int nand_block_markbad_lowlevel(s - */ - static int nand_check_wp(struct mtd_info *mtd) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - /* Broken xD cards report WP despite being writable */ - if (chip->options & NAND_BROKEN_XD) -@@ -491,7 +518,7 @@ static int nand_check_wp(struct mtd_info - */ - static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - if (!chip->bbt) - return 0; -@@ -503,19 +530,17 @@ static int nand_block_isreserved(struct - * nand_block_checkbad - [GENERIC] Check if a block is marked bad - * @mtd: MTD device structure - * @ofs: offset from device start -- * @getchip: 0, if the chip is already selected - * @allowbbt: 1, if its allowed to access the bbt area - * - * Check, if the block is bad. Either by reading the bad block table or - * calling of the scan function. - */ --static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, -- int allowbbt) -+static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - if (!chip->bbt) -- return chip->block_bad(mtd, ofs, getchip); -+ return chip->block_bad(mtd, ofs); - - /* Return info from the table */ - return nand_isbad_bbt(mtd, ofs, allowbbt); -@@ -531,7 +556,7 @@ static int nand_block_checkbad(struct mt - */ - static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - int i; - - /* Wait for the device to get ready */ -@@ -551,7 +576,7 @@ static void panic_nand_wait_ready(struct - */ - void nand_wait_ready(struct mtd_info *mtd) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - unsigned long timeo = 400; - - if (in_interrupt() || oops_in_progress) -@@ -566,8 +591,8 @@ void nand_wait_ready(struct mtd_info *mt - cond_resched(); - } while (time_before(jiffies, timeo)); - -- pr_warn_ratelimited( -- "timeout while waiting for chip to become ready\n"); -+ if (!chip->dev_ready(mtd)) -+ pr_warn_ratelimited("timeout while waiting for chip to become ready\n"); - out: - led_trigger_event(nand_led_trigger, LED_OFF); - } -@@ -582,7 +607,7 @@ EXPORT_SYMBOL_GPL(nand_wait_ready); - */ - static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo) - { -- register struct nand_chip *chip = mtd->priv; -+ register struct nand_chip *chip = mtd_to_nand(mtd); - - timeo = jiffies + msecs_to_jiffies(timeo); - do { -@@ -605,7 +630,7 @@ static void nand_wait_status_ready(struc - static void nand_command(struct mtd_info *mtd, unsigned int command, - int column, int page_addr) - { -- register struct nand_chip *chip = mtd->priv; -+ register struct nand_chip *chip = mtd_to_nand(mtd); - int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; - - /* Write out the command to the device */ -@@ -708,7 +733,7 @@ static void nand_command(struct mtd_info - static void nand_command_lp(struct mtd_info *mtd, unsigned int command, - int column, int page_addr) - { -- register struct nand_chip *chip = mtd->priv; -+ register struct nand_chip *chip = mtd_to_nand(mtd); - - /* Emulate NAND_CMD_READOOB */ - if (command == NAND_CMD_READOOB) { -@@ -832,7 +857,7 @@ static void panic_nand_get_device(struct - static int - nand_get_device(struct mtd_info *mtd, int new_state) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - spinlock_t *lock = &chip->controller->lock; - wait_queue_head_t *wq = &chip->controller->wq; - DECLARE_WAITQUEUE(wait, current); -@@ -952,7 +977,7 @@ static int __nand_unlock(struct mtd_info - { - int ret = 0; - int status, page; -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - /* Submit address of first page to unlock */ - page = ofs >> chip->page_shift; -@@ -987,7 +1012,7 @@ int nand_unlock(struct mtd_info *mtd, lo - { - int ret = 0; - int chipnr; -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - pr_debug("%s: start = 0x%012llx, len = %llu\n", - __func__, (unsigned long long)ofs, len); -@@ -1050,7 +1075,7 @@ int nand_lock(struct mtd_info *mtd, loff - { - int ret = 0; - int chipnr, status, page; -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - pr_debug("%s: start = 0x%012llx, len = %llu\n", - __func__, (unsigned long long)ofs, len); -@@ -1309,13 +1334,12 @@ static int nand_read_page_raw_syndrome(s - static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, - uint8_t *buf, int oob_required, int page) - { -- int i, eccsize = chip->ecc.size; -+ int i, eccsize = chip->ecc.size, ret; - int eccbytes = chip->ecc.bytes; - int eccsteps = chip->ecc.steps; - uint8_t *p = buf; - uint8_t *ecc_calc = chip->buffers->ecccalc; - uint8_t *ecc_code = chip->buffers->ecccode; -- uint32_t *eccpos = chip->ecc.layout->eccpos; - unsigned int max_bitflips = 0; - - chip->ecc.read_page_raw(mtd, chip, buf, 1, page); -@@ -1323,8 +1347,10 @@ static int nand_read_page_swecc(struct m - for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) - chip->ecc.calculate(mtd, p, &ecc_calc[i]); - -- for (i = 0; i < chip->ecc.total; i++) -- ecc_code[i] = chip->oob_poi[eccpos[i]]; -+ ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, -+ chip->ecc.total); -+ if (ret) -+ return ret; - - eccsteps = chip->ecc.steps; - p = buf; -@@ -1356,14 +1382,14 @@ static int nand_read_subpage(struct mtd_ - uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi, - int page) - { -- int start_step, end_step, num_steps; -- uint32_t *eccpos = chip->ecc.layout->eccpos; -+ int start_step, end_step, num_steps, ret; - uint8_t *p; - int data_col_addr, i, gaps = 0; - int datafrag_len, eccfrag_len, aligned_len, aligned_pos; - int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; -- int index; -+ int index, section = 0; - unsigned int max_bitflips = 0; -+ struct mtd_oob_region oobregion = { }; - - /* Column address within the page aligned to ECC size (256bytes) */ - start_step = data_offs / chip->ecc.size; -@@ -1391,12 +1417,13 @@ static int nand_read_subpage(struct mtd_ - * The performance is faster if we position offsets according to - * ecc.pos. Let's make sure that there are no gaps in ECC positions. - */ -- for (i = 0; i < eccfrag_len - 1; i++) { -- if (eccpos[i + index] + 1 != eccpos[i + index + 1]) { -- gaps = 1; -- break; -- } -- } -+ ret = mtd_ooblayout_find_eccregion(mtd, index, §ion, &oobregion); -+ if (ret) -+ return ret; -+ -+ if (oobregion.length < eccfrag_len) -+ gaps = 1; -+ - if (gaps) { - chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); - chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); -@@ -1405,20 +1432,23 @@ static int nand_read_subpage(struct mtd_ - * Send the command to read the particular ECC bytes take care - * about buswidth alignment in read_buf. - */ -- aligned_pos = eccpos[index] & ~(busw - 1); -+ aligned_pos = oobregion.offset & ~(busw - 1); - aligned_len = eccfrag_len; -- if (eccpos[index] & (busw - 1)) -+ if (oobregion.offset & (busw - 1)) - aligned_len++; -- if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1)) -+ if ((oobregion.offset + (num_steps * chip->ecc.bytes)) & -+ (busw - 1)) - aligned_len++; - - chip->cmdfunc(mtd, NAND_CMD_RNDOUT, -- mtd->writesize + aligned_pos, -1); -+ mtd->writesize + aligned_pos, -1); - chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len); - } - -- for (i = 0; i < eccfrag_len; i++) -- chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]]; -+ ret = mtd_ooblayout_get_eccbytes(mtd, chip->buffers->ecccode, -+ chip->oob_poi, index, eccfrag_len); -+ if (ret) -+ return ret; - - p = bufpoi + data_col_addr; - for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { -@@ -1426,6 +1456,16 @@ static int nand_read_subpage(struct mtd_ - - stat = chip->ecc.correct(mtd, p, - &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); -+ if (stat == -EBADMSG && -+ (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { -+ /* check for empty pages with bitflips */ -+ stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, -+ &chip->buffers->ecccode[i], -+ chip->ecc.bytes, -+ NULL, 0, -+ chip->ecc.strength); -+ } -+ - if (stat < 0) { - mtd->ecc_stats.failed++; - } else { -@@ -1449,13 +1489,12 @@ static int nand_read_subpage(struct mtd_ - static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, - uint8_t *buf, int oob_required, int page) - { -- int i, eccsize = chip->ecc.size; -+ int i, eccsize = chip->ecc.size, ret; - int eccbytes = chip->ecc.bytes; - int eccsteps = chip->ecc.steps; - uint8_t *p = buf; - uint8_t *ecc_calc = chip->buffers->ecccalc; - uint8_t *ecc_code = chip->buffers->ecccode; -- uint32_t *eccpos = chip->ecc.layout->eccpos; - unsigned int max_bitflips = 0; - - for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { -@@ -1465,8 +1504,10 @@ static int nand_read_page_hwecc(struct m - } - chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); - -- for (i = 0; i < chip->ecc.total; i++) -- ecc_code[i] = chip->oob_poi[eccpos[i]]; -+ ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, -+ chip->ecc.total); -+ if (ret) -+ return ret; - - eccsteps = chip->ecc.steps; - p = buf; -@@ -1475,6 +1516,15 @@ static int nand_read_page_hwecc(struct m - int stat; - - stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); -+ if (stat == -EBADMSG && -+ (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { -+ /* check for empty pages with bitflips */ -+ stat = nand_check_erased_ecc_chunk(p, eccsize, -+ &ecc_code[i], eccbytes, -+ NULL, 0, -+ chip->ecc.strength); -+ } -+ - if (stat < 0) { - mtd->ecc_stats.failed++; - } else { -@@ -1502,12 +1552,11 @@ static int nand_read_page_hwecc(struct m - static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, - struct nand_chip *chip, uint8_t *buf, int oob_required, int page) - { -- int i, eccsize = chip->ecc.size; -+ int i, eccsize = chip->ecc.size, ret; - int eccbytes = chip->ecc.bytes; - int eccsteps = chip->ecc.steps; - uint8_t *p = buf; - uint8_t *ecc_code = chip->buffers->ecccode; -- uint32_t *eccpos = chip->ecc.layout->eccpos; - uint8_t *ecc_calc = chip->buffers->ecccalc; - unsigned int max_bitflips = 0; - -@@ -1516,8 +1565,10 @@ static int nand_read_page_hwecc_oob_firs - chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); - chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); - -- for (i = 0; i < chip->ecc.total; i++) -- ecc_code[i] = chip->oob_poi[eccpos[i]]; -+ ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, -+ chip->ecc.total); -+ if (ret) -+ return ret; - - for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { - int stat; -@@ -1527,6 +1578,15 @@ static int nand_read_page_hwecc_oob_firs - chip->ecc.calculate(mtd, p, &ecc_calc[i]); - - stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); -+ if (stat == -EBADMSG && -+ (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { -+ /* check for empty pages with bitflips */ -+ stat = nand_check_erased_ecc_chunk(p, eccsize, -+ &ecc_code[i], eccbytes, -+ NULL, 0, -+ chip->ecc.strength); -+ } -+ - if (stat < 0) { - mtd->ecc_stats.failed++; - } else { -@@ -1554,6 +1614,7 @@ static int nand_read_page_syndrome(struc - int i, eccsize = chip->ecc.size; - int eccbytes = chip->ecc.bytes; - int eccsteps = chip->ecc.steps; -+ int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad; - uint8_t *p = buf; - uint8_t *oob = chip->oob_poi; - unsigned int max_bitflips = 0; -@@ -1573,19 +1634,29 @@ static int nand_read_page_syndrome(struc - chip->read_buf(mtd, oob, eccbytes); - stat = chip->ecc.correct(mtd, p, oob, NULL); - -- if (stat < 0) { -- mtd->ecc_stats.failed++; -- } else { -- mtd->ecc_stats.corrected += stat; -- max_bitflips = max_t(unsigned int, max_bitflips, stat); -- } -- - oob += eccbytes; - - if (chip->ecc.postpad) { - chip->read_buf(mtd, oob, chip->ecc.postpad); - oob += chip->ecc.postpad; - } -+ -+ if (stat == -EBADMSG && -+ (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { -+ /* check for empty pages with bitflips */ -+ stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, -+ oob - eccpadbytes, -+ eccpadbytes, -+ NULL, 0, -+ chip->ecc.strength); -+ } -+ -+ if (stat < 0) { -+ mtd->ecc_stats.failed++; -+ } else { -+ mtd->ecc_stats.corrected += stat; -+ max_bitflips = max_t(unsigned int, max_bitflips, stat); -+ } - } - - /* Calculate remaining oob bytes */ -@@ -1598,14 +1669,17 @@ static int nand_read_page_syndrome(struc - - /** - * nand_transfer_oob - [INTERN] Transfer oob to client buffer -- * @chip: nand chip structure -+ * @mtd: mtd info structure - * @oob: oob destination address - * @ops: oob ops structure - * @len: size of oob to transfer - */ --static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, -+static uint8_t *nand_transfer_oob(struct mtd_info *mtd, uint8_t *oob, - struct mtd_oob_ops *ops, size_t len) - { -+ struct nand_chip *chip = mtd_to_nand(mtd); -+ int ret; -+ - switch (ops->mode) { - - case MTD_OPS_PLACE_OOB: -@@ -1613,31 +1687,12 @@ static uint8_t *nand_transfer_oob(struct - memcpy(oob, chip->oob_poi + ops->ooboffs, len); - return oob + len; - -- case MTD_OPS_AUTO_OOB: { -- struct nand_oobfree *free = chip->ecc.layout->oobfree; -- uint32_t boffs = 0, roffs = ops->ooboffs; -- size_t bytes = 0; -- -- for (; free->length && len; free++, len -= bytes) { -- /* Read request not from offset 0? */ -- if (unlikely(roffs)) { -- if (roffs >= free->length) { -- roffs -= free->length; -- continue; -- } -- boffs = free->offset + roffs; -- bytes = min_t(size_t, len, -- (free->length - roffs)); -- roffs = 0; -- } else { -- bytes = min_t(size_t, len, free->length); -- boffs = free->offset; -- } -- memcpy(oob, chip->oob_poi + boffs, bytes); -- oob += bytes; -- } -- return oob; -- } -+ case MTD_OPS_AUTO_OOB: -+ ret = mtd_ooblayout_get_databytes(mtd, oob, chip->oob_poi, -+ ops->ooboffs, len); -+ BUG_ON(ret); -+ return oob + len; -+ - default: - BUG(); - } -@@ -1655,7 +1710,7 @@ static uint8_t *nand_transfer_oob(struct - */ - static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - pr_debug("setting READ RETRY mode %d\n", retry_mode); - -@@ -1680,12 +1735,11 @@ static int nand_do_read_ops(struct mtd_i - struct mtd_oob_ops *ops) - { - int chipnr, page, realpage, col, bytes, aligned, oob_required; -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - int ret = 0; - uint32_t readlen = ops->len; - uint32_t oobreadlen = ops->ooblen; -- uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ? -- mtd->oobavail : mtd->oobsize; -+ uint32_t max_oobsize = mtd_oobavail(mtd, ops); - - uint8_t *bufpoi, *oob, *buf; - int use_bufpoi; -@@ -1772,7 +1826,7 @@ read_retry: - int toread = min(oobreadlen, max_oobsize); - - if (toread) { -- oob = nand_transfer_oob(chip, -+ oob = nand_transfer_oob(mtd, - oob, ops, toread); - oobreadlen -= toread; - } -@@ -2025,7 +2079,7 @@ static int nand_do_read_oob(struct mtd_i - { - unsigned int max_bitflips = 0; - int page, realpage, chipnr; -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - struct mtd_ecc_stats stats; - int readlen = ops->ooblen; - int len; -@@ -2037,10 +2091,7 @@ static int nand_do_read_oob(struct mtd_i - - stats = mtd->ecc_stats; - -- if (ops->mode == MTD_OPS_AUTO_OOB) -- len = chip->ecc.layout->oobavail; -- else -- len = mtd->oobsize; -+ len = mtd_oobavail(mtd, ops); - - if (unlikely(ops->ooboffs >= len)) { - pr_debug("%s: attempt to start read outside oob\n", -@@ -2074,7 +2125,7 @@ static int nand_do_read_oob(struct mtd_i - break; - - len = min(len, readlen); -- buf = nand_transfer_oob(chip, buf, ops, len); -+ buf = nand_transfer_oob(mtd, buf, ops, len); - - if (chip->options & NAND_NEED_READRDY) { - /* Apply delay or wait for ready/busy pin */ -@@ -2235,19 +2286,20 @@ static int nand_write_page_swecc(struct - const uint8_t *buf, int oob_required, - int page) - { -- int i, eccsize = chip->ecc.size; -+ int i, eccsize = chip->ecc.size, ret; - int eccbytes = chip->ecc.bytes; - int eccsteps = chip->ecc.steps; - uint8_t *ecc_calc = chip->buffers->ecccalc; - const uint8_t *p = buf; -- uint32_t *eccpos = chip->ecc.layout->eccpos; - - /* Software ECC calculation */ - for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) - chip->ecc.calculate(mtd, p, &ecc_calc[i]); - -- for (i = 0; i < chip->ecc.total; i++) -- chip->oob_poi[eccpos[i]] = ecc_calc[i]; -+ ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, -+ chip->ecc.total); -+ if (ret) -+ return ret; - - return chip->ecc.write_page_raw(mtd, chip, buf, 1, page); - } -@@ -2264,12 +2316,11 @@ static int nand_write_page_hwecc(struct - const uint8_t *buf, int oob_required, - int page) - { -- int i, eccsize = chip->ecc.size; -+ int i, eccsize = chip->ecc.size, ret; - int eccbytes = chip->ecc.bytes; - int eccsteps = chip->ecc.steps; - uint8_t *ecc_calc = chip->buffers->ecccalc; - const uint8_t *p = buf; -- uint32_t *eccpos = chip->ecc.layout->eccpos; - - for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { - chip->ecc.hwctl(mtd, NAND_ECC_WRITE); -@@ -2277,8 +2328,10 @@ static int nand_write_page_hwecc(struct - chip->ecc.calculate(mtd, p, &ecc_calc[i]); - } - -- for (i = 0; i < chip->ecc.total; i++) -- chip->oob_poi[eccpos[i]] = ecc_calc[i]; -+ ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, -+ chip->ecc.total); -+ if (ret) -+ return ret; - - chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); - -@@ -2306,11 +2359,10 @@ static int nand_write_subpage_hwecc(stru - int ecc_size = chip->ecc.size; - int ecc_bytes = chip->ecc.bytes; - int ecc_steps = chip->ecc.steps; -- uint32_t *eccpos = chip->ecc.layout->eccpos; - uint32_t start_step = offset / ecc_size; - uint32_t end_step = (offset + data_len - 1) / ecc_size; - int oob_bytes = mtd->oobsize / ecc_steps; -- int step, i; -+ int step, ret; - - for (step = 0; step < ecc_steps; step++) { - /* configure controller for WRITE access */ -@@ -2338,8 +2390,10 @@ static int nand_write_subpage_hwecc(stru - /* copy calculated ECC for whole page to chip->buffer->oob */ - /* this include masked-value(0xFF) for unwritten subpages */ - ecc_calc = chip->buffers->ecccalc; -- for (i = 0; i < chip->ecc.total; i++) -- chip->oob_poi[eccpos[i]] = ecc_calc[i]; -+ ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, -+ chip->ecc.total); -+ if (ret) -+ return ret; - - /* write OOB buffer to NAND device */ - chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); -@@ -2475,7 +2529,8 @@ static int nand_write_page(struct mtd_in - static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len, - struct mtd_oob_ops *ops) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); -+ int ret; - - /* - * Initialise to all 0xFF, to avoid the possibility of left over OOB -@@ -2490,31 +2545,12 @@ static uint8_t *nand_fill_oob(struct mtd - memcpy(chip->oob_poi + ops->ooboffs, oob, len); - return oob + len; - -- case MTD_OPS_AUTO_OOB: { -- struct nand_oobfree *free = chip->ecc.layout->oobfree; -- uint32_t boffs = 0, woffs = ops->ooboffs; -- size_t bytes = 0; -- -- for (; free->length && len; free++, len -= bytes) { -- /* Write request not from offset 0? */ -- if (unlikely(woffs)) { -- if (woffs >= free->length) { -- woffs -= free->length; -- continue; -- } -- boffs = free->offset + woffs; -- bytes = min_t(size_t, len, -- (free->length - woffs)); -- woffs = 0; -- } else { -- bytes = min_t(size_t, len, free->length); -- boffs = free->offset; -- } -- memcpy(chip->oob_poi + boffs, oob, bytes); -- oob += bytes; -- } -- return oob; -- } -+ case MTD_OPS_AUTO_OOB: -+ ret = mtd_ooblayout_set_databytes(mtd, oob, chip->oob_poi, -+ ops->ooboffs, len); -+ BUG_ON(ret); -+ return oob + len; -+ - default: - BUG(); - } -@@ -2535,12 +2571,11 @@ static int nand_do_write_ops(struct mtd_ - struct mtd_oob_ops *ops) - { - int chipnr, realpage, page, blockmask, column; -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - uint32_t writelen = ops->len; - - uint32_t oobwritelen = ops->ooblen; -- uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ? -- mtd->oobavail : mtd->oobsize; -+ uint32_t oobmaxlen = mtd_oobavail(mtd, ops); - - uint8_t *oob = ops->oobbuf; - uint8_t *buf = ops->datbuf; -@@ -2665,7 +2700,7 @@ err_out: - static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, - size_t *retlen, const uint8_t *buf) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - int chipnr = (int)(to >> chip->chip_shift); - struct mtd_oob_ops ops; - int ret; -@@ -2728,15 +2763,12 @@ static int nand_do_write_oob(struct mtd_ - struct mtd_oob_ops *ops) - { - int chipnr, page, status, len; -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - pr_debug("%s: to = 0x%08x, len = %i\n", - __func__, (unsigned int)to, (int)ops->ooblen); - -- if (ops->mode == MTD_OPS_AUTO_OOB) -- len = chip->ecc.layout->oobavail; -- else -- len = mtd->oobsize; -+ len = mtd_oobavail(mtd, ops); - - /* Do not allow write past end of page */ - if ((ops->ooboffs + ops->ooblen) > len) { -@@ -2853,7 +2885,7 @@ out: - */ - static int single_erase(struct mtd_info *mtd, int page) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - /* Send commands to erase a block */ - chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); - chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); -@@ -2885,7 +2917,7 @@ int nand_erase_nand(struct mtd_info *mtd - int allowbbt) - { - int page, status, pages_per_block, ret, chipnr; -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - loff_t len; - - pr_debug("%s: start = 0x%012llx, len = %llu\n", -@@ -2924,7 +2956,7 @@ int nand_erase_nand(struct mtd_info *mtd - while (len) { - /* Check if we have a bad block, we do not erase bad blocks! */ - if (nand_block_checkbad(mtd, ((loff_t) page) << -- chip->page_shift, 0, allowbbt)) { -+ chip->page_shift, allowbbt)) { - pr_warn("%s: attempt to erase a bad block at page 0x%08x\n", - __func__, page); - instr->state = MTD_ERASE_FAILED; -@@ -3011,7 +3043,20 @@ static void nand_sync(struct mtd_info *m - */ - static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) - { -- return nand_block_checkbad(mtd, offs, 1, 0); -+ struct nand_chip *chip = mtd_to_nand(mtd); -+ int chipnr = (int)(offs >> chip->chip_shift); -+ int ret; -+ -+ /* Select the NAND device */ -+ nand_get_device(mtd, FL_READING); -+ chip->select_chip(mtd, chipnr); -+ -+ ret = nand_block_checkbad(mtd, offs, 0); -+ -+ chip->select_chip(mtd, -1); -+ nand_release_device(mtd); -+ -+ return ret; - } - - /** -@@ -3100,7 +3145,7 @@ static int nand_suspend(struct mtd_info - */ - static void nand_resume(struct mtd_info *mtd) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - if (chip->state == FL_PM_SUSPENDED) - nand_release_device(mtd); -@@ -3272,7 +3317,7 @@ ext_out: - - static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode}; - - return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY, -@@ -3943,10 +3988,13 @@ ident_done: - return type; - } - --static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, -- struct device_node *dn) -+static int nand_dt_init(struct nand_chip *chip) - { -- int ecc_mode, ecc_strength, ecc_step; -+ struct device_node *dn = nand_get_flash_node(chip); -+ int ecc_mode, ecc_algo, ecc_strength, ecc_step; -+ -+ if (!dn) -+ return 0; - - if (of_get_nand_bus_width(dn) == 16) - chip->options |= NAND_BUSWIDTH_16; -@@ -3955,6 +4003,7 @@ static int nand_dt_init(struct mtd_info - chip->bbt_options |= NAND_BBT_USE_FLASH; - - ecc_mode = of_get_nand_ecc_mode(dn); -+ ecc_algo = of_get_nand_ecc_algo(dn); - ecc_strength = of_get_nand_ecc_strength(dn); - ecc_step = of_get_nand_ecc_step_size(dn); - -@@ -3967,6 +4016,9 @@ static int nand_dt_init(struct mtd_info - if (ecc_mode >= 0) - chip->ecc.mode = ecc_mode; - -+ if (ecc_algo >= 0) -+ chip->ecc.algo = ecc_algo; -+ - if (ecc_strength >= 0) - chip->ecc.strength = ecc_strength; - -@@ -3990,15 +4042,16 @@ int nand_scan_ident(struct mtd_info *mtd - struct nand_flash_dev *table) - { - int i, nand_maf_id, nand_dev_id; -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - struct nand_flash_dev *type; - int ret; - -- if (chip->flash_node) { -- ret = nand_dt_init(mtd, chip, chip->flash_node); -- if (ret) -- return ret; -- } -+ ret = nand_dt_init(chip); -+ if (ret) -+ return ret; -+ -+ if (!mtd->name && mtd->dev.parent) -+ mtd->name = dev_name(mtd->dev.parent); - - if (!mtd->name && mtd->dev.parent) - mtd->name = dev_name(mtd->dev.parent); -@@ -4061,7 +4114,7 @@ EXPORT_SYMBOL(nand_scan_ident); - */ - static bool nand_ecc_strength_good(struct mtd_info *mtd) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - struct nand_ecc_ctrl *ecc = &chip->ecc; - int corr, ds_corr; - -@@ -4089,10 +4142,10 @@ static bool nand_ecc_strength_good(struc - */ - int nand_scan_tail(struct mtd_info *mtd) - { -- int i; -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - struct nand_ecc_ctrl *ecc = &chip->ecc; - struct nand_buffers *nbuf; -+ int ret; - - /* New bad blocks should be marked in OOB, flash-based BBT, or both */ - BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) && -@@ -4119,19 +4172,15 @@ int nand_scan_tail(struct mtd_info *mtd) - /* - * If no default placement scheme is given, select an appropriate one. - */ -- if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) { -+ if (!mtd->ooblayout && (ecc->mode != NAND_ECC_SOFT_BCH)) { - switch (mtd->oobsize) { - case 8: -- ecc->layout = &nand_oob_8; -- break; - case 16: -- ecc->layout = &nand_oob_16; -+ mtd_set_ooblayout(mtd, &nand_ooblayout_sp_ops); - break; - case 64: -- ecc->layout = &nand_oob_64; -- break; - case 128: -- ecc->layout = &nand_oob_128; -+ mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops); - break; - default: - pr_warn("No oob scheme defined for oobsize %d\n", -@@ -4174,7 +4223,7 @@ int nand_scan_tail(struct mtd_info *mtd) - ecc->write_oob = nand_write_oob_std; - if (!ecc->read_subpage) - ecc->read_subpage = nand_read_subpage; -- if (!ecc->write_subpage) -+ if (!ecc->write_subpage && ecc->hwctl && ecc->calculate) - ecc->write_subpage = nand_write_subpage_hwecc; - - case NAND_ECC_HW_SYNDROME: -@@ -4252,10 +4301,8 @@ int nand_scan_tail(struct mtd_info *mtd) - } - - /* See nand_bch_init() for details. */ -- ecc->bytes = DIV_ROUND_UP( -- ecc->strength * fls(8 * ecc->size), 8); -- ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes, -- &ecc->layout); -+ ecc->bytes = 0; -+ ecc->priv = nand_bch_init(mtd); - if (!ecc->priv) { - pr_warn("BCH ECC initialization failed!\n"); - BUG(); -@@ -4286,20 +4333,9 @@ int nand_scan_tail(struct mtd_info *mtd) - if (!ecc->write_oob_raw) - ecc->write_oob_raw = ecc->write_oob; - -- /* -- * The number of bytes available for a client to place data into -- * the out of band area. -- */ -- ecc->layout->oobavail = 0; -- for (i = 0; ecc->layout->oobfree[i].length -- && i < ARRAY_SIZE(ecc->layout->oobfree); i++) -- ecc->layout->oobavail += ecc->layout->oobfree[i].length; -- mtd->oobavail = ecc->layout->oobavail; -- -- /* ECC sanity check: warn if it's too weak */ -- if (!nand_ecc_strength_good(mtd)) -- pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n", -- mtd->name); -+ /* propagate ecc info to mtd_info */ -+ mtd->ecc_strength = ecc->strength; -+ mtd->ecc_step_size = ecc->size; - - /* - * Set the number of read / write steps for one page depending on ECC -@@ -4312,6 +4348,21 @@ int nand_scan_tail(struct mtd_info *mtd) - } - ecc->total = ecc->steps * ecc->bytes; - -+ /* -+ * The number of bytes available for a client to place data into -+ * the out of band area. -+ */ -+ ret = mtd_ooblayout_count_freebytes(mtd); -+ if (ret < 0) -+ ret = 0; -+ -+ mtd->oobavail = ret; -+ -+ /* ECC sanity check: warn if it's too weak */ -+ if (!nand_ecc_strength_good(mtd)) -+ pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n", -+ mtd->name); -+ - /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ - if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) { - switch (ecc->steps) { -@@ -4368,10 +4419,6 @@ int nand_scan_tail(struct mtd_info *mtd) - mtd->_block_markbad = nand_block_markbad; - mtd->writebufsize = mtd->writesize; - -- /* propagate ecc info to mtd_info */ -- mtd->ecclayout = ecc->layout; -- mtd->ecc_strength = ecc->strength; -- mtd->ecc_step_size = ecc->size; - /* - * Initialize bitflip_threshold to its default prior scan_bbt() call. - * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be -@@ -4427,7 +4474,7 @@ EXPORT_SYMBOL(nand_scan); - */ - void nand_release(struct mtd_info *mtd) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - if (chip->ecc.mode == NAND_ECC_SOFT_BCH) - nand_bch_free((struct nand_bch_control *)chip->ecc.priv); ---- a/drivers/mtd/nand/nand_bbt.c -+++ b/drivers/mtd/nand/nand_bbt.c -@@ -172,7 +172,7 @@ static int read_bbt(struct mtd_info *mtd - struct nand_bbt_descr *td, int offs) - { - int res, ret = 0, i, j, act = 0; -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - size_t retlen, len, totlen; - loff_t from; - int bits = td->options & NAND_BBT_NRBITS_MSK; -@@ -263,7 +263,7 @@ static int read_bbt(struct mtd_info *mtd - */ - static int read_abs_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td, int chip) - { -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - int res = 0, i; - - if (td->options & NAND_BBT_PERCHIP) { -@@ -388,7 +388,7 @@ static u32 bbt_get_ver_offs(struct mtd_i - static void read_abs_bbts(struct mtd_info *mtd, uint8_t *buf, - struct nand_bbt_descr *td, struct nand_bbt_descr *md) - { -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - - /* Read the primary version, if available */ - if (td->options & NAND_BBT_VERSION) { -@@ -454,7 +454,7 @@ static int scan_block_fast(struct mtd_in - static int create_bbt(struct mtd_info *mtd, uint8_t *buf, - struct nand_bbt_descr *bd, int chip) - { -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - int i, numblocks, numpages; - int startblock; - loff_t from; -@@ -523,7 +523,7 @@ static int create_bbt(struct mtd_info *m - */ - static int search_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td) - { -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - int i, chips; - int startblock, block, dir; - int scanlen = mtd->writesize + mtd->oobsize; -@@ -618,7 +618,7 @@ static int write_bbt(struct mtd_info *mt - struct nand_bbt_descr *td, struct nand_bbt_descr *md, - int chipsel) - { -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - struct erase_info einfo; - int i, res, chip = 0; - int bits, startblock, dir, page, offs, numblocks, sft, sftmsk; -@@ -819,7 +819,7 @@ static int write_bbt(struct mtd_info *mt - */ - static inline int nand_memory_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd) - { -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - - return create_bbt(mtd, this->buffers->databuf, bd, -1); - } -@@ -838,7 +838,7 @@ static inline int nand_memory_bbt(struct - static int check_create(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *bd) - { - int i, chips, writeops, create, chipsel, res, res2; -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - struct nand_bbt_descr *td = this->bbt_td; - struct nand_bbt_descr *md = this->bbt_md; - struct nand_bbt_descr *rd, *rd2; -@@ -962,7 +962,7 @@ static int check_create(struct mtd_info - */ - static void mark_bbt_region(struct mtd_info *mtd, struct nand_bbt_descr *td) - { -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - int i, j, chips, block, nrblocks, update; - uint8_t oldval; - -@@ -1022,7 +1022,7 @@ static void mark_bbt_region(struct mtd_i - */ - static void verify_bbt_descr(struct mtd_info *mtd, struct nand_bbt_descr *bd) - { -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - u32 pattern_len; - u32 bits; - u32 table_size; -@@ -1074,7 +1074,7 @@ static void verify_bbt_descr(struct mtd_ - */ - static int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd) - { -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - int len, res; - uint8_t *buf; - struct nand_bbt_descr *td = this->bbt_td; -@@ -1147,7 +1147,7 @@ err: - */ - static int nand_update_bbt(struct mtd_info *mtd, loff_t offs) - { -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - int len, res = 0; - int chip, chipsel; - uint8_t *buf; -@@ -1281,7 +1281,7 @@ static int nand_create_badblock_pattern( - */ - int nand_default_bbt(struct mtd_info *mtd) - { -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - int ret; - - /* Is a flash based bad block table requested? */ -@@ -1317,7 +1317,7 @@ int nand_default_bbt(struct mtd_info *mt - */ - int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs) - { -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - int block; - - block = (int)(offs >> this->bbt_erase_shift); -@@ -1332,7 +1332,7 @@ int nand_isreserved_bbt(struct mtd_info - */ - int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt) - { -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - int block, res; - - block = (int)(offs >> this->bbt_erase_shift); -@@ -1359,7 +1359,7 @@ int nand_isbad_bbt(struct mtd_info *mtd, - */ - int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs) - { -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - int block, ret = 0; - - block = (int)(offs >> this->bbt_erase_shift); -@@ -1373,5 +1373,3 @@ int nand_markbad_bbt(struct mtd_info *mt - - return ret; - } -- --EXPORT_SYMBOL(nand_scan_bbt); ---- a/drivers/mtd/nand/nand_bch.c -+++ b/drivers/mtd/nand/nand_bch.c -@@ -32,13 +32,11 @@ - /** - * struct nand_bch_control - private NAND BCH control structure - * @bch: BCH control structure -- * @ecclayout: private ecc layout for this BCH configuration - * @errloc: error location array - * @eccmask: XOR ecc mask, allows erased pages to be decoded as valid - */ - struct nand_bch_control { - struct bch_control *bch; -- struct nand_ecclayout ecclayout; - unsigned int *errloc; - unsigned char *eccmask; - }; -@@ -52,7 +50,7 @@ struct nand_bch_control { - int nand_bch_calculate_ecc(struct mtd_info *mtd, const unsigned char *buf, - unsigned char *code) - { -- const struct nand_chip *chip = mtd->priv; -+ const struct nand_chip *chip = mtd_to_nand(mtd); - struct nand_bch_control *nbc = chip->ecc.priv; - unsigned int i; - -@@ -79,7 +77,7 @@ EXPORT_SYMBOL(nand_bch_calculate_ecc); - int nand_bch_correct_data(struct mtd_info *mtd, unsigned char *buf, - unsigned char *read_ecc, unsigned char *calc_ecc) - { -- const struct nand_chip *chip = mtd->priv; -+ const struct nand_chip *chip = mtd_to_nand(mtd); - struct nand_bch_control *nbc = chip->ecc.priv; - unsigned int *errloc = nbc->errloc; - int i, count; -@@ -98,7 +96,7 @@ int nand_bch_correct_data(struct mtd_inf - } - } else if (count < 0) { - printk(KERN_ERR "ecc unrecoverable error\n"); -- count = -1; -+ count = -EBADMSG; - } - return count; - } -@@ -107,9 +105,6 @@ EXPORT_SYMBOL(nand_bch_correct_data); - /** - * nand_bch_init - [NAND Interface] Initialize NAND BCH error correction - * @mtd: MTD block structure -- * @eccsize: ecc block size in bytes -- * @eccbytes: ecc length in bytes -- * @ecclayout: output default layout - * - * Returns: - * a pointer to a new NAND BCH control structure, or NULL upon failure -@@ -123,14 +118,20 @@ EXPORT_SYMBOL(nand_bch_correct_data); - * @eccsize = 512 (thus, m=13 is the smallest integer such that 2^m-1 > 512*8) - * @eccbytes = 7 (7 bytes are required to store m*t = 13*4 = 52 bits) - */ --struct nand_bch_control * --nand_bch_init(struct mtd_info *mtd, unsigned int eccsize, unsigned int eccbytes, -- struct nand_ecclayout **ecclayout) -+struct nand_bch_control *nand_bch_init(struct mtd_info *mtd) - { -+ struct nand_chip *nand = mtd_to_nand(mtd); - unsigned int m, t, eccsteps, i; -- struct nand_ecclayout *layout; - struct nand_bch_control *nbc = NULL; - unsigned char *erased_page; -+ unsigned int eccsize = nand->ecc.size; -+ unsigned int eccbytes = nand->ecc.bytes; -+ unsigned int eccstrength = nand->ecc.strength; -+ -+ if (!eccbytes && eccstrength) { -+ eccbytes = DIV_ROUND_UP(eccstrength * fls(8 * eccsize), 8); -+ nand->ecc.bytes = eccbytes; -+ } - - if (!eccsize || !eccbytes) { - printk(KERN_WARNING "ecc parameters not supplied\n"); -@@ -158,7 +159,7 @@ nand_bch_init(struct mtd_info *mtd, unsi - eccsteps = mtd->writesize/eccsize; - - /* if no ecc placement scheme was provided, build one */ -- if (!*ecclayout) { -+ if (!mtd->ooblayout) { - - /* handle large page devices only */ - if (mtd->oobsize < 64) { -@@ -167,24 +168,7 @@ nand_bch_init(struct mtd_info *mtd, unsi - goto fail; - } - -- layout = &nbc->ecclayout; -- layout->eccbytes = eccsteps*eccbytes; -- -- /* reserve 2 bytes for bad block marker */ -- if (layout->eccbytes+2 > mtd->oobsize) { -- printk(KERN_WARNING "no suitable oob scheme available " -- "for oobsize %d eccbytes %u\n", mtd->oobsize, -- eccbytes); -- goto fail; -- } -- /* put ecc bytes at oob tail */ -- for (i = 0; i < layout->eccbytes; i++) -- layout->eccpos[i] = mtd->oobsize-layout->eccbytes+i; -- -- layout->oobfree[0].offset = 2; -- layout->oobfree[0].length = mtd->oobsize-2-layout->eccbytes; -- -- *ecclayout = layout; -+ mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops); - } - - /* sanity checks */ -@@ -192,7 +176,8 @@ nand_bch_init(struct mtd_info *mtd, unsi - printk(KERN_WARNING "eccsize %u is too large\n", eccsize); - goto fail; - } -- if ((*ecclayout)->eccbytes != (eccsteps*eccbytes)) { -+ -+ if (mtd_ooblayout_count_eccbytes(mtd) != (eccsteps*eccbytes)) { - printk(KERN_WARNING "invalid ecc layout\n"); - goto fail; - } -@@ -216,6 +201,9 @@ nand_bch_init(struct mtd_info *mtd, unsi - for (i = 0; i < eccbytes; i++) - nbc->eccmask[i] ^= 0xff; - -+ if (!eccstrength) -+ nand->ecc.strength = (eccbytes * 8) / fls(8 * eccsize); -+ - return nbc; - fail: - nand_bch_free(nbc); ---- a/drivers/mtd/nand/nand_ecc.c -+++ b/drivers/mtd/nand/nand_ecc.c -@@ -424,7 +424,7 @@ int nand_calculate_ecc(struct mtd_info * - unsigned char *code) - { - __nand_calculate_ecc(buf, -- ((struct nand_chip *)mtd->priv)->ecc.size, code); -+ mtd_to_nand(mtd)->ecc.size, code); - - return 0; - } -@@ -524,7 +524,7 @@ int nand_correct_data(struct mtd_info *m - unsigned char *read_ecc, unsigned char *calc_ecc) - { - return __nand_correct_data(buf, read_ecc, calc_ecc, -- ((struct nand_chip *)mtd->priv)->ecc.size); -+ mtd_to_nand(mtd)->ecc.size); - } - EXPORT_SYMBOL(nand_correct_data); - ---- a/drivers/mtd/nand/nand_ids.c -+++ b/drivers/mtd/nand/nand_ids.c -@@ -50,8 +50,8 @@ struct nand_flash_dev nand_flash_ids[] = - SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) }, - {"H27UCG8T2ATR-BC 64G 3.3V 8-bit", - { .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} }, -- SZ_8K, SZ_8K, SZ_2M, 0, 6, 640, NAND_ECC_INFO(40, SZ_1K), -- 4 }, -+ SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640, -+ NAND_ECC_INFO(40, SZ_1K), 4 }, - - LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS), - LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS), ---- a/drivers/mtd/nand/nandsim.c -+++ b/drivers/mtd/nand/nandsim.c -@@ -666,8 +666,8 @@ static char *get_partition_name(int i) - */ - static int init_nandsim(struct mtd_info *mtd) - { -- struct nand_chip *chip = mtd->priv; -- struct nandsim *ns = chip->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); -+ struct nandsim *ns = nand_get_controller_data(chip); - int i, ret = 0; - uint64_t remains; - uint64_t next_offset; -@@ -1908,7 +1908,8 @@ static void switch_state(struct nandsim - - static u_char ns_nand_read_byte(struct mtd_info *mtd) - { -- struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); -+ struct nandsim *ns = nand_get_controller_data(chip); - u_char outb = 0x00; - - /* Sanity and correctness checks */ -@@ -1969,7 +1970,8 @@ static u_char ns_nand_read_byte(struct m - - static void ns_nand_write_byte(struct mtd_info *mtd, u_char byte) - { -- struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); -+ struct nandsim *ns = nand_get_controller_data(chip); - - /* Sanity and correctness checks */ - if (!ns->lines.ce) { -@@ -2123,7 +2125,8 @@ static void ns_nand_write_byte(struct mt - - static void ns_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int bitmask) - { -- struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); -+ struct nandsim *ns = nand_get_controller_data(chip); - - ns->lines.cle = bitmask & NAND_CLE ? 1 : 0; - ns->lines.ale = bitmask & NAND_ALE ? 1 : 0; -@@ -2141,7 +2144,7 @@ static int ns_device_ready(struct mtd_in - - static uint16_t ns_nand_read_word(struct mtd_info *mtd) - { -- struct nand_chip *chip = (struct nand_chip *)mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - NS_DBG("read_word\n"); - -@@ -2150,7 +2153,8 @@ static uint16_t ns_nand_read_word(struct - - static void ns_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) - { -- struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); -+ struct nandsim *ns = nand_get_controller_data(chip); - - /* Check that chip is expecting data input */ - if (!(ns->state & STATE_DATAIN_MASK)) { -@@ -2177,7 +2181,8 @@ static void ns_nand_write_buf(struct mtd - - static void ns_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) - { -- struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); -+ struct nandsim *ns = nand_get_controller_data(chip); - - /* Sanity and correctness checks */ - if (!ns->lines.ce) { -@@ -2198,7 +2203,7 @@ static void ns_nand_read_buf(struct mtd_ - int i; - - for (i = 0; i < len; i++) -- buf[i] = ((struct nand_chip *)mtd->priv)->read_byte(mtd); -+ buf[i] = mtd_to_nand(mtd)->read_byte(mtd); - - return; - } -@@ -2236,16 +2241,15 @@ static int __init ns_init_module(void) - } - - /* Allocate and initialize mtd_info, nand_chip and nandsim structures */ -- nsmtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip) -- + sizeof(struct nandsim), GFP_KERNEL); -- if (!nsmtd) { -+ chip = kzalloc(sizeof(struct nand_chip) + sizeof(struct nandsim), -+ GFP_KERNEL); -+ if (!chip) { - NS_ERR("unable to allocate core structures.\n"); - return -ENOMEM; - } -- chip = (struct nand_chip *)(nsmtd + 1); -- nsmtd->priv = (void *)chip; -+ nsmtd = nand_to_mtd(chip); - nand = (struct nandsim *)(chip + 1); -- chip->priv = (void *)nand; -+ nand_set_controller_data(chip, (void *)nand); - - /* - * Register simulator's callbacks. -@@ -2257,6 +2261,7 @@ static int __init ns_init_module(void) - chip->read_buf = ns_nand_read_buf; - chip->read_word = ns_nand_read_word; - chip->ecc.mode = NAND_ECC_SOFT; -+ chip->ecc.algo = NAND_ECC_HAMMING; - /* The NAND_SKIP_BBTSCAN option is necessary for 'overridesize' */ - /* and 'badblocks' parameters to work */ - chip->options |= NAND_SKIP_BBTSCAN; -@@ -2335,6 +2340,7 @@ static int __init ns_init_module(void) - goto error; - } - chip->ecc.mode = NAND_ECC_SOFT_BCH; -+ chip->ecc.algo = NAND_ECC_BCH; - chip->ecc.size = 512; - chip->ecc.strength = bch; - chip->ecc.bytes = eccbytes; -@@ -2392,7 +2398,7 @@ err_exit: - for (i = 0;i < ARRAY_SIZE(nand->partitions); ++i) - kfree(nand->partitions[i].name); - error: -- kfree(nsmtd); -+ kfree(chip); - free_lists(); - - return retval; -@@ -2405,7 +2411,8 @@ module_init(ns_init_module); - */ - static void __exit ns_cleanup_module(void) - { -- struct nandsim *ns = ((struct nand_chip *)nsmtd->priv)->priv; -+ struct nand_chip *chip = mtd_to_nand(nsmtd); -+ struct nandsim *ns = nand_get_controller_data(chip); - int i; - - nandsim_debugfs_remove(ns); -@@ -2413,7 +2420,7 @@ static void __exit ns_cleanup_module(voi - nand_release(nsmtd); /* Unregister driver */ - for (i = 0;i < ARRAY_SIZE(ns->partitions); ++i) - kfree(ns->partitions[i].name); -- kfree(nsmtd); /* Free other structures */ -+ kfree(mtd_to_nand(nsmtd)); /* Free other structures */ - free_lists(); - } - ---- a/drivers/mtd/ofpart.c -+++ b/drivers/mtd/ofpart.c -@@ -26,9 +26,10 @@ static bool node_has_compatible(struct d - } - - static int parse_ofpart_partitions(struct mtd_info *master, -- struct mtd_partition **pparts, -+ const struct mtd_partition **pparts, - struct mtd_part_parser_data *data) - { -+ struct mtd_partition *parts; - struct device_node *mtd_node; - struct device_node *ofpart_node; - const char *partname; -@@ -37,10 +38,8 @@ static int parse_ofpart_partitions(struc - bool dedicated = true; - - -- if (!data) -- return 0; -- -- mtd_node = data->of_node; -+ /* Pull of_node from the master device node */ -+ mtd_node = mtd_get_of_node(master); - if (!mtd_node) - return 0; - -@@ -72,8 +71,8 @@ static int parse_ofpart_partitions(struc - if (nr_parts == 0) - return 0; - -- *pparts = kzalloc(nr_parts * sizeof(**pparts), GFP_KERNEL); -- if (!*pparts) -+ parts = kzalloc(nr_parts * sizeof(*parts), GFP_KERNEL); -+ if (!parts) - return -ENOMEM; - - i = 0; -@@ -107,19 +106,19 @@ static int parse_ofpart_partitions(struc - goto ofpart_fail; - } - -- (*pparts)[i].offset = of_read_number(reg, a_cells); -- (*pparts)[i].size = of_read_number(reg + a_cells, s_cells); -+ parts[i].offset = of_read_number(reg, a_cells); -+ parts[i].size = of_read_number(reg + a_cells, s_cells); - - partname = of_get_property(pp, "label", &len); - if (!partname) - partname = of_get_property(pp, "name", &len); -- (*pparts)[i].name = partname; -+ parts[i].name = partname; - - if (of_get_property(pp, "read-only", &len)) -- (*pparts)[i].mask_flags |= MTD_WRITEABLE; -+ parts[i].mask_flags |= MTD_WRITEABLE; - - if (of_get_property(pp, "lock", &len)) -- (*pparts)[i].mask_flags |= MTD_POWERUP_LOCK; -+ parts[i].mask_flags |= MTD_POWERUP_LOCK; - - i++; - } -@@ -127,6 +126,7 @@ static int parse_ofpart_partitions(struc - if (!nr_parts) - goto ofpart_none; - -+ *pparts = parts; - return nr_parts; - - ofpart_fail: -@@ -135,21 +135,20 @@ ofpart_fail: - ret = -EINVAL; - ofpart_none: - of_node_put(pp); -- kfree(*pparts); -- *pparts = NULL; -+ kfree(parts); - return ret; - } - - static struct mtd_part_parser ofpart_parser = { -- .owner = THIS_MODULE, - .parse_fn = parse_ofpart_partitions, - .name = "ofpart", - }; - - static int parse_ofoldpart_partitions(struct mtd_info *master, -- struct mtd_partition **pparts, -+ const struct mtd_partition **pparts, - struct mtd_part_parser_data *data) - { -+ struct mtd_partition *parts; - struct device_node *dp; - int i, plen, nr_parts; - const struct { -@@ -157,10 +156,8 @@ static int parse_ofoldpart_partitions(st - } *part; - const char *names; - -- if (!data) -- return 0; -- -- dp = data->of_node; -+ /* Pull of_node from the master device node */ -+ dp = mtd_get_of_node(master); - if (!dp) - return 0; - -@@ -173,37 +170,37 @@ static int parse_ofoldpart_partitions(st - - nr_parts = plen / sizeof(part[0]); - -- *pparts = kzalloc(nr_parts * sizeof(*(*pparts)), GFP_KERNEL); -- if (!*pparts) -+ parts = kzalloc(nr_parts * sizeof(*parts), GFP_KERNEL); -+ if (!parts) - return -ENOMEM; - - names = of_get_property(dp, "partition-names", &plen); - - for (i = 0; i < nr_parts; i++) { -- (*pparts)[i].offset = be32_to_cpu(part->offset); -- (*pparts)[i].size = be32_to_cpu(part->len) & ~1; -+ parts[i].offset = be32_to_cpu(part->offset); -+ parts[i].size = be32_to_cpu(part->len) & ~1; - /* bit 0 set signifies read only partition */ - if (be32_to_cpu(part->len) & 1) -- (*pparts)[i].mask_flags = MTD_WRITEABLE; -+ parts[i].mask_flags = MTD_WRITEABLE; - - if (names && (plen > 0)) { - int len = strlen(names) + 1; - -- (*pparts)[i].name = names; -+ parts[i].name = names; - plen -= len; - names += len; - } else { -- (*pparts)[i].name = "unnamed"; -+ parts[i].name = "unnamed"; - } - - part++; - } - -+ *pparts = parts; - return nr_parts; - } - - static struct mtd_part_parser ofoldpart_parser = { -- .owner = THIS_MODULE, - .parse_fn = parse_ofoldpart_partitions, - .name = "ofoldpart", - }; ---- a/drivers/mtd/spi-nor/Kconfig -+++ b/drivers/mtd/spi-nor/Kconfig -@@ -7,6 +7,14 @@ menuconfig MTD_SPI_NOR - - if MTD_SPI_NOR - -+config MTD_MT81xx_NOR -+ tristate "Mediatek MT81xx SPI NOR flash controller" -+ depends on HAS_IOMEM -+ help -+ This enables access to SPI NOR flash, using MT81xx SPI NOR flash -+ controller. This controller does not support generic SPI BUS, it only -+ supports SPI NOR Flash. -+ - config MTD_SPI_NOR_USE_4K_SECTORS - bool "Use small 4096 B erase sectors" - default y -@@ -23,7 +31,7 @@ config MTD_SPI_NOR_USE_4K_SECTORS - - config SPI_FSL_QUADSPI - tristate "Freescale Quad SPI controller" -- depends on ARCH_MXC || COMPILE_TEST -+ depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST - depends on HAS_IOMEM - help - This enables support for the Quad SPI controller in master mode. ---- a/drivers/mtd/spi-nor/Makefile -+++ b/drivers/mtd/spi-nor/Makefile -@@ -1,3 +1,4 @@ - obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o - obj-$(CONFIG_SPI_FSL_QUADSPI) += fsl-quadspi.o -+obj-$(CONFIG_MTD_MT81xx_NOR) += mtk-quadspi.o - obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o ---- /dev/null -+++ b/drivers/mtd/spi-nor/mtk-quadspi.c -@@ -0,0 +1,485 @@ -+/* -+ * Copyright (c) 2015 MediaTek Inc. -+ * Author: Bayi Cheng <bayi.cheng@mediatek.com> -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include <linux/clk.h> -+#include <linux/delay.h> -+#include <linux/device.h> -+#include <linux/init.h> -+#include <linux/io.h> -+#include <linux/iopoll.h> -+#include <linux/ioport.h> -+#include <linux/math64.h> -+#include <linux/module.h> -+#include <linux/mtd/mtd.h> -+#include <linux/mutex.h> -+#include <linux/of.h> -+#include <linux/of_device.h> -+#include <linux/pinctrl/consumer.h> -+#include <linux/platform_device.h> -+#include <linux/slab.h> -+#include <linux/mtd/mtd.h> -+#include <linux/mtd/partitions.h> -+#include <linux/mtd/spi-nor.h> -+ -+#define MTK_NOR_CMD_REG 0x00 -+#define MTK_NOR_CNT_REG 0x04 -+#define MTK_NOR_RDSR_REG 0x08 -+#define MTK_NOR_RDATA_REG 0x0c -+#define MTK_NOR_RADR0_REG 0x10 -+#define MTK_NOR_RADR1_REG 0x14 -+#define MTK_NOR_RADR2_REG 0x18 -+#define MTK_NOR_WDATA_REG 0x1c -+#define MTK_NOR_PRGDATA0_REG 0x20 -+#define MTK_NOR_PRGDATA1_REG 0x24 -+#define MTK_NOR_PRGDATA2_REG 0x28 -+#define MTK_NOR_PRGDATA3_REG 0x2c -+#define MTK_NOR_PRGDATA4_REG 0x30 -+#define MTK_NOR_PRGDATA5_REG 0x34 -+#define MTK_NOR_SHREG0_REG 0x38 -+#define MTK_NOR_SHREG1_REG 0x3c -+#define MTK_NOR_SHREG2_REG 0x40 -+#define MTK_NOR_SHREG3_REG 0x44 -+#define MTK_NOR_SHREG4_REG 0x48 -+#define MTK_NOR_SHREG5_REG 0x4c -+#define MTK_NOR_SHREG6_REG 0x50 -+#define MTK_NOR_SHREG7_REG 0x54 -+#define MTK_NOR_SHREG8_REG 0x58 -+#define MTK_NOR_SHREG9_REG 0x5c -+#define MTK_NOR_CFG1_REG 0x60 -+#define MTK_NOR_CFG2_REG 0x64 -+#define MTK_NOR_CFG3_REG 0x68 -+#define MTK_NOR_STATUS0_REG 0x70 -+#define MTK_NOR_STATUS1_REG 0x74 -+#define MTK_NOR_STATUS2_REG 0x78 -+#define MTK_NOR_STATUS3_REG 0x7c -+#define MTK_NOR_FLHCFG_REG 0x84 -+#define MTK_NOR_TIME_REG 0x94 -+#define MTK_NOR_PP_DATA_REG 0x98 -+#define MTK_NOR_PREBUF_STUS_REG 0x9c -+#define MTK_NOR_DELSEL0_REG 0xa0 -+#define MTK_NOR_DELSEL1_REG 0xa4 -+#define MTK_NOR_INTRSTUS_REG 0xa8 -+#define MTK_NOR_INTREN_REG 0xac -+#define MTK_NOR_CHKSUM_CTL_REG 0xb8 -+#define MTK_NOR_CHKSUM_REG 0xbc -+#define MTK_NOR_CMD2_REG 0xc0 -+#define MTK_NOR_WRPROT_REG 0xc4 -+#define MTK_NOR_RADR3_REG 0xc8 -+#define MTK_NOR_DUAL_REG 0xcc -+#define MTK_NOR_DELSEL2_REG 0xd0 -+#define MTK_NOR_DELSEL3_REG 0xd4 -+#define MTK_NOR_DELSEL4_REG 0xd8 -+ -+/* commands for mtk nor controller */ -+#define MTK_NOR_READ_CMD 0x0 -+#define MTK_NOR_RDSR_CMD 0x2 -+#define MTK_NOR_PRG_CMD 0x4 -+#define MTK_NOR_WR_CMD 0x10 -+#define MTK_NOR_PIO_WR_CMD 0x90 -+#define MTK_NOR_WRSR_CMD 0x20 -+#define MTK_NOR_PIO_READ_CMD 0x81 -+#define MTK_NOR_WR_BUF_ENABLE 0x1 -+#define MTK_NOR_WR_BUF_DISABLE 0x0 -+#define MTK_NOR_ENABLE_SF_CMD 0x30 -+#define MTK_NOR_DUAD_ADDR_EN 0x8 -+#define MTK_NOR_QUAD_READ_EN 0x4 -+#define MTK_NOR_DUAL_ADDR_EN 0x2 -+#define MTK_NOR_DUAL_READ_EN 0x1 -+#define MTK_NOR_DUAL_DISABLE 0x0 -+#define MTK_NOR_FAST_READ 0x1 -+ -+#define SFLASH_WRBUF_SIZE 128 -+ -+/* Can shift up to 48 bits (6 bytes) of TX/RX */ -+#define MTK_NOR_MAX_RX_TX_SHIFT 6 -+/* can shift up to 56 bits (7 bytes) transfer by MTK_NOR_PRG_CMD */ -+#define MTK_NOR_MAX_SHIFT 7 -+ -+/* Helpers for accessing the program data / shift data registers */ -+#define MTK_NOR_PRG_REG(n) (MTK_NOR_PRGDATA0_REG + 4 * (n)) -+#define MTK_NOR_SHREG(n) (MTK_NOR_SHREG0_REG + 4 * (n)) -+ -+struct mt8173_nor { -+ struct spi_nor nor; -+ struct device *dev; -+ void __iomem *base; /* nor flash base address */ -+ struct clk *spi_clk; -+ struct clk *nor_clk; -+}; -+ -+static void mt8173_nor_set_read_mode(struct mt8173_nor *mt8173_nor) -+{ -+ struct spi_nor *nor = &mt8173_nor->nor; -+ -+ switch (nor->flash_read) { -+ case SPI_NOR_FAST: -+ writeb(nor->read_opcode, mt8173_nor->base + -+ MTK_NOR_PRGDATA3_REG); -+ writeb(MTK_NOR_FAST_READ, mt8173_nor->base + -+ MTK_NOR_CFG1_REG); -+ break; -+ case SPI_NOR_DUAL: -+ writeb(nor->read_opcode, mt8173_nor->base + -+ MTK_NOR_PRGDATA3_REG); -+ writeb(MTK_NOR_DUAL_READ_EN, mt8173_nor->base + -+ MTK_NOR_DUAL_REG); -+ break; -+ case SPI_NOR_QUAD: -+ writeb(nor->read_opcode, mt8173_nor->base + -+ MTK_NOR_PRGDATA4_REG); -+ writeb(MTK_NOR_QUAD_READ_EN, mt8173_nor->base + -+ MTK_NOR_DUAL_REG); -+ break; -+ default: -+ writeb(MTK_NOR_DUAL_DISABLE, mt8173_nor->base + -+ MTK_NOR_DUAL_REG); -+ break; -+ } -+} -+ -+static int mt8173_nor_execute_cmd(struct mt8173_nor *mt8173_nor, u8 cmdval) -+{ -+ int reg; -+ u8 val = cmdval & 0x1f; -+ -+ writeb(cmdval, mt8173_nor->base + MTK_NOR_CMD_REG); -+ return readl_poll_timeout(mt8173_nor->base + MTK_NOR_CMD_REG, reg, -+ !(reg & val), 100, 10000); -+} -+ -+static int mt8173_nor_do_tx_rx(struct mt8173_nor *mt8173_nor, u8 op, -+ u8 *tx, int txlen, u8 *rx, int rxlen) -+{ -+ int len = 1 + txlen + rxlen; -+ int i, ret, idx; -+ -+ if (len > MTK_NOR_MAX_SHIFT) -+ return -EINVAL; -+ -+ writeb(len * 8, mt8173_nor->base + MTK_NOR_CNT_REG); -+ -+ /* start at PRGDATA5, go down to PRGDATA0 */ -+ idx = MTK_NOR_MAX_RX_TX_SHIFT - 1; -+ -+ /* opcode */ -+ writeb(op, mt8173_nor->base + MTK_NOR_PRG_REG(idx)); -+ idx--; -+ -+ /* program TX data */ -+ for (i = 0; i < txlen; i++, idx--) -+ writeb(tx[i], mt8173_nor->base + MTK_NOR_PRG_REG(idx)); -+ -+ /* clear out rest of TX registers */ -+ while (idx >= 0) { -+ writeb(0, mt8173_nor->base + MTK_NOR_PRG_REG(idx)); -+ idx--; -+ } -+ -+ ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PRG_CMD); -+ if (ret) -+ return ret; -+ -+ /* restart at first RX byte */ -+ idx = rxlen - 1; -+ -+ /* read out RX data */ -+ for (i = 0; i < rxlen; i++, idx--) -+ rx[i] = readb(mt8173_nor->base + MTK_NOR_SHREG(idx)); -+ -+ return 0; -+} -+ -+/* Do a WRSR (Write Status Register) command */ -+static int mt8173_nor_wr_sr(struct mt8173_nor *mt8173_nor, u8 sr) -+{ -+ writeb(sr, mt8173_nor->base + MTK_NOR_PRGDATA5_REG); -+ writeb(8, mt8173_nor->base + MTK_NOR_CNT_REG); -+ return mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_WRSR_CMD); -+} -+ -+static int mt8173_nor_write_buffer_enable(struct mt8173_nor *mt8173_nor) -+{ -+ u8 reg; -+ -+ /* the bit0 of MTK_NOR_CFG2_REG is pre-fetch buffer -+ * 0: pre-fetch buffer use for read -+ * 1: pre-fetch buffer use for page program -+ */ -+ writel(MTK_NOR_WR_BUF_ENABLE, mt8173_nor->base + MTK_NOR_CFG2_REG); -+ return readb_poll_timeout(mt8173_nor->base + MTK_NOR_CFG2_REG, reg, -+ 0x01 == (reg & 0x01), 100, 10000); -+} -+ -+static int mt8173_nor_write_buffer_disable(struct mt8173_nor *mt8173_nor) -+{ -+ u8 reg; -+ -+ writel(MTK_NOR_WR_BUF_DISABLE, mt8173_nor->base + MTK_NOR_CFG2_REG); -+ return readb_poll_timeout(mt8173_nor->base + MTK_NOR_CFG2_REG, reg, -+ MTK_NOR_WR_BUF_DISABLE == (reg & 0x1), 100, -+ 10000); -+} -+ -+static void mt8173_nor_set_addr(struct mt8173_nor *mt8173_nor, u32 addr) -+{ -+ int i; -+ -+ for (i = 0; i < 3; i++) { -+ writeb(addr & 0xff, mt8173_nor->base + MTK_NOR_RADR0_REG + i * 4); -+ addr >>= 8; -+ } -+ /* Last register is non-contiguous */ -+ writeb(addr & 0xff, mt8173_nor->base + MTK_NOR_RADR3_REG); -+} -+ -+static int mt8173_nor_read(struct spi_nor *nor, loff_t from, size_t length, -+ size_t *retlen, u_char *buffer) -+{ -+ int i, ret; -+ int addr = (int)from; -+ u8 *buf = (u8 *)buffer; -+ struct mt8173_nor *mt8173_nor = nor->priv; -+ -+ /* set mode for fast read mode ,dual mode or quad mode */ -+ mt8173_nor_set_read_mode(mt8173_nor); -+ mt8173_nor_set_addr(mt8173_nor, addr); -+ -+ for (i = 0; i < length; i++, (*retlen)++) { -+ ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PIO_READ_CMD); -+ if (ret < 0) -+ return ret; -+ buf[i] = readb(mt8173_nor->base + MTK_NOR_RDATA_REG); -+ } -+ return 0; -+} -+ -+static int mt8173_nor_write_single_byte(struct mt8173_nor *mt8173_nor, -+ int addr, int length, u8 *data) -+{ -+ int i, ret; -+ -+ mt8173_nor_set_addr(mt8173_nor, addr); -+ -+ for (i = 0; i < length; i++) { -+ writeb(*data++, mt8173_nor->base + MTK_NOR_WDATA_REG); -+ ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PIO_WR_CMD); -+ if (ret < 0) -+ return ret; -+ } -+ return 0; -+} -+ -+static int mt8173_nor_write_buffer(struct mt8173_nor *mt8173_nor, int addr, -+ const u8 *buf) -+{ -+ int i, bufidx, data; -+ -+ mt8173_nor_set_addr(mt8173_nor, addr); -+ -+ bufidx = 0; -+ for (i = 0; i < SFLASH_WRBUF_SIZE; i += 4) { -+ data = buf[bufidx + 3]<<24 | buf[bufidx + 2]<<16 | -+ buf[bufidx + 1]<<8 | buf[bufidx]; -+ bufidx += 4; -+ writel(data, mt8173_nor->base + MTK_NOR_PP_DATA_REG); -+ } -+ return mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_WR_CMD); -+} -+ -+static void mt8173_nor_write(struct spi_nor *nor, loff_t to, size_t len, -+ size_t *retlen, const u_char *buf) -+{ -+ int ret; -+ struct mt8173_nor *mt8173_nor = nor->priv; -+ -+ ret = mt8173_nor_write_buffer_enable(mt8173_nor); -+ if (ret < 0) -+ dev_warn(mt8173_nor->dev, "write buffer enable failed!\n"); -+ -+ while (len >= SFLASH_WRBUF_SIZE) { -+ ret = mt8173_nor_write_buffer(mt8173_nor, to, buf); -+ if (ret < 0) -+ dev_err(mt8173_nor->dev, "write buffer failed!\n"); -+ len -= SFLASH_WRBUF_SIZE; -+ to += SFLASH_WRBUF_SIZE; -+ buf += SFLASH_WRBUF_SIZE; -+ (*retlen) += SFLASH_WRBUF_SIZE; -+ } -+ ret = mt8173_nor_write_buffer_disable(mt8173_nor); -+ if (ret < 0) -+ dev_warn(mt8173_nor->dev, "write buffer disable failed!\n"); -+ -+ if (len) { -+ ret = mt8173_nor_write_single_byte(mt8173_nor, to, (int)len, -+ (u8 *)buf); -+ if (ret < 0) -+ dev_err(mt8173_nor->dev, "write single byte failed!\n"); -+ (*retlen) += len; -+ } -+} -+ -+static int mt8173_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) -+{ -+ int ret; -+ struct mt8173_nor *mt8173_nor = nor->priv; -+ -+ switch (opcode) { -+ case SPINOR_OP_RDSR: -+ ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_RDSR_CMD); -+ if (ret < 0) -+ return ret; -+ if (len == 1) -+ *buf = readb(mt8173_nor->base + MTK_NOR_RDSR_REG); -+ else -+ dev_err(mt8173_nor->dev, "len should be 1 for read status!\n"); -+ break; -+ default: -+ ret = mt8173_nor_do_tx_rx(mt8173_nor, opcode, NULL, 0, buf, len); -+ break; -+ } -+ return ret; -+} -+ -+static int mt8173_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, -+ int len) -+{ -+ int ret; -+ struct mt8173_nor *mt8173_nor = nor->priv; -+ -+ switch (opcode) { -+ case SPINOR_OP_WRSR: -+ /* We only handle 1 byte */ -+ ret = mt8173_nor_wr_sr(mt8173_nor, *buf); -+ break; -+ default: -+ ret = mt8173_nor_do_tx_rx(mt8173_nor, opcode, buf, len, NULL, 0); -+ if (ret) -+ dev_warn(mt8173_nor->dev, "write reg failure!\n"); -+ break; -+ } -+ return ret; -+} -+ -+static int mtk_nor_init(struct mt8173_nor *mt8173_nor, -+ struct device_node *flash_node) -+{ -+ int ret; -+ struct spi_nor *nor; -+ -+ /* initialize controller to accept commands */ -+ writel(MTK_NOR_ENABLE_SF_CMD, mt8173_nor->base + MTK_NOR_WRPROT_REG); -+ -+ nor = &mt8173_nor->nor; -+ nor->dev = mt8173_nor->dev; -+ nor->priv = mt8173_nor; -+ spi_nor_set_flash_node(nor, flash_node); -+ -+ /* fill the hooks to spi nor */ -+ nor->read = mt8173_nor_read; -+ nor->read_reg = mt8173_nor_read_reg; -+ nor->write = mt8173_nor_write; -+ nor->write_reg = mt8173_nor_write_reg; -+ nor->mtd.name = "mtk_nor"; -+ /* initialized with NULL */ -+ ret = spi_nor_scan(nor, NULL, SPI_NOR_DUAL); -+ if (ret) -+ return ret; -+ -+ return mtd_device_register(&nor->mtd, NULL, 0); -+} -+ -+static int mtk_nor_drv_probe(struct platform_device *pdev) -+{ -+ struct device_node *flash_np; -+ struct resource *res; -+ int ret; -+ struct mt8173_nor *mt8173_nor; -+ -+ if (!pdev->dev.of_node) { -+ dev_err(&pdev->dev, "No DT found\n"); -+ return -EINVAL; -+ } -+ -+ mt8173_nor = devm_kzalloc(&pdev->dev, sizeof(*mt8173_nor), GFP_KERNEL); -+ if (!mt8173_nor) -+ return -ENOMEM; -+ platform_set_drvdata(pdev, mt8173_nor); -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ mt8173_nor->base = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(mt8173_nor->base)) -+ return PTR_ERR(mt8173_nor->base); -+ -+ mt8173_nor->spi_clk = devm_clk_get(&pdev->dev, "spi"); -+ if (IS_ERR(mt8173_nor->spi_clk)) -+ return PTR_ERR(mt8173_nor->spi_clk); -+ -+ mt8173_nor->nor_clk = devm_clk_get(&pdev->dev, "sf"); -+ if (IS_ERR(mt8173_nor->nor_clk)) -+ return PTR_ERR(mt8173_nor->nor_clk); -+ -+ mt8173_nor->dev = &pdev->dev; -+ ret = clk_prepare_enable(mt8173_nor->spi_clk); -+ if (ret) -+ return ret; -+ -+ ret = clk_prepare_enable(mt8173_nor->nor_clk); -+ if (ret) { -+ clk_disable_unprepare(mt8173_nor->spi_clk); -+ return ret; -+ } -+ /* only support one attached flash */ -+ flash_np = of_get_next_available_child(pdev->dev.of_node, NULL); -+ if (!flash_np) { -+ dev_err(&pdev->dev, "no SPI flash device to configure\n"); -+ ret = -ENODEV; -+ goto nor_free; -+ } -+ ret = mtk_nor_init(mt8173_nor, flash_np); -+ -+nor_free: -+ if (ret) { -+ clk_disable_unprepare(mt8173_nor->spi_clk); -+ clk_disable_unprepare(mt8173_nor->nor_clk); -+ } -+ return ret; -+} -+ -+static int mtk_nor_drv_remove(struct platform_device *pdev) -+{ -+ struct mt8173_nor *mt8173_nor = platform_get_drvdata(pdev); -+ -+ clk_disable_unprepare(mt8173_nor->spi_clk); -+ clk_disable_unprepare(mt8173_nor->nor_clk); -+ return 0; -+} -+ -+static const struct of_device_id mtk_nor_of_ids[] = { -+ { .compatible = "mediatek,mt8173-nor"}, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, mtk_nor_of_ids); -+ -+static struct platform_driver mtk_nor_driver = { -+ .probe = mtk_nor_drv_probe, -+ .remove = mtk_nor_drv_remove, -+ .driver = { -+ .name = "mtk-nor", -+ .of_match_table = mtk_nor_of_ids, -+ }, -+}; -+ -+module_platform_driver(mtk_nor_driver); -+MODULE_LICENSE("GPL v2"); -+MODULE_DESCRIPTION("MediaTek SPI NOR Flash Driver"); ---- a/drivers/mtd/spi-nor/spi-nor.c -+++ b/drivers/mtd/spi-nor/spi-nor.c -@@ -38,6 +38,7 @@ - #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ) - - #define SPI_NOR_MAX_ID_LEN 6 -+#define SPI_NOR_MAX_ADDR_WIDTH 4 - - struct flash_info { - char *name; -@@ -60,15 +61,20 @@ struct flash_info { - u16 addr_width; - - u16 flags; --#define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */ --#define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */ --#define SST_WRITE 0x04 /* use SST byte programming */ --#define SPI_NOR_NO_FR 0x08 /* Can't do fastread */ --#define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */ --#define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */ --#define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */ --#define USE_FSR 0x80 /* use flag status register */ --#define SPI_NOR_HAS_LOCK 0x100 /* Flash supports lock/unlock via SR */ -+#define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */ -+#define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */ -+#define SST_WRITE BIT(2) /* use SST byte programming */ -+#define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */ -+#define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */ -+#define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */ -+#define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */ -+#define USE_FSR BIT(7) /* use flag status register */ -+#define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */ -+#define SPI_NOR_HAS_TB BIT(9) /* -+ * Flash SR has Top/Bottom (TB) protect -+ * bit. Must be used with -+ * SPI_NOR_HAS_LOCK. -+ */ - }; - - #define JEDEC_MFR(info) ((info)->id[0]) -@@ -314,6 +320,29 @@ static void spi_nor_unlock_and_unprep(st - } - - /* -+ * Initiate the erasure of a single sector -+ */ -+static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) -+{ -+ u8 buf[SPI_NOR_MAX_ADDR_WIDTH]; -+ int i; -+ -+ if (nor->erase) -+ return nor->erase(nor, addr); -+ -+ /* -+ * Default implementation, if driver doesn't have a specialized HW -+ * control -+ */ -+ for (i = nor->addr_width - 1; i >= 0; i--) { -+ buf[i] = addr & 0xff; -+ addr >>= 8; -+ } -+ -+ return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width); -+} -+ -+/* - * Erase an address range on the nor chip. The address range may extend - * one or more erase sectors. Return an error is there is a problem erasing. - */ -@@ -372,10 +401,9 @@ static int spi_nor_erase(struct mtd_info - while (len) { - write_enable(nor); - -- if (nor->erase(nor, addr)) { -- ret = -EIO; -+ ret = spi_nor_erase_sector(nor, addr); -+ if (ret) - goto erase_err; -- } - - addr += mtd->erasesize; - len -= mtd->erasesize; -@@ -388,17 +416,13 @@ static int spi_nor_erase(struct mtd_info - - write_disable(nor); - -+erase_err: - spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE); - -- instr->state = MTD_ERASE_DONE; -+ instr->state = ret ? MTD_ERASE_FAILED : MTD_ERASE_DONE; - mtd_erase_callback(instr); - - return ret; -- --erase_err: -- spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE); -- instr->state = MTD_ERASE_FAILED; -- return ret; - } - - static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs, -@@ -416,32 +440,58 @@ static void stm_get_locked_range(struct - } else { - pow = ((sr & mask) ^ mask) >> shift; - *len = mtd->size >> pow; -- *ofs = mtd->size - *len; -+ if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB) -+ *ofs = 0; -+ else -+ *ofs = mtd->size - *len; - } - } - - /* -- * Return 1 if the entire region is locked, 0 otherwise -+ * Return 1 if the entire region is locked (if @locked is true) or unlocked (if -+ * @locked is false); 0 otherwise - */ --static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, -- u8 sr) -+static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, -+ u8 sr, bool locked) - { - loff_t lock_offs; - uint64_t lock_len; - -+ if (!len) -+ return 1; -+ - stm_get_locked_range(nor, sr, &lock_offs, &lock_len); - -- return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs); -+ if (locked) -+ /* Requested range is a sub-range of locked range */ -+ return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs); -+ else -+ /* Requested range does not overlap with locked range */ -+ return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs); -+} -+ -+static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, -+ u8 sr) -+{ -+ return stm_check_lock_status_sr(nor, ofs, len, sr, true); -+} -+ -+static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, -+ u8 sr) -+{ -+ return stm_check_lock_status_sr(nor, ofs, len, sr, false); - } - - /* - * Lock a region of the flash. Compatible with ST Micro and similar flash. -- * Supports only the block protection bits BP{0,1,2} in the status register -+ * Supports the block protection bits BP{0,1,2} in the status register - * (SR). Does not support these features found in newer SR bitfields: -- * - TB: top/bottom protect - only handle TB=0 (top protect) - * - SEC: sector/block protect - only handle SEC=0 (block protect) - * - CMP: complement protect - only support CMP=0 (range is not complemented) - * -+ * Support for the following is provided conditionally for some flash: -+ * - TB: top/bottom protect -+ * - * Sample table portion for 8MB flash (Winbond w25q64fw): - * - * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion -@@ -454,26 +504,55 @@ static int stm_is_locked_sr(struct spi_n - * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4 - * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2 - * X | X | 1 | 1 | 1 | 8 MB | ALL -+ * ------|-------|-------|-------|-------|---------------|------------------- -+ * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64 -+ * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32 -+ * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16 -+ * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8 -+ * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4 -+ * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2 - * - * Returns negative on errors, 0 on success. - */ - static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) - { - struct mtd_info *mtd = &nor->mtd; -- u8 status_old, status_new; -+ int status_old, status_new; - u8 mask = SR_BP2 | SR_BP1 | SR_BP0; - u8 shift = ffs(mask) - 1, pow, val; -+ loff_t lock_len; -+ bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; -+ bool use_top; -+ int ret; - - status_old = read_sr(nor); -+ if (status_old < 0) -+ return status_old; - -- /* SPI NOR always locks to the end */ -- if (ofs + len != mtd->size) { -- /* Does combined region extend to end? */ -- if (!stm_is_locked_sr(nor, ofs + len, mtd->size - ofs - len, -- status_old)) -- return -EINVAL; -- len = mtd->size - ofs; -- } -+ /* If nothing in our range is unlocked, we don't need to do anything */ -+ if (stm_is_locked_sr(nor, ofs, len, status_old)) -+ return 0; -+ -+ /* If anything below us is unlocked, we can't use 'bottom' protection */ -+ if (!stm_is_locked_sr(nor, 0, ofs, status_old)) -+ can_be_bottom = false; -+ -+ /* If anything above us is unlocked, we can't use 'top' protection */ -+ if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len), -+ status_old)) -+ can_be_top = false; -+ -+ if (!can_be_bottom && !can_be_top) -+ return -EINVAL; -+ -+ /* Prefer top, if both are valid */ -+ use_top = can_be_top; -+ -+ /* lock_len: length of region that should end up locked */ -+ if (use_top) -+ lock_len = mtd->size - ofs; -+ else -+ lock_len = ofs + len; - - /* - * Need smallest pow such that: -@@ -484,7 +563,7 @@ static int stm_lock(struct spi_nor *nor, - * - * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len)) - */ -- pow = ilog2(mtd->size) - ilog2(len); -+ pow = ilog2(mtd->size) - ilog2(lock_len); - val = mask - (pow << shift); - if (val & ~mask) - return -EINVAL; -@@ -492,14 +571,27 @@ static int stm_lock(struct spi_nor *nor, - if (!(val & mask)) - return -EINVAL; - -- status_new = (status_old & ~mask) | val; -+ status_new = (status_old & ~mask & ~SR_TB) | val; -+ -+ /* Disallow further writes if WP pin is asserted */ -+ status_new |= SR_SRWD; -+ -+ if (!use_top) -+ status_new |= SR_TB; -+ -+ /* Don't bother if they're the same */ -+ if (status_new == status_old) -+ return 0; - - /* Only modify protection if it will not unlock other areas */ -- if ((status_new & mask) <= (status_old & mask)) -+ if ((status_new & mask) < (status_old & mask)) - return -EINVAL; - - write_enable(nor); -- return write_sr(nor, status_new); -+ ret = write_sr(nor, status_new); -+ if (ret) -+ return ret; -+ return spi_nor_wait_till_ready(nor); - } - - /* -@@ -510,17 +602,43 @@ static int stm_lock(struct spi_nor *nor, - static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) - { - struct mtd_info *mtd = &nor->mtd; -- uint8_t status_old, status_new; -+ int status_old, status_new; - u8 mask = SR_BP2 | SR_BP1 | SR_BP0; - u8 shift = ffs(mask) - 1, pow, val; -+ loff_t lock_len; -+ bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; -+ bool use_top; -+ int ret; - - status_old = read_sr(nor); -+ if (status_old < 0) -+ return status_old; -+ -+ /* If nothing in our range is locked, we don't need to do anything */ -+ if (stm_is_unlocked_sr(nor, ofs, len, status_old)) -+ return 0; -+ -+ /* If anything below us is locked, we can't use 'top' protection */ -+ if (!stm_is_unlocked_sr(nor, 0, ofs, status_old)) -+ can_be_top = false; -+ -+ /* If anything above us is locked, we can't use 'bottom' protection */ -+ if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len), -+ status_old)) -+ can_be_bottom = false; - -- /* Cannot unlock; would unlock larger region than requested */ -- if (stm_is_locked_sr(nor, ofs - mtd->erasesize, mtd->erasesize, -- status_old)) -+ if (!can_be_bottom && !can_be_top) - return -EINVAL; - -+ /* Prefer top, if both are valid */ -+ use_top = can_be_top; -+ -+ /* lock_len: length of region that should remain locked */ -+ if (use_top) -+ lock_len = mtd->size - (ofs + len); -+ else -+ lock_len = ofs; -+ - /* - * Need largest pow such that: - * -@@ -530,8 +648,8 @@ static int stm_unlock(struct spi_nor *no - * - * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len)) - */ -- pow = ilog2(mtd->size) - order_base_2(mtd->size - (ofs + len)); -- if (ofs + len == mtd->size) { -+ pow = ilog2(mtd->size) - order_base_2(lock_len); -+ if (lock_len == 0) { - val = 0; /* fully unlocked */ - } else { - val = mask - (pow << shift); -@@ -540,14 +658,28 @@ static int stm_unlock(struct spi_nor *no - return -EINVAL; - } - -- status_new = (status_old & ~mask) | val; -+ status_new = (status_old & ~mask & ~SR_TB) | val; -+ -+ /* Don't protect status register if we're fully unlocked */ -+ if (lock_len == mtd->size) -+ status_new &= ~SR_SRWD; -+ -+ if (!use_top) -+ status_new |= SR_TB; -+ -+ /* Don't bother if they're the same */ -+ if (status_new == status_old) -+ return 0; - - /* Only modify protection if it will not lock other areas */ -- if ((status_new & mask) >= (status_old & mask)) -+ if ((status_new & mask) > (status_old & mask)) - return -EINVAL; - - write_enable(nor); -- return write_sr(nor, status_new); -+ ret = write_sr(nor, status_new); -+ if (ret) -+ return ret; -+ return spi_nor_wait_till_ready(nor); - } - - /* -@@ -737,8 +869,8 @@ static const struct flash_info spi_nor_i - { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, - { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, - { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, -- { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, -- { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, -+ { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, -+ { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, - { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, - { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, - { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, -@@ -772,6 +904,7 @@ static const struct flash_info spi_nor_i - { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, -+ { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) }, - { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) }, - { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ) }, -@@ -835,11 +968,23 @@ static const struct flash_info spi_nor_i - { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) }, - { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) }, - { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) }, -- { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, -+ { -+ "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, -+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | -+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) -+ }, - { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) }, - { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, -- { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, -- { "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, -+ { -+ "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, -+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | -+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) -+ }, -+ { -+ "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256, -+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | -+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) -+ }, - { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) }, - { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) }, - { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) }, -@@ -862,7 +1007,7 @@ static const struct flash_info *spi_nor_ - - tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN); - if (tmp < 0) { -- dev_dbg(nor->dev, " error %d reading JEDEC ID\n", tmp); -+ dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp); - return ERR_PTR(tmp); - } - -@@ -873,7 +1018,7 @@ static const struct flash_info *spi_nor_ - return &spi_nor_ids[tmp]; - } - } -- dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %2x, %2x\n", -+ dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n", - id[0], id[1], id[2]); - return ERR_PTR(-ENODEV); - } -@@ -1019,6 +1164,8 @@ static int macronix_quad_enable(struct s - int ret, val; - - val = read_sr(nor); -+ if (val < 0) -+ return val; - write_enable(nor); - - write_sr(nor, val | SR_QUAD_EN_MX); -@@ -1107,7 +1254,7 @@ static int set_quad_mode(struct spi_nor - static int spi_nor_check(struct spi_nor *nor) - { - if (!nor->dev || !nor->read || !nor->write || -- !nor->read_reg || !nor->write_reg || !nor->erase) { -+ !nor->read_reg || !nor->write_reg) { - pr_err("spi-nor: please fill all the necessary fields!\n"); - return -EINVAL; - } -@@ -1120,7 +1267,7 @@ int spi_nor_scan(struct spi_nor *nor, co - const struct flash_info *info = NULL; - struct device *dev = nor->dev; - struct mtd_info *mtd = &nor->mtd; -- struct device_node *np = nor->flash_node; -+ struct device_node *np = spi_nor_get_flash_node(nor); - int ret; - int i; - -@@ -1174,6 +1321,7 @@ int spi_nor_scan(struct spi_nor *nor, co - info->flags & SPI_NOR_HAS_LOCK) { - write_enable(nor); - write_sr(nor, 0); -+ spi_nor_wait_till_ready(nor); - } - - if (!mtd->name) -@@ -1208,6 +1356,8 @@ int spi_nor_scan(struct spi_nor *nor, co - - if (info->flags & USE_FSR) - nor->flags |= SNOR_F_USE_FSR; -+ if (info->flags & SPI_NOR_HAS_TB) -+ nor->flags |= SNOR_F_HAS_SR_TB; - - #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS - /* prefer "small sector" erase if possible */ -@@ -1310,6 +1460,12 @@ int spi_nor_scan(struct spi_nor *nor, co - nor->addr_width = 3; - } - -+ if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) { -+ dev_err(dev, "address width is too large: %u\n", -+ nor->addr_width); -+ return -EINVAL; -+ } -+ - nor->read_dummy = spi_nor_read_dummy_cycles(nor); - - dev_info(dev, "%s (%lld Kbytes)\n", info->name, ---- a/drivers/mtd/tests/mtd_nandecctest.c -+++ b/drivers/mtd/tests/mtd_nandecctest.c -@@ -187,7 +187,7 @@ static int double_bit_error_detect(void - __nand_calculate_ecc(error_data, size, calc_ecc); - ret = __nand_correct_data(error_data, error_ecc, calc_ecc, size); - -- return (ret == -1) ? 0 : -EINVAL; -+ return (ret == -EBADMSG) ? 0 : -EINVAL; - } - - static const struct nand_ecc_test nand_ecc_test[] = { ---- a/drivers/mtd/tests/oobtest.c -+++ b/drivers/mtd/tests/oobtest.c -@@ -215,19 +215,19 @@ static int verify_eraseblock(int ebnum) - pr_info("ignoring error as within bitflip_limit\n"); - } - -- if (use_offset != 0 || use_len < mtd->ecclayout->oobavail) { -+ if (use_offset != 0 || use_len < mtd->oobavail) { - int k; - - ops.mode = MTD_OPS_AUTO_OOB; - ops.len = 0; - ops.retlen = 0; -- ops.ooblen = mtd->ecclayout->oobavail; -+ ops.ooblen = mtd->oobavail; - ops.oobretlen = 0; - ops.ooboffs = 0; - ops.datbuf = NULL; - ops.oobbuf = readbuf; - err = mtd_read_oob(mtd, addr, &ops); -- if (err || ops.oobretlen != mtd->ecclayout->oobavail) { -+ if (err || ops.oobretlen != mtd->oobavail) { - pr_err("error: readoob failed at %#llx\n", - (long long)addr); - errcnt += 1; -@@ -244,7 +244,7 @@ static int verify_eraseblock(int ebnum) - /* verify post-(use_offset + use_len) area for 0xff */ - k = use_offset + use_len; - bitflips += memffshow(addr, k, readbuf + k, -- mtd->ecclayout->oobavail - k); -+ mtd->oobavail - k); - - if (bitflips > bitflip_limit) { - pr_err("error: verify failed at %#llx\n", -@@ -269,8 +269,8 @@ static int verify_eraseblock_in_one_go(i - struct mtd_oob_ops ops; - int err = 0; - loff_t addr = (loff_t)ebnum * mtd->erasesize; -- size_t len = mtd->ecclayout->oobavail * pgcnt; -- size_t oobavail = mtd->ecclayout->oobavail; -+ size_t len = mtd->oobavail * pgcnt; -+ size_t oobavail = mtd->oobavail; - size_t bitflips; - int i; - -@@ -394,8 +394,8 @@ static int __init mtd_oobtest_init(void) - goto out; - - use_offset = 0; -- use_len = mtd->ecclayout->oobavail; -- use_len_max = mtd->ecclayout->oobavail; -+ use_len = mtd->oobavail; -+ use_len_max = mtd->oobavail; - vary_offset = 0; - - /* First test: write all OOB, read it back and verify */ -@@ -460,8 +460,8 @@ static int __init mtd_oobtest_init(void) - - /* Write all eraseblocks */ - use_offset = 0; -- use_len = mtd->ecclayout->oobavail; -- use_len_max = mtd->ecclayout->oobavail; -+ use_len = mtd->oobavail; -+ use_len_max = mtd->oobavail; - vary_offset = 1; - prandom_seed_state(&rnd_state, 5); - -@@ -471,8 +471,8 @@ static int __init mtd_oobtest_init(void) - - /* Check all eraseblocks */ - use_offset = 0; -- use_len = mtd->ecclayout->oobavail; -- use_len_max = mtd->ecclayout->oobavail; -+ use_len = mtd->oobavail; -+ use_len_max = mtd->oobavail; - vary_offset = 1; - prandom_seed_state(&rnd_state, 5); - err = verify_all_eraseblocks(); -@@ -480,8 +480,8 @@ static int __init mtd_oobtest_init(void) - goto out; - - use_offset = 0; -- use_len = mtd->ecclayout->oobavail; -- use_len_max = mtd->ecclayout->oobavail; -+ use_len = mtd->oobavail; -+ use_len_max = mtd->oobavail; - vary_offset = 0; - - /* Fourth test: try to write off end of device */ -@@ -501,7 +501,7 @@ static int __init mtd_oobtest_init(void) - ops.retlen = 0; - ops.ooblen = 1; - ops.oobretlen = 0; -- ops.ooboffs = mtd->ecclayout->oobavail; -+ ops.ooboffs = mtd->oobavail; - ops.datbuf = NULL; - ops.oobbuf = writebuf; - pr_info("attempting to start write past end of OOB\n"); -@@ -521,7 +521,7 @@ static int __init mtd_oobtest_init(void) - ops.retlen = 0; - ops.ooblen = 1; - ops.oobretlen = 0; -- ops.ooboffs = mtd->ecclayout->oobavail; -+ ops.ooboffs = mtd->oobavail; - ops.datbuf = NULL; - ops.oobbuf = readbuf; - pr_info("attempting to start read past end of OOB\n"); -@@ -543,7 +543,7 @@ static int __init mtd_oobtest_init(void) - ops.mode = MTD_OPS_AUTO_OOB; - ops.len = 0; - ops.retlen = 0; -- ops.ooblen = mtd->ecclayout->oobavail + 1; -+ ops.ooblen = mtd->oobavail + 1; - ops.oobretlen = 0; - ops.ooboffs = 0; - ops.datbuf = NULL; -@@ -563,7 +563,7 @@ static int __init mtd_oobtest_init(void) - ops.mode = MTD_OPS_AUTO_OOB; - ops.len = 0; - ops.retlen = 0; -- ops.ooblen = mtd->ecclayout->oobavail + 1; -+ ops.ooblen = mtd->oobavail + 1; - ops.oobretlen = 0; - ops.ooboffs = 0; - ops.datbuf = NULL; -@@ -587,7 +587,7 @@ static int __init mtd_oobtest_init(void) - ops.mode = MTD_OPS_AUTO_OOB; - ops.len = 0; - ops.retlen = 0; -- ops.ooblen = mtd->ecclayout->oobavail; -+ ops.ooblen = mtd->oobavail; - ops.oobretlen = 0; - ops.ooboffs = 1; - ops.datbuf = NULL; -@@ -607,7 +607,7 @@ static int __init mtd_oobtest_init(void) - ops.mode = MTD_OPS_AUTO_OOB; - ops.len = 0; - ops.retlen = 0; -- ops.ooblen = mtd->ecclayout->oobavail; -+ ops.ooblen = mtd->oobavail; - ops.oobretlen = 0; - ops.ooboffs = 1; - ops.datbuf = NULL; -@@ -638,7 +638,7 @@ static int __init mtd_oobtest_init(void) - for (i = 0; i < ebcnt - 1; ++i) { - int cnt = 2; - int pg; -- size_t sz = mtd->ecclayout->oobavail; -+ size_t sz = mtd->oobavail; - if (bbt[i] || bbt[i + 1]) - continue; - addr = (loff_t)(i + 1) * mtd->erasesize - mtd->writesize; -@@ -673,13 +673,12 @@ static int __init mtd_oobtest_init(void) - for (i = 0; i < ebcnt - 1; ++i) { - if (bbt[i] || bbt[i + 1]) - continue; -- prandom_bytes_state(&rnd_state, writebuf, -- mtd->ecclayout->oobavail * 2); -+ prandom_bytes_state(&rnd_state, writebuf, mtd->oobavail * 2); - addr = (loff_t)(i + 1) * mtd->erasesize - mtd->writesize; - ops.mode = MTD_OPS_AUTO_OOB; - ops.len = 0; - ops.retlen = 0; -- ops.ooblen = mtd->ecclayout->oobavail * 2; -+ ops.ooblen = mtd->oobavail * 2; - ops.oobretlen = 0; - ops.ooboffs = 0; - ops.datbuf = NULL; -@@ -688,7 +687,7 @@ static int __init mtd_oobtest_init(void) - if (err) - goto out; - if (memcmpshow(addr, readbuf, writebuf, -- mtd->ecclayout->oobavail * 2)) { -+ mtd->oobavail * 2)) { - pr_err("error: verify failed at %#llx\n", - (long long)addr); - errcnt += 1; ---- a/drivers/mtd/tests/pagetest.c -+++ b/drivers/mtd/tests/pagetest.c -@@ -127,13 +127,12 @@ static int crosstest(void) - unsigned char *pp1, *pp2, *pp3, *pp4; - - pr_info("crosstest\n"); -- pp1 = kmalloc(pgsize * 4, GFP_KERNEL); -+ pp1 = kzalloc(pgsize * 4, GFP_KERNEL); - if (!pp1) - return -ENOMEM; - pp2 = pp1 + pgsize; - pp3 = pp2 + pgsize; - pp4 = pp3 + pgsize; -- memset(pp1, 0, pgsize * 4); - - addr0 = 0; - for (i = 0; i < ebcnt && bbt[i]; ++i) ---- a/include/linux/mtd/bbm.h -+++ b/include/linux/mtd/bbm.h -@@ -166,7 +166,6 @@ struct bbm_info { - }; - - /* OneNAND BBT interface */ --extern int onenand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); - extern int onenand_default_bbt(struct mtd_info *mtd); - - #endif /* __LINUX_MTD_BBM_H */ ---- a/include/linux/mtd/fsmc.h -+++ b/include/linux/mtd/fsmc.h -@@ -103,24 +103,6 @@ - - #define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ) - --/* -- * There are 13 bytes of ecc for every 512 byte block in FSMC version 8 -- * and it has to be read consecutively and immediately after the 512 -- * byte data block for hardware to generate the error bit offsets -- * Managing the ecc bytes in the following way is easier. This way is -- * similar to oobfree structure maintained already in u-boot nand driver -- */ --#define MAX_ECCPLACE_ENTRIES 32 -- --struct fsmc_nand_eccplace { -- uint8_t offset; -- uint8_t length; --}; -- --struct fsmc_eccplace { -- struct fsmc_nand_eccplace eccplace[MAX_ECCPLACE_ENTRIES]; --}; -- - struct fsmc_nand_timings { - uint8_t tclr; - uint8_t tar; ---- a/include/linux/mtd/inftl.h -+++ b/include/linux/mtd/inftl.h -@@ -44,7 +44,6 @@ struct INFTLrecord { - unsigned int nb_blocks; /* number of physical blocks */ - unsigned int nb_boot_blocks; /* number of blocks used by the bios */ - struct erase_info instr; -- struct nand_ecclayout oobinfo; - }; - - int INFTL_mount(struct INFTLrecord *s); ---- a/include/linux/mtd/map.h -+++ b/include/linux/mtd/map.h -@@ -137,7 +137,9 @@ - #endif - - #ifndef map_bankwidth -+#ifdef CONFIG_MTD - #warning "No CONFIG_MTD_MAP_BANK_WIDTH_xx selected. No NOR chip support can work" -+#endif - static inline int map_bankwidth(void *map) - { - BUG(); -@@ -233,8 +235,11 @@ struct map_info { - If there is no cache to care about this can be set to NULL. */ - void (*inval_cache)(struct map_info *, unsigned long, ssize_t); - -- /* set_vpp() must handle being reentered -- enable, enable, disable -- must leave it enabled. */ -+ /* This will be called with 1 as parameter when the first map user -+ * needs VPP, and called with 0 when the last user exits. The map -+ * core maintains a reference counter, and assumes that VPP is a -+ * global resource applying to all mapped flash chips on the system. -+ */ - void (*set_vpp)(struct map_info *, int); - - unsigned long pfow_base; ---- a/include/linux/mtd/mtd.h -+++ b/include/linux/mtd/mtd.h -@@ -100,17 +100,35 @@ struct mtd_oob_ops { - - #define MTD_MAX_OOBFREE_ENTRIES_LARGE 32 - #define MTD_MAX_ECCPOS_ENTRIES_LARGE 640 -+/** -+ * struct mtd_oob_region - oob region definition -+ * @offset: region offset -+ * @length: region length -+ * -+ * This structure describes a region of the OOB area, and is used -+ * to retrieve ECC or free bytes sections. -+ * Each section is defined by an offset within the OOB area and a -+ * length. -+ */ -+struct mtd_oob_region { -+ u32 offset; -+ u32 length; -+}; -+ - /* -- * Internal ECC layout control structure. For historical reasons, there is a -- * similar, smaller struct nand_ecclayout_user (in mtd-abi.h) that is retained -- * for export to user-space via the ECCGETLAYOUT ioctl. -- * nand_ecclayout should be expandable in the future simply by the above macros. -+ * struct mtd_ooblayout_ops - NAND OOB layout operations -+ * @ecc: function returning an ECC region in the OOB area. -+ * Should return -ERANGE if %section exceeds the total number of -+ * ECC sections. -+ * @free: function returning a free region in the OOB area. -+ * Should return -ERANGE if %section exceeds the total number of -+ * free sections. - */ --struct nand_ecclayout { -- __u32 eccbytes; -- __u32 eccpos[MTD_MAX_ECCPOS_ENTRIES_LARGE]; -- __u32 oobavail; -- struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES_LARGE]; -+struct mtd_ooblayout_ops { -+ int (*ecc)(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobecc); -+ int (*free)(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobfree); - }; - - struct module; /* only needed for owner field in mtd_info */ -@@ -171,8 +189,8 @@ struct mtd_info { - const char *name; - int index; - -- /* ECC layout structure pointer - read only! */ -- struct nand_ecclayout *ecclayout; -+ /* OOB layout description */ -+ const struct mtd_ooblayout_ops *ooblayout; - - /* the ecc step size. */ - unsigned int ecc_step_size; -@@ -258,6 +276,46 @@ struct mtd_info { - int usecount; - }; - -+int mtd_ooblayout_ecc(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobecc); -+int mtd_ooblayout_find_eccregion(struct mtd_info *mtd, int eccbyte, -+ int *section, -+ struct mtd_oob_region *oobregion); -+int mtd_ooblayout_get_eccbytes(struct mtd_info *mtd, u8 *eccbuf, -+ const u8 *oobbuf, int start, int nbytes); -+int mtd_ooblayout_set_eccbytes(struct mtd_info *mtd, const u8 *eccbuf, -+ u8 *oobbuf, int start, int nbytes); -+int mtd_ooblayout_free(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobfree); -+int mtd_ooblayout_get_databytes(struct mtd_info *mtd, u8 *databuf, -+ const u8 *oobbuf, int start, int nbytes); -+int mtd_ooblayout_set_databytes(struct mtd_info *mtd, const u8 *databuf, -+ u8 *oobbuf, int start, int nbytes); -+int mtd_ooblayout_count_freebytes(struct mtd_info *mtd); -+int mtd_ooblayout_count_eccbytes(struct mtd_info *mtd); -+ -+static inline void mtd_set_ooblayout(struct mtd_info *mtd, -+ const struct mtd_ooblayout_ops *ooblayout) -+{ -+ mtd->ooblayout = ooblayout; -+} -+ -+static inline void mtd_set_of_node(struct mtd_info *mtd, -+ struct device_node *np) -+{ -+ mtd->dev.of_node = np; -+} -+ -+static inline struct device_node *mtd_get_of_node(struct mtd_info *mtd) -+{ -+ return mtd->dev.of_node; -+} -+ -+static inline int mtd_oobavail(struct mtd_info *mtd, struct mtd_oob_ops *ops) -+{ -+ return ops->mode == MTD_OPS_AUTO_OOB ? mtd->oobavail : mtd->oobsize; -+} -+ - int mtd_erase(struct mtd_info *mtd, struct erase_info *instr); - int mtd_point(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, - void **virt, resource_size_t *phys); ---- a/include/linux/mtd/nand.h -+++ b/include/linux/mtd/nand.h -@@ -119,6 +119,12 @@ typedef enum { - NAND_ECC_SOFT_BCH, - } nand_ecc_modes_t; - -+enum nand_ecc_algo { -+ NAND_ECC_UNKNOWN, -+ NAND_ECC_HAMMING, -+ NAND_ECC_BCH, -+}; -+ - /* - * Constants for Hardware ECC - */ -@@ -129,6 +135,14 @@ typedef enum { - /* Enable Hardware ECC before syndrome is read back from flash */ - #define NAND_ECC_READSYN 2 - -+/* -+ * Enable generic NAND 'page erased' check. This check is only done when -+ * ecc.correct() returns -EBADMSG. -+ * Set this flag if your implementation does not fix bitflips in erased -+ * pages and you want to rely on the default implementation. -+ */ -+#define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) -+ - /* Bit mask for flags passed to do_nand_read_ecc */ - #define NAND_GET_DEVICE 0x80 - -@@ -160,6 +174,12 @@ typedef enum { - /* Device supports subpage reads */ - #define NAND_SUBPAGE_READ 0x00001000 - -+/* -+ * Some MLC NANDs need data scrambling to limit bitflips caused by repeated -+ * patterns. -+ */ -+#define NAND_NEED_SCRAMBLING 0x00002000 -+ - /* Options valid for Samsung large page devices */ - #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG - -@@ -276,15 +296,15 @@ struct nand_onfi_params { - __le16 t_r; - __le16 t_ccs; - __le16 src_sync_timing_mode; -- __le16 src_ssync_features; -+ u8 src_ssync_features; - __le16 clk_pin_capacitance_typ; - __le16 io_pin_capacitance_typ; - __le16 input_pin_capacitance_typ; - u8 input_pin_capacitance_max; - u8 driver_strength_support; - __le16 t_int_r; -- __le16 t_ald; -- u8 reserved4[7]; -+ __le16 t_adl; -+ u8 reserved4[8]; - - /* vendor */ - __le16 vendor_revision; -@@ -407,7 +427,7 @@ struct nand_jedec_params { - __le16 input_pin_capacitance_typ; - __le16 clk_pin_capacitance_typ; - u8 driver_strength_support; -- __le16 t_ald; -+ __le16 t_adl; - u8 reserved4[36]; - - /* ECC and endurance block */ -@@ -444,6 +464,7 @@ struct nand_hw_control { - /** - * struct nand_ecc_ctrl - Control structure for ECC - * @mode: ECC mode -+ * @algo: ECC algorithm - * @steps: number of ECC steps per page - * @size: data bytes per ECC step - * @bytes: ECC bytes per step -@@ -451,12 +472,18 @@ struct nand_hw_control { - * @total: total number of ECC bytes per page - * @prepad: padding information for syndrome based ECC generators - * @postpad: padding information for syndrome based ECC generators -- * @layout: ECC layout control struct pointer -+ * @options: ECC specific options (see NAND_ECC_XXX flags defined above) - * @priv: pointer to private ECC control data - * @hwctl: function to control hardware ECC generator. Must only - * be provided if an hardware ECC is available - * @calculate: function for ECC calculation or readback from ECC hardware -- * @correct: function for ECC correction, matching to ECC generator (sw/hw) -+ * @correct: function for ECC correction, matching to ECC generator (sw/hw). -+ * Should return a positive number representing the number of -+ * corrected bitflips, -EBADMSG if the number of bitflips exceed -+ * ECC strength, or any other error code if the error is not -+ * directly related to correction. -+ * If -EBADMSG is returned the input buffers should be left -+ * untouched. - * @read_page_raw: function to read a raw page without ECC. This function - * should hide the specific layout used by the ECC - * controller and always return contiguous in-band and -@@ -487,6 +514,7 @@ struct nand_hw_control { - */ - struct nand_ecc_ctrl { - nand_ecc_modes_t mode; -+ enum nand_ecc_algo algo; - int steps; - int size; - int bytes; -@@ -494,7 +522,7 @@ struct nand_ecc_ctrl { - int strength; - int prepad; - int postpad; -- struct nand_ecclayout *layout; -+ unsigned int options; - void *priv; - void (*hwctl)(struct mtd_info *mtd, int mode); - int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, -@@ -540,11 +568,11 @@ struct nand_buffers { - - /** - * struct nand_chip - NAND Private Flash Chip Data -+ * @mtd: MTD device registered to the MTD framework - * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the - * flash device - * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the - * flash device. -- * @flash_node: [BOARDSPECIFIC] device node describing this instance - * @read_byte: [REPLACEABLE] read one byte from the chip - * @read_word: [REPLACEABLE] read one word from the chip - * @write_byte: [REPLACEABLE] write a single byte to the chip on the -@@ -640,18 +668,17 @@ struct nand_buffers { - */ - - struct nand_chip { -+ struct mtd_info mtd; - void __iomem *IO_ADDR_R; - void __iomem *IO_ADDR_W; - -- struct device_node *flash_node; -- - uint8_t (*read_byte)(struct mtd_info *mtd); - u16 (*read_word)(struct mtd_info *mtd); - void (*write_byte)(struct mtd_info *mtd, uint8_t byte); - void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); - void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); - void (*select_chip)(struct mtd_info *mtd, int chip); -- int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); -+ int (*block_bad)(struct mtd_info *mtd, loff_t ofs); - int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); - void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); - int (*dev_ready)(struct mtd_info *mtd); -@@ -719,6 +746,40 @@ struct nand_chip { - void *priv; - }; - -+extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops; -+extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops; -+ -+static inline void nand_set_flash_node(struct nand_chip *chip, -+ struct device_node *np) -+{ -+ mtd_set_of_node(&chip->mtd, np); -+} -+ -+static inline struct device_node *nand_get_flash_node(struct nand_chip *chip) -+{ -+ return mtd_get_of_node(&chip->mtd); -+} -+ -+static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) -+{ -+ return container_of(mtd, struct nand_chip, mtd); -+} -+ -+static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip) -+{ -+ return &chip->mtd; -+} -+ -+static inline void *nand_get_controller_data(struct nand_chip *chip) -+{ -+ return chip->priv; -+} -+ -+static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) -+{ -+ chip->priv = priv; -+} -+ - /* - * NAND Flash Manufacturer ID Codes - */ -@@ -851,7 +912,6 @@ extern int nand_do_read(struct mtd_info - * @chip_delay: R/B delay value in us - * @options: Option flags, e.g. 16bit buswidth - * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH -- * @ecclayout: ECC layout info structure - * @part_probe_types: NULL-terminated array of probe types - */ - struct platform_nand_chip { -@@ -859,7 +919,6 @@ struct platform_nand_chip { - int chip_offset; - int nr_partitions; - struct mtd_partition *partitions; -- struct nand_ecclayout *ecclayout; - int chip_delay; - unsigned int options; - unsigned int bbt_options; -@@ -909,15 +968,6 @@ struct platform_nand_data { - struct platform_nand_ctrl ctrl; - }; - --/* Some helpers to access the data structures */ --static inline --struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd) --{ -- struct nand_chip *chip = mtd->priv; -- -- return chip->priv; --} -- - /* return the supported features. */ - static inline int onfi_feature(struct nand_chip *chip) - { ---- a/include/linux/mtd/nand_bch.h -+++ b/include/linux/mtd/nand_bch.h -@@ -32,9 +32,7 @@ int nand_bch_correct_data(struct mtd_inf - /* - * Initialize BCH encoder/decoder - */ --struct nand_bch_control * --nand_bch_init(struct mtd_info *mtd, unsigned int eccsize, -- unsigned int eccbytes, struct nand_ecclayout **ecclayout); -+struct nand_bch_control *nand_bch_init(struct mtd_info *mtd); - /* - * Release BCH encoder/decoder resources - */ -@@ -55,12 +53,10 @@ static inline int - nand_bch_correct_data(struct mtd_info *mtd, unsigned char *buf, - unsigned char *read_ecc, unsigned char *calc_ecc) - { -- return -1; -+ return -ENOTSUPP; - } - --static inline struct nand_bch_control * --nand_bch_init(struct mtd_info *mtd, unsigned int eccsize, -- unsigned int eccbytes, struct nand_ecclayout **ecclayout) -+static inline struct nand_bch_control *nand_bch_init(struct mtd_info *mtd) - { - return NULL; - } ---- a/include/linux/mtd/nftl.h -+++ b/include/linux/mtd/nftl.h -@@ -50,7 +50,6 @@ struct NFTLrecord { - unsigned int nb_blocks; /* number of physical blocks */ - unsigned int nb_boot_blocks; /* number of blocks used by the bios */ - struct erase_info instr; -- struct nand_ecclayout oobinfo; - }; - - int NFTL_mount(struct NFTLrecord *s); ---- a/include/linux/mtd/onenand.h -+++ b/include/linux/mtd/onenand.h -@@ -80,7 +80,6 @@ struct onenand_bufferram { - * @page_buf: [INTERN] page main data buffer - * @oob_buf: [INTERN] page oob data buffer - * @subpagesize: [INTERN] holds the subpagesize -- * @ecclayout: [REPLACEABLE] the default ecc placement scheme - * @bbm: [REPLACEABLE] pointer to Bad Block Management - * @priv: [OPTIONAL] pointer to private chip date - */ -@@ -134,7 +133,6 @@ struct onenand_chip { - #endif - - int subpagesize; -- struct nand_ecclayout *ecclayout; - - void *bbm; - ---- a/include/linux/mtd/partitions.h -+++ b/include/linux/mtd/partitions.h -@@ -42,7 +42,6 @@ struct mtd_partition { - uint64_t size; /* partition size */ - uint64_t offset; /* offset within the master MTD space */ - uint32_t mask_flags; /* master MTD flags to mask out for this partition */ -- struct nand_ecclayout *ecclayout; /* out of band layout for this partition (NAND only) */ - }; - - #define MTDPART_OFS_RETAIN (-3) -@@ -56,11 +55,9 @@ struct device_node; - /** - * struct mtd_part_parser_data - used to pass data to MTD partition parsers. - * @origin: for RedBoot, start address of MTD device -- * @of_node: for OF parsers, device node containing partitioning information - */ - struct mtd_part_parser_data { - unsigned long origin; -- struct device_node *of_node; - }; - - -@@ -78,14 +75,34 @@ struct mtd_part_parser { - struct list_head list; - struct module *owner; - const char *name; -- int (*parse_fn)(struct mtd_info *, struct mtd_partition **, -+ int (*parse_fn)(struct mtd_info *, const struct mtd_partition **, - struct mtd_part_parser_data *); -+ void (*cleanup)(const struct mtd_partition *pparts, int nr_parts); - enum mtd_parser_type type; - }; - --extern void register_mtd_parser(struct mtd_part_parser *parser); -+/* Container for passing around a set of parsed partitions */ -+struct mtd_partitions { -+ const struct mtd_partition *parts; -+ int nr_parts; -+ const struct mtd_part_parser *parser; -+}; -+ -+extern int __register_mtd_parser(struct mtd_part_parser *parser, -+ struct module *owner); -+#define register_mtd_parser(parser) __register_mtd_parser(parser, THIS_MODULE) -+ - extern void deregister_mtd_parser(struct mtd_part_parser *parser); - -+/* -+ * module_mtd_part_parser() - Helper macro for MTD partition parsers that don't -+ * do anything special in module init/exit. Each driver may only use this macro -+ * once, and calling it replaces module_init() and module_exit(). -+ */ -+#define module_mtd_part_parser(__mtd_part_parser) \ -+ module_driver(__mtd_part_parser, register_mtd_parser, \ -+ deregister_mtd_parser) -+ - int mtd_is_partition(const struct mtd_info *mtd); - int mtd_add_partition(struct mtd_info *master, const char *name, - long long offset, long long length); ---- a/include/linux/mtd/sh_flctl.h -+++ b/include/linux/mtd/sh_flctl.h -@@ -143,7 +143,6 @@ enum flctl_ecc_res_t { - struct dma_chan; - - struct sh_flctl { -- struct mtd_info mtd; - struct nand_chip chip; - struct platform_device *pdev; - struct dev_pm_qos_request pm_qos; -@@ -187,7 +186,7 @@ struct sh_flctl_platform_data { - - static inline struct sh_flctl *mtd_to_flctl(struct mtd_info *mtdinfo) - { -- return container_of(mtdinfo, struct sh_flctl, mtd); -+ return container_of(mtd_to_nand(mtdinfo), struct sh_flctl, chip); - } - - #endif /* __SH_FLCTL_H__ */ ---- a/include/linux/mtd/sharpsl.h -+++ b/include/linux/mtd/sharpsl.h -@@ -14,7 +14,7 @@ - - struct sharpsl_nand_platform_data { - struct nand_bbt_descr *badblock_pattern; -- struct nand_ecclayout *ecc_layout; -+ const struct mtd_ooblayout_ops *ecc_layout; - struct mtd_partition *partitions; - unsigned int nr_partitions; - }; ---- a/include/uapi/mtd/mtd-abi.h -+++ b/include/uapi/mtd/mtd-abi.h -@@ -228,7 +228,7 @@ struct nand_oobfree { - * complete set of ECC information. The ioctl truncates the larger internal - * structure to retain binary compatibility with the static declaration of the - * ioctl. Note that the "MTD_MAX_..._ENTRIES" macros represent the max size of -- * the user struct, not the MAX size of the internal struct nand_ecclayout. -+ * the user struct, not the MAX size of the internal OOB layout representation. - */ - struct nand_ecclayout_user { - __u32 eccbytes; ---- a/fs/jffs2/wbuf.c -+++ b/fs/jffs2/wbuf.c -@@ -1153,7 +1153,7 @@ static struct jffs2_sb_info *work_to_sb( - { - struct delayed_work *dwork; - -- dwork = container_of(work, struct delayed_work, work); -+ dwork = to_delayed_work(work); - return container_of(dwork, struct jffs2_sb_info, wbuf_dwork); - } - -@@ -1183,22 +1183,20 @@ void jffs2_dirty_trigger(struct jffs2_sb - - int jffs2_nand_flash_setup(struct jffs2_sb_info *c) - { -- struct nand_ecclayout *oinfo = c->mtd->ecclayout; -- - if (!c->mtd->oobsize) - return 0; - - /* Cleanmarker is out-of-band, so inline size zero */ - c->cleanmarker_size = 0; - -- if (!oinfo || oinfo->oobavail == 0) { -+ if (c->mtd->oobavail == 0) { - pr_err("inconsistent device description\n"); - return -EINVAL; - } - - jffs2_dbg(1, "using OOB on NAND\n"); - -- c->oobavail = oinfo->oobavail; -+ c->oobavail = c->mtd->oobavail; - - /* Initialise write buffer */ - init_rwsem(&c->wbuf_sem); ---- a/include/linux/mtd/spi-nor.h -+++ b/include/linux/mtd/spi-nor.h -@@ -85,6 +85,7 @@ - #define SR_BP0 BIT(2) /* Block protect 0 */ - #define SR_BP1 BIT(3) /* Block protect 1 */ - #define SR_BP2 BIT(4) /* Block protect 2 */ -+#define SR_TB BIT(5) /* Top/Bottom protect */ - #define SR_SRWD BIT(7) /* SR write protect */ - - #define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */ -@@ -116,6 +117,7 @@ enum spi_nor_ops { - - enum spi_nor_option_flags { - SNOR_F_USE_FSR = BIT(0), -+ SNOR_F_HAS_SR_TB = BIT(1), - }; - - /** -@@ -123,7 +125,6 @@ enum spi_nor_option_flags { - * @mtd: point to a mtd_info structure - * @lock: the lock for the read/write/erase/lock/unlock operations - * @dev: point to a spi device, or a spi nor controller device. -- * @flash_node: point to a device node describing this flash instance. - * @page_size: the page size of the SPI NOR - * @addr_width: number of address bytes - * @erase_opcode: the opcode for erasing a sector -@@ -143,7 +144,8 @@ enum spi_nor_option_flags { - * @read: [DRIVER-SPECIFIC] read data from the SPI NOR - * @write: [DRIVER-SPECIFIC] write data to the SPI NOR - * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR -- * at the offset @offs -+ * at the offset @offs; if not provided by the driver, -+ * spi-nor will send the erase opcode via write_reg() - * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR - * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR - * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is -@@ -154,7 +156,6 @@ struct spi_nor { - struct mtd_info mtd; - struct mutex lock; - struct device *dev; -- struct device_node *flash_node; - u32 page_size; - u8 addr_width; - u8 erase_opcode; -@@ -184,6 +185,17 @@ struct spi_nor { - void *priv; - }; - -+static inline void spi_nor_set_flash_node(struct spi_nor *nor, -+ struct device_node *np) -+{ -+ mtd_set_of_node(&nor->mtd, np); -+} -+ -+static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor) -+{ -+ return mtd_get_of_node(&nor->mtd); -+} -+ - /** - * spi_nor_scan() - scan the SPI NOR - * @nor: the spi_nor structure diff --git a/target/linux/oxnas/patches-4.4/0073-of-mtd-prepare-helper-reading-NAND-ECC-algo-from-DT.patch b/target/linux/oxnas/patches-4.4/0073-of-mtd-prepare-helper-reading-NAND-ECC-algo-from-DT.patch deleted file mode 100644 index aa45441afa..0000000000 --- a/target/linux/oxnas/patches-4.4/0073-of-mtd-prepare-helper-reading-NAND-ECC-algo-from-DT.patch +++ /dev/null @@ -1,91 +0,0 @@ -From 410a91f6efa1c4c3c4369d1dd2c31286749dff33 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> -Date: Wed, 23 Mar 2016 11:19:01 +0100 -Subject: [PATCH 073/102] of: mtd: prepare helper reading NAND ECC algo from - DT -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -NAND subsystem is being slightly reworked to store ECC details in -separated fields. In future we'll want to add support for more DT -properties as specifying every possible setup with a single -"nand-ecc-mode" is a pretty bad idea. -To allow this let's add a helper that will support something like -"nand-ecc-algo" in future. Right now we use it for keeping backward -compatibility. - -Signed-off-by: Rafał Miłecki <zajec5@gmail.com> -Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> ---- - drivers/of/of_mtd.c | 36 ++++++++++++++++++++++++++++++++++++ - include/linux/of_mtd.h | 6 ++++++ - 2 files changed, 42 insertions(+) - ---- a/drivers/of/of_mtd.c -+++ b/drivers/of/of_mtd.c -@@ -50,6 +50,42 @@ int of_get_nand_ecc_mode(struct device_n - EXPORT_SYMBOL_GPL(of_get_nand_ecc_mode); - - /** -+ * of_get_nand_ecc_algo - Get nand ecc algorithm for given device_node -+ * @np: Pointer to the given device_node -+ * -+ * The function gets ecc algorithm and returns its enum value, or errno in error -+ * case. -+ */ -+int of_get_nand_ecc_algo(struct device_node *np) -+{ -+ const char *pm; -+ int err; -+ -+ /* -+ * TODO: Read ECC algo OF property and map it to enum nand_ecc_algo. -+ * It's not implemented yet as currently NAND subsystem ignores -+ * algorithm explicitly set this way. Once it's handled we should -+ * document & support new property. -+ */ -+ -+ /* -+ * For backward compatibility we also read "nand-ecc-mode" checking -+ * for some obsoleted values that were specifying ECC algorithm. -+ */ -+ err = of_property_read_string(np, "nand-ecc-mode", &pm); -+ if (err < 0) -+ return err; -+ -+ if (!strcasecmp(pm, "soft")) -+ return NAND_ECC_HAMMING; -+ else if (!strcasecmp(pm, "soft_bch")) -+ return NAND_ECC_BCH; -+ -+ return -ENODEV; -+} -+EXPORT_SYMBOL_GPL(of_get_nand_ecc_algo); -+ -+/** - * of_get_nand_ecc_step_size - Get ECC step size associated to - * the required ECC strength (see below). - * @np: Pointer to the given device_node ---- a/include/linux/of_mtd.h -+++ b/include/linux/of_mtd.h -@@ -13,6 +13,7 @@ - - #include <linux/of.h> - int of_get_nand_ecc_mode(struct device_node *np); -+int of_get_nand_ecc_algo(struct device_node *np); - int of_get_nand_ecc_step_size(struct device_node *np); - int of_get_nand_ecc_strength(struct device_node *np); - int of_get_nand_bus_width(struct device_node *np); -@@ -24,6 +25,11 @@ static inline int of_get_nand_ecc_mode(s - { - return -ENOSYS; - } -+ -+static inline int of_get_nand_ecc_algo(struct device_node *np) -+{ -+ return -ENOSYS; -+} - - static inline int of_get_nand_ecc_step_size(struct device_node *np) - { diff --git a/target/linux/oxnas/patches-4.4/0074-mtd-nand-import-nand_hw_control_init.patch b/target/linux/oxnas/patches-4.4/0074-mtd-nand-import-nand_hw_control_init.patch deleted file mode 100644 index 8ff28b3bc2..0000000000 --- a/target/linux/oxnas/patches-4.4/0074-mtd-nand-import-nand_hw_control_init.patch +++ /dev/null @@ -1,175 +0,0 @@ -From d45bc58dd3bdcaabc1d7d8d9b0b8dee826635cc6 Mon Sep 17 00:00:00 2001 -From: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> -Date: Wed, 27 Jul 2016 11:23:52 +0200 -Subject: [PATCH] mtd: nand: import nand_hw_control_init() - -The code to initialize a struct nand_hw_control is duplicated across -several drivers. Factorize it using an inline function. - -Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> -Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> ---- - drivers/mtd/nand/bf5xx_nand.c | 3 +-- - drivers/mtd/nand/brcmnand/brcmnand.c | 3 +-- - drivers/mtd/nand/docg4.c | 3 +-- - drivers/mtd/nand/fsl_elbc_nand.c | 3 +-- - drivers/mtd/nand/fsl_ifc_nand.c | 3 +-- - drivers/mtd/nand/jz4780_nand.c | 3 +-- - drivers/mtd/nand/nand_base.c | 3 +-- - drivers/mtd/nand/ndfc.c | 3 +-- - drivers/mtd/nand/pxa3xx_nand.c | 3 +-- - drivers/mtd/nand/qcom_nandc.c | 3 +-- - drivers/mtd/nand/s3c2410.c | 3 +-- - drivers/mtd/nand/sunxi_nand.c | 3 +-- - drivers/mtd/nand/txx9ndfmc.c | 3 +-- - include/linux/mtd/nand.h | 7 +++++++ - 14 files changed, 20 insertions(+), 26 deletions(-) - ---- a/drivers/mtd/nand/bf5xx_nand.c -+++ b/drivers/mtd/nand/bf5xx_nand.c -@@ -748,8 +748,7 @@ static int bf5xx_nand_probe(struct platf - - platform_set_drvdata(pdev, info); - -- spin_lock_init(&info->controller.lock); -- init_waitqueue_head(&info->controller.wq); -+ nand_hw_control_init(&info->controller); - - info->device = &pdev->dev; - info->platform = plat; ---- a/drivers/mtd/nand/brcmnand/brcmnand.c -+++ b/drivers/mtd/nand/brcmnand/brcmnand.c -@@ -2149,8 +2149,7 @@ int brcmnand_probe(struct platform_devic - - init_completion(&ctrl->done); - init_completion(&ctrl->dma_done); -- spin_lock_init(&ctrl->controller.lock); -- init_waitqueue_head(&ctrl->controller.wq); -+ nand_hw_control_init(&ctrl->controller); - INIT_LIST_HEAD(&ctrl->host_list); - - /* NAND register range */ ---- a/drivers/mtd/nand/docg4.c -+++ b/drivers/mtd/nand/docg4.c -@@ -1227,8 +1227,7 @@ static void __init init_mtd_structs(stru - nand->options = NAND_BUSWIDTH_16 | NAND_NO_SUBPAGE_WRITE; - nand->IO_ADDR_R = nand->IO_ADDR_W = doc->virtadr + DOC_IOSPACE_DATA; - nand->controller = &nand->hwcontrol; -- spin_lock_init(&nand->controller->lock); -- init_waitqueue_head(&nand->controller->wq); -+ nand_hw_control_init(nand->controller); - - /* methods */ - nand->cmdfunc = docg4_command; ---- a/drivers/mtd/nand/fsl_elbc_nand.c -+++ b/drivers/mtd/nand/fsl_elbc_nand.c -@@ -866,8 +866,7 @@ static int fsl_elbc_nand_probe(struct pl - } - elbc_fcm_ctrl->counter++; - -- spin_lock_init(&elbc_fcm_ctrl->controller.lock); -- init_waitqueue_head(&elbc_fcm_ctrl->controller.wq); -+ nand_hw_control_init(&elbc_fcm_ctrl->controller); - fsl_lbc_ctrl_dev->nand = elbc_fcm_ctrl; - } else { - elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand; ---- a/drivers/mtd/nand/fsl_ifc_nand.c -+++ b/drivers/mtd/nand/fsl_ifc_nand.c -@@ -1073,8 +1073,7 @@ static int fsl_ifc_nand_probe(struct pla - ifc_nand_ctrl->addr = NULL; - fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl; - -- spin_lock_init(&ifc_nand_ctrl->controller.lock); -- init_waitqueue_head(&ifc_nand_ctrl->controller.wq); -+ nand_hw_control_init(&ifc_nand_ctrl->controller); - } else { - ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand; - } ---- a/drivers/mtd/nand/nand_base.c -+++ b/drivers/mtd/nand/nand_base.c -@@ -3208,8 +3208,7 @@ static void nand_set_defaults(struct nan - - if (!chip->controller) { - chip->controller = &chip->hwcontrol; -- spin_lock_init(&chip->controller->lock); -- init_waitqueue_head(&chip->controller->wq); -+ nand_hw_control_init(chip->controller); - } - - } ---- a/drivers/mtd/nand/ndfc.c -+++ b/drivers/mtd/nand/ndfc.c -@@ -220,8 +220,7 @@ static int ndfc_probe(struct platform_de - ndfc = &ndfc_ctrl[cs]; - ndfc->chip_select = cs; - -- spin_lock_init(&ndfc->ndfc_control.lock); -- init_waitqueue_head(&ndfc->ndfc_control.wq); -+ nand_hw_control_init(&ndfc->ndfc_control); - ndfc->ofdev = ofdev; - dev_set_drvdata(&ofdev->dev, ndfc); - ---- a/drivers/mtd/nand/pxa3xx_nand.c -+++ b/drivers/mtd/nand/pxa3xx_nand.c -@@ -1739,8 +1739,7 @@ static int alloc_nand_resource(struct pl - chip->cmdfunc = nand_cmdfunc; - } - -- spin_lock_init(&chip->controller->lock); -- init_waitqueue_head(&chip->controller->wq); -+ nand_hw_control_init(chip->controller); - info->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(info->clk)) { - dev_err(&pdev->dev, "failed to get nand clock\n"); ---- a/drivers/mtd/nand/s3c2410.c -+++ b/drivers/mtd/nand/s3c2410.c -@@ -955,8 +955,7 @@ static int s3c24xx_nand_probe(struct pla - - platform_set_drvdata(pdev, info); - -- spin_lock_init(&info->controller.lock); -- init_waitqueue_head(&info->controller.wq); -+ nand_hw_control_init(&info->controller); - - /* get the clock source and enable it */ - ---- a/drivers/mtd/nand/sunxi_nand.c -+++ b/drivers/mtd/nand/sunxi_nand.c -@@ -1432,8 +1432,7 @@ static int sunxi_nfc_probe(struct platfo - return -ENOMEM; - - nfc->dev = dev; -- spin_lock_init(&nfc->controller.lock); -- init_waitqueue_head(&nfc->controller.wq); -+ nand_hw_control_init(&nfc->controller); - INIT_LIST_HEAD(&nfc->chips); - - r = platform_get_resource(pdev, IORESOURCE_MEM, 0); ---- a/drivers/mtd/nand/txx9ndfmc.c -+++ b/drivers/mtd/nand/txx9ndfmc.c -@@ -304,8 +304,7 @@ static int __init txx9ndfmc_probe(struct - dev_info(&dev->dev, "CLK:%ldMHz HOLD:%d SPW:%d\n", - (gbusclk + 500000) / 1000000, hold, spw); - -- spin_lock_init(&drvdata->hw_control.lock); -- init_waitqueue_head(&drvdata->hw_control.wq); -+ nand_hw_control_init(&drvdata->hw_control); - - platform_set_drvdata(dev, drvdata); - txx9ndfmc_initialize(dev); ---- a/include/linux/mtd/nand.h -+++ b/include/linux/mtd/nand.h -@@ -461,6 +461,13 @@ struct nand_hw_control { - wait_queue_head_t wq; - }; - -+static inline void nand_hw_control_init(struct nand_hw_control *nfc) -+{ -+ nfc->active = NULL; -+ spin_lock_init(&nfc->lock); -+ init_waitqueue_head(&nfc->wq); -+} -+ - /** - * struct nand_ecc_ctrl - Control structure for ECC - * @mode: ECC mode diff --git a/target/linux/oxnas/patches-4.4/010-arm_introduce-dma-fiq-irq-broadcast.patch b/target/linux/oxnas/patches-4.4/010-arm_introduce-dma-fiq-irq-broadcast.patch deleted file mode 100644 index 024675e599..0000000000 --- a/target/linux/oxnas/patches-4.4/010-arm_introduce-dma-fiq-irq-broadcast.patch +++ /dev/null @@ -1,80 +0,0 @@ ---- a/arch/arm/include/asm/glue-cache.h -+++ b/arch/arm/include/asm/glue-cache.h -@@ -156,9 +156,15 @@ static inline void nop_dma_unmap_area(co - #define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range) - #define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range) - #define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range) --#define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area) - --#define dmac_flush_range __glue(_CACHE,_dma_flush_range) -+#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST -+# define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area) -+# define dmac_flush_range __glue(_CACHE,_dma_flush_range) -+#else -+# define __cpuc_flush_dcache_area __glue(fiq,_flush_kern_dcache_area) -+# define dmac_flush_range __glue(fiq,_dma_flush_range) -+#endif -+ - #endif - - #endif ---- a/arch/arm/mm/Kconfig -+++ b/arch/arm/mm/Kconfig -@@ -866,6 +866,17 @@ config DMA_CACHE_RWFO - in hardware, other workarounds are needed (e.g. cache - maintenance broadcasting in software via FIQ). - -+config DMA_CACHE_FIQ_BROADCAST -+ bool "Enable fiq broadcast DMA cache maintenance" -+ depends on CPU_V6K && SMP -+ select FIQ -+ help -+ The Snoop Control Unit on ARM11MPCore does not detect the -+ cache maintenance operations and the dma_{map,unmap}_area() -+ functions may leave stale cache entries on other CPUs. By -+ enabling this option, fiq broadcast in the ARMv6 -+ DMA cache maintenance functions is performed. -+ - config OUTER_CACHE - bool - ---- a/arch/arm/mm/flush.c -+++ b/arch/arm/mm/flush.c -@@ -319,6 +319,7 @@ void __sync_icache_dcache(pte_t pteval) - void flush_dcache_page(struct page *page) - { - struct address_space *mapping; -+ bool skip_broadcast = true; - - /* - * The zero page is never written to, so never has any dirty -@@ -329,7 +330,10 @@ void flush_dcache_page(struct page *page - - mapping = page_mapping(page); - -- if (!cache_ops_need_broadcast() && -+#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST -+ skip_broadcast = !cache_ops_need_broadcast(); -+#endif -+ if (skip_broadcast && - mapping && !page_mapped(page)) - clear_bit(PG_dcache_clean, &page->flags); - else { ---- a/arch/arm/mm/dma.h -+++ b/arch/arm/mm/dma.h -@@ -4,8 +4,13 @@ - #include <asm/glue-cache.h> - - #ifndef MULTI_CACHE --#define dmac_map_area __glue(_CACHE,_dma_map_area) --#define dmac_unmap_area __glue(_CACHE,_dma_unmap_area) -+#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST -+# define dmac_map_area __glue(_CACHE,_dma_map_area) -+# define dmac_unmap_area __glue(_CACHE,_dma_unmap_area) -+#else -+# define dmac_map_area __glue(fiq,_dma_map_area) -+# define dmac_unmap_area __glue(fiq,_dma_unmap_area) -+#endif - - /* - * These are private to the dma-mapping API. Do not use directly. diff --git a/target/linux/oxnas/patches-4.4/250-add-plxtech-vendor-prefix.patch b/target/linux/oxnas/patches-4.4/250-add-plxtech-vendor-prefix.patch deleted file mode 100644 index a94ac2277b..0000000000 --- a/target/linux/oxnas/patches-4.4/250-add-plxtech-vendor-prefix.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/Documentation/devicetree/bindings/vendor-prefixes.txt -+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt -@@ -175,6 +175,7 @@ picochip Picochip Ltd - plathome Plat'Home Co., Ltd. - plda PLDA - pixcir PIXCIR MICROELECTRONICS Co., Ltd -+plxtech PLX Technology, Inc. - pulsedlight PulsedLight, Inc - powervr PowerVR (deprecated, use img) - qca Qualcomm Atheros, Inc. diff --git a/target/linux/oxnas/patches-4.4/300-introduce-oxnas-platform.patch b/target/linux/oxnas/patches-4.4/300-introduce-oxnas-platform.patch deleted file mode 100644 index a88d5d94b5..0000000000 --- a/target/linux/oxnas/patches-4.4/300-introduce-oxnas-platform.patch +++ /dev/null @@ -1,71 +0,0 @@ ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -603,6 +603,19 @@ config ARCH_LPC32XX - help - Support for the NXP LPC32XX family of processors - -+config ARCH_OXNAS -+ bool "Oxford Semiconductor 815/820/825 NAS SoC" -+ select ARM_GIC -+ select ARCH_REQUIRE_GPIOLIB -+ select CLKDEV_LOOKUP -+ select GENERIC_CLOCKEVENTS -+ select COMMON_CLK -+ select MIGHT_HAVE_PCI -+ select ARCH_HAS_RESET_CONTROLLER -+ help -+ This enables support for Oxford 815/820/825 NAS SoC -+ later renamed to PLXTECH NAS782x. -+ - config ARCH_PXA - bool "PXA2xx/PXA3xx-based" - depends on MMU -@@ -883,6 +896,8 @@ source "arch/arm/mach-omap2/Kconfig" - - source "arch/arm/mach-orion5x/Kconfig" - -+source "arch/arm/mach-oxnas/Kconfig" -+ - source "arch/arm/mach-picoxcell/Kconfig" - - source "arch/arm/mach-pxa/Kconfig" ---- a/arch/arm/Makefile -+++ b/arch/arm/Makefile -@@ -200,6 +200,7 @@ machine-$(CONFIG_ARCH_NSPIRE) += nspire - machine-$(CONFIG_ARCH_OMAP1) += omap1 - machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2 - machine-$(CONFIG_ARCH_ORION5X) += orion5x -+machine-$(CONFIG_ARCH_OXNAS) += oxnas - machine-$(CONFIG_ARCH_PICOXCELL) += picoxcell - machine-$(CONFIG_ARCH_PXA) += pxa - machine-$(CONFIG_ARCH_QCOM) += qcom ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -497,6 +497,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \ - orion5x-lswsgl.dtb \ - orion5x-maxtor-shared-storage-2.dtb \ - orion5x-rd88f5182-nas.dtb -+dtb-$(CONFIG_ARCH_OXNAS) += ox820-pogoplug-pro.dtb - dtb-$(CONFIG_ARCH_PRIMA2) += \ - prima2-evb.dtb - dtb-$(CONFIG_ARCH_QCOM) += \ ---- a/arch/arm/tools/mach-types -+++ b/arch/arm/tools/mach-types -@@ -228,6 +228,7 @@ edb9302a MACH_EDB9302A EDB9302A 1127 - edb9307a MACH_EDB9307A EDB9307A 1128 - omap_3430sdp MACH_OMAP_3430SDP OMAP_3430SDP 1138 - vstms MACH_VSTMS VSTMS 1140 -+ox820 MACH_OX820 OX820 1152 - micro9m MACH_MICRO9M MICRO9M 1169 - bug MACH_BUG BUG 1179 - at91sam9263ek MACH_AT91SAM9263EK AT91SAM9263EK 1202 ---- a/drivers/clk/Makefile -+++ b/drivers/clk/Makefile -@@ -32,6 +32,7 @@ obj-$(CONFIG_ARCH_MB86S7X) += clk-mb86s - obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o - obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o - obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o -+obj-$(CONFIG_ARCH_OXNAS) += clk-oxnas.o - obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o - obj-$(CONFIG_CLK_QORIQ) += clk-qoriq.o - obj-$(CONFIG_COMMON_CLK_RK808) += clk-rk808.o diff --git a/target/linux/oxnas/patches-4.4/310-oxnas-clocksource.patch b/target/linux/oxnas/patches-4.4/310-oxnas-clocksource.patch deleted file mode 100644 index efb058dbb4..0000000000 --- a/target/linux/oxnas/patches-4.4/310-oxnas-clocksource.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/drivers/clocksource/Kconfig -+++ b/drivers/clocksource/Kconfig -@@ -222,6 +222,12 @@ config VF_PIT_TIMER - help - Support for Period Interrupt Timer on Freescale Vybrid Family SoCs. - -+config CLKSRC_RPS_TIMER -+ def_bool y if ARCH_OXNAS -+ select CLKSRC_MMIO -+ help -+ This option enables support for the oxnas rps timers. -+ - config SYS_SUPPORTS_SH_CMT - bool - ---- a/drivers/clocksource/Makefile -+++ b/drivers/clocksource/Makefile -@@ -41,6 +41,7 @@ obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exyno - obj-$(CONFIG_CLKSRC_LPC32XX) += time-lpc32xx.o - obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o - obj-$(CONFIG_FSL_FTM_TIMER) += fsl_ftm_timer.o -+obj-$(CONFIG_CLKSRC_RPS_TIMER) += oxnas_rps_timer.o - obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o - obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o - obj-$(CONFIG_MTK_TIMER) += mtk_timer.o diff --git a/target/linux/oxnas/patches-4.4/320-oxnas-irqchip.patch b/target/linux/oxnas/patches-4.4/320-oxnas-irqchip.patch deleted file mode 100644 index 37918d680b..0000000000 --- a/target/linux/oxnas/patches-4.4/320-oxnas-irqchip.patch +++ /dev/null @@ -1,34 +0,0 @@ ---- a/drivers/irqchip/Kconfig -+++ b/drivers/irqchip/Kconfig -@@ -27,6 +27,11 @@ config ARM_GIC_V3_ITS - bool - select PCI_MSI_IRQ_DOMAIN - -+config PLXTECH_RPS -+ def_bool y if ARHC_OXNAS -+ depends on ARCH_OXNAS -+ select IRQ_DOMAIN -+ - config ARM_NVIC - bool - select IRQ_DOMAIN ---- a/drivers/irqchip/Makefile -+++ b/drivers/irqchip/Makefile -@@ -34,6 +34,7 @@ obj-$(CONFIG_IRQ_MIPS_CPU) += irq-mips- - obj-$(CONFIG_SIRF_IRQ) += irq-sirfsoc.o - obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o - obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o -+obj-$(CONFIG_PLXTECH_RPS) += irq-rps.o - obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o - obj-$(CONFIG_ARCH_NSPIRE) += irq-zevio.o - obj-$(CONFIG_ARCH_VT8500) += irq-vt8500.o ---- a/drivers/irqchip/irq-gic.c -+++ b/drivers/irqchip/irq-gic.c -@@ -1253,6 +1253,7 @@ IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm, - IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); - IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); - IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); -+IRQCHIP_DECLARE(arm11_mpcore_gic, "arm,arm11mp-gic", gic_of_init); - IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); - IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); - IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init); diff --git a/target/linux/oxnas/patches-4.4/330-oxnas-pinctrl.patch b/target/linux/oxnas/patches-4.4/330-oxnas-pinctrl.patch deleted file mode 100644 index 76a19267a2..0000000000 --- a/target/linux/oxnas/patches-4.4/330-oxnas-pinctrl.patch +++ /dev/null @@ -1,28 +0,0 @@ ---- a/drivers/pinctrl/Kconfig -+++ b/drivers/pinctrl/Kconfig -@@ -228,6 +228,15 @@ config PINCTRL_COH901 - COH 901 335 and COH 901 571/3. They contain 3, 5 or 7 - ports of 8 GPIO pins each. - -+config PINCTRL_OXNAS -+ bool "OXNAS pinctrl driver" -+ depends on OF -+ depends on ARCH_OXNAS -+ select PINMUX -+ select PINCONF -+ help -+ Say Y here to enable the oxnas pinctrl driver -+ - config PINCTRL_PALMAS - bool "Pinctrl driver for the PALMAS Series MFD devices" - depends on OF && MFD_PALMAS ---- a/drivers/pinctrl/Makefile -+++ b/drivers/pinctrl/Makefile -@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd - obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o - obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o - obj-$(CONFIG_PINCTRL_MESON) += meson/ -+obj-$(CONFIG_PINCTRL_OXNAS) += pinctrl-oxnas.o - obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o - obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o - obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o diff --git a/target/linux/oxnas/patches-4.4/340-oxnas-pcie.patch b/target/linux/oxnas/patches-4.4/340-oxnas-pcie.patch deleted file mode 100644 index edc23b70a1..0000000000 --- a/target/linux/oxnas/patches-4.4/340-oxnas-pcie.patch +++ /dev/null @@ -1,22 +0,0 @@ ---- a/drivers/pci/host/Kconfig -+++ b/drivers/pci/host/Kconfig -@@ -173,4 +173,9 @@ config PCI_HISI - help - Say Y here if you want PCIe controller support on HiSilicon HIP05 SoC - -+config PCI_OXNAS -+ bool "PLX Oxnas PCIe controller" -+ depends on ARCH_OXNAS -+ select PCIEPORTBUS -+ - endmenu ---- a/drivers/pci/host/Makefile -+++ b/drivers/pci/host/Makefile -@@ -3,6 +3,7 @@ obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o - obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o - obj-$(CONFIG_PCI_IMX6) += pci-imx6.o - obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o -+obj-$(CONFIG_PCI_OXNAS) += pcie-oxnas.o - obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o - obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o - obj-$(CONFIG_PCI_RCAR_GEN2_PCIE) += pcie-rcar.o diff --git a/target/linux/oxnas/patches-4.4/350-oxnas-reset.patch b/target/linux/oxnas/patches-4.4/350-oxnas-reset.patch deleted file mode 100644 index e9aaf4b430..0000000000 --- a/target/linux/oxnas/patches-4.4/350-oxnas-reset.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- a/drivers/reset/Kconfig -+++ b/drivers/reset/Kconfig -@@ -12,4 +12,9 @@ menuconfig RESET_CONTROLLER - - If unsure, say no. - -+config RESET_CONTROLLER_OXNAS -+ bool -+ select RESET_CONTROLLER -+ - source "drivers/reset/sti/Kconfig" -+ ---- a/drivers/reset/Makefile -+++ b/drivers/reset/Makefile -@@ -1,4 +1,5 @@ - obj-$(CONFIG_RESET_CONTROLLER) += core.o -+obj-$(CONFIG_RESET_CONTROLLER_OXNAS) += reset-ox820.o - obj-$(CONFIG_ARCH_LPC18XX) += reset-lpc18xx.o - obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o - obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o diff --git a/target/linux/oxnas/patches-4.4/400-oxnas-nand.patch b/target/linux/oxnas/patches-4.4/400-oxnas-nand.patch deleted file mode 100644 index fbc3edbbe8..0000000000 --- a/target/linux/oxnas/patches-4.4/400-oxnas-nand.patch +++ /dev/null @@ -1,24 +0,0 @@ ---- a/drivers/mtd/nand/Kconfig -+++ b/drivers/mtd/nand/Kconfig -@@ -563,4 +563,11 @@ config MTD_NAND_QCOM - Enables support for NAND flash chips on SoCs containing the EBI2 NAND - controller. This controller is found on IPQ806x SoC. - -+config MTD_NAND_OXNAS -+ tristate "Support for NAND on Plxtech NAS782X SoC" -+ depends on ARCH_OXNAS -+ help -+ Enables support for NAND Flash chips on Plxtech NAS782X SoCs. NAND is attached -+ to the STATIC Unit. -+ - endif # MTD_NAND ---- a/drivers/mtd/nand/Makefile -+++ b/drivers/mtd/nand/Makefile -@@ -46,6 +46,7 @@ obj-$(CONFIG_MTD_NAND_SOCRATES) += socr - obj-$(CONFIG_MTD_NAND_TXX9NDFMC) += txx9ndfmc.o - obj-$(CONFIG_MTD_NAND_NUC900) += nuc900_nand.o - obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mpc5121_nfc.o -+obj-$(CONFIG_MTD_NAND_OXNAS) += oxnas_nand.o - obj-$(CONFIG_MTD_NAND_VF610_NFC) += vf610_nfc.o - obj-$(CONFIG_MTD_NAND_RICOH) += r852.o - obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o diff --git a/target/linux/oxnas/patches-4.4/500-oxnas-sata.patch b/target/linux/oxnas/patches-4.4/500-oxnas-sata.patch deleted file mode 100644 index b833b635aa..0000000000 --- a/target/linux/oxnas/patches-4.4/500-oxnas-sata.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/ata/Kconfig -+++ b/drivers/ata/Kconfig -@@ -432,6 +432,13 @@ config SATA_VITESSE - - If unsure, say N. - -+config SATA_OXNAS -+ tristate "PLXTECH NAS782X SATA support" -+ help -+ This option enables support for Nas782x Serial ATA controller. -+ -+ If unsure, say N. -+ - comment "PATA SFF controllers with BMDMA" - - config PATA_ALI ---- a/drivers/ata/Makefile -+++ b/drivers/ata/Makefile -@@ -40,6 +40,7 @@ obj-$(CONFIG_SATA_SVW) += sata_svw.o - obj-$(CONFIG_SATA_ULI) += sata_uli.o - obj-$(CONFIG_SATA_VIA) += sata_via.o - obj-$(CONFIG_SATA_VITESSE) += sata_vsc.o -+obj-$(CONFIG_SATA_OXNAS) += sata_oxnas.o - - # SFF PATA w/ BMDMA - obj-$(CONFIG_PATA_ALI) += pata_ali.o diff --git a/target/linux/oxnas/patches-4.4/700-oxnas-dwmac.patch b/target/linux/oxnas/patches-4.4/700-oxnas-dwmac.patch deleted file mode 100644 index 5de25d2e82..0000000000 --- a/target/linux/oxnas/patches-4.4/700-oxnas-dwmac.patch +++ /dev/null @@ -1,29 +0,0 @@ ---- a/drivers/net/ethernet/stmicro/stmmac/Kconfig -+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig -@@ -69,6 +69,16 @@ config DWMAC_MESON - the stmmac device driver. This driver is used for Meson6 and - Meson8 SoCs. - -+config DWMAC_OXNAS -+ tristate "Oxnas gmac support" -+ default ARCH_OXNAS -+ depends on OF && ARCH_OXNAS -+ help -+ Support for Ethernet controller on Oxnas SoCs. -+ -+ This selects the Oxford OX82x SoC glue layer support for -+ the stmmac device driver. -+ - config DWMAC_ROCKCHIP - tristate "Rockchip dwmac support" - default ARCH_ROCKCHIP ---- a/drivers/net/ethernet/stmicro/stmmac/Makefile -+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile -@@ -9,6 +9,7 @@ obj-$(CONFIG_STMMAC_PLATFORM) += stmmac- - obj-$(CONFIG_DWMAC_IPQ806X) += dwmac-ipq806x.o - obj-$(CONFIG_DWMAC_LPC18XX) += dwmac-lpc18xx.o - obj-$(CONFIG_DWMAC_MESON) += dwmac-meson.o -+obj-$(CONFIG_DWMAC_OXNAS) += dwmac-oxnas.o - obj-$(CONFIG_DWMAC_ROCKCHIP) += dwmac-rk.o - obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-socfpga.o - obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o diff --git a/target/linux/oxnas/patches-4.4/800-oxnas-ehci.patch b/target/linux/oxnas/patches-4.4/800-oxnas-ehci.patch deleted file mode 100644 index 7f26de6b14..0000000000 --- a/target/linux/oxnas/patches-4.4/800-oxnas-ehci.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/usb/host/Kconfig -+++ b/drivers/usb/host/Kconfig -@@ -315,6 +315,13 @@ config USB_OCTEON_EHCI - USB 2.0 device support. All CN6XXX based chips with USB are - supported. - -+config USB_EHCI_OXNAS -+ tristate "OXNAS EHCI Module" -+ depends on USB_EHCI_HCD && ARCH_OXNAS -+ select USB_EHCI_ROOT_HUB_TT -+ ---help--- -+ Enable support for the OX820 SOC's on-chip EHCI controller. -+ - endif # USB_EHCI_HCD - - config USB_OXU210HP_HCD ---- a/drivers/usb/host/Makefile -+++ b/drivers/usb/host/Makefile -@@ -41,6 +41,7 @@ obj-$(CONFIG_USB_EHCI_HCD_AT91) += ehci- - obj-$(CONFIG_USB_EHCI_MSM) += ehci-msm.o - obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o - obj-$(CONFIG_USB_W90X900_EHCI) += ehci-w90x900.o -+obj-$(CONFIG_USB_EHCI_OXNAS) += ehci-oxnas.o - - obj-$(CONFIG_USB_OXU210HP_HCD) += oxu210hp-hcd.o - obj-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o diff --git a/target/linux/oxnas/patches-4.4/900-more-boards.patch b/target/linux/oxnas/patches-4.4/900-more-boards.patch deleted file mode 100644 index f41fa8648e..0000000000 --- a/target/linux/oxnas/patches-4.4/900-more-boards.patch +++ /dev/null @@ -1,15 +0,0 @@ ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -497,7 +497,11 @@ dtb-$(CONFIG_ARCH_ORION5X) += \ - orion5x-lswsgl.dtb \ - orion5x-maxtor-shared-storage-2.dtb \ - orion5x-rd88f5182-nas.dtb --dtb-$(CONFIG_ARCH_OXNAS) += ox820-pogoplug-pro.dtb -+dtb-$(CONFIG_ARCH_OXNAS) += ox820-akitio.dtb \ -+ ox820-pogoplug-pro.dtb \ -+ ox820-pogoplug-v3.dtb \ -+ ox820-stg212.dtb \ -+ ox820-kd20.dtb - dtb-$(CONFIG_ARCH_PRIMA2) += \ - prima2-evb.dtb - dtb-$(CONFIG_ARCH_QCOM) += \ diff --git a/target/linux/oxnas/patches-4.4/996-ATAG_DTB_COMPAT_CMDLINE_MANGLE.patch b/target/linux/oxnas/patches-4.4/996-ATAG_DTB_COMPAT_CMDLINE_MANGLE.patch deleted file mode 100644 index 6bffa6fe6a..0000000000 --- a/target/linux/oxnas/patches-4.4/996-ATAG_DTB_COMPAT_CMDLINE_MANGLE.patch +++ /dev/null @@ -1,185 +0,0 @@ -Author: Adrian Panella <ianchi74@outlook.com> -Date: Fri Jun 10 19:10:15 2016 -0500 - -generic: Mangle bootloader's kernel arguments - -The command-line arguments provided by the boot loader will be -appended to a new device tree property: bootloader-args. -If there is a property "append-rootblock" in DT under /chosen -and a root= option in bootloaders command line it will be parsed -and added to DT bootargs with the form: <append-rootblock>XX. -Only command line ATAG will be processed, the rest of the ATAGs -sent by bootloader will be ignored. -This is usefull in dual boot systems, to get the current root partition -without afecting the rest of the system. - - -Signed-off-by: Adrian Panella <ianchi74@outlook.com> - ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -1943,6 +1943,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN - The command-line arguments provided by the boot loader will be - appended to the the device tree bootargs property. - -+config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE -+ bool "Append rootblock parsing bootloader's kernel arguments" -+ help -+ The command-line arguments provided by the boot loader will be -+ appended to a new device tree property: bootloader-args. -+ If there is a property "append-rootblock" in DT under /chosen -+ and a root= option in bootloaders command line it will be parsed -+ and added to DT bootargs with the form: <append-rootblock>XX. -+ Only command line ATAG will be processed, the rest of the ATAGs -+ sent by bootloader will be ignored. -+ - endchoice - - config CMDLINE ---- a/arch/arm/boot/compressed/atags_to_fdt.c -+++ b/arch/arm/boot/compressed/atags_to_fdt.c -@@ -3,6 +3,8 @@ - - #if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND) - #define do_extend_cmdline 1 -+#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+#define do_extend_cmdline 1 - #else - #define do_extend_cmdline 0 - #endif -@@ -66,6 +68,59 @@ static uint32_t get_cell_size(const void - return cell_size; - } - -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+ -+static char *append_rootblock(char *dest, const char *str, int len, void *fdt) -+{ -+ char *ptr, *end; -+ char *root="root="; -+ int i, l; -+ const char *rootblock; -+ -+ //ARM doesn't have __HAVE_ARCH_STRSTR, so search manually -+ ptr = str - 1; -+ -+ do { -+ //first find an 'r' at the begining or after a space -+ do { -+ ptr++; -+ ptr = strchr(ptr, 'r'); -+ if(!ptr) return dest; -+ -+ } while (ptr != str && *(ptr-1) != ' '); -+ -+ //then check for the rest -+ for(i = 1; i <= 4; i++) -+ if(*(ptr+i) != *(root+i)) break; -+ -+ } while (i != 5); -+ -+ end = strchr(ptr, ' '); -+ end = end ? (end - 1) : (strchr(ptr, 0) - 1); -+ -+ //find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX ) -+ for( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++); -+ ptr = end + 1; -+ -+ /* if append-rootblock property is set use it to append to command line */ -+ rootblock = getprop(fdt, "/chosen", "append-rootblock", &l); -+ if(rootblock != NULL) { -+ if(*dest != ' ') { -+ *dest = ' '; -+ dest++; -+ len++; -+ } -+ if (len + l + i <= COMMAND_LINE_SIZE) { -+ memcpy(dest, rootblock, l); -+ dest += l - 1; -+ memcpy(dest, ptr, i); -+ dest += i; -+ } -+ } -+ return dest; -+} -+#endif -+ - static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline) - { - char cmdline[COMMAND_LINE_SIZE]; -@@ -85,12 +140,21 @@ static void merge_fdt_bootargs(void *fdt - - /* and append the ATAG_CMDLINE */ - if (fdt_cmdline) { -+ -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+ //save original bootloader args -+ //and append ubi.mtd with root partition number to current cmdline -+ setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline); -+ ptr = append_rootblock(ptr, fdt_cmdline, len, fdt); -+ -+#else - len = strlen(fdt_cmdline); - if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) { - *ptr++ = ' '; - memcpy(ptr, fdt_cmdline, len); - ptr += len; - } -+#endif - } - *ptr = '\0'; - -@@ -147,7 +211,9 @@ int atags_to_fdt(void *atag_list, void * - else - setprop_string(fdt, "/chosen", "bootargs", - atag->u.cmdline.cmdline); -- } else if (atag->hdr.tag == ATAG_MEM) { -+ } -+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE -+ else if (atag->hdr.tag == ATAG_MEM) { - if (memcount >= sizeof(mem_reg_property)/4) - continue; - if (!atag->u.mem.size) -@@ -186,6 +252,10 @@ int atags_to_fdt(void *atag_list, void * - setprop(fdt, "/memory", "reg", mem_reg_property, - 4 * memcount * memsize); - } -+#else -+ -+ } -+#endif - - return fdt_pack(fdt); - } ---- a/init/main.c -+++ b/init/main.c -@@ -89,6 +89,10 @@ - #include <asm/sections.h> - #include <asm/cacheflush.h> - -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+#include <linux/of.h> -+#endif -+ - static int kernel_init(void *); - - extern void init_IRQ(void); -@@ -562,6 +566,18 @@ asmlinkage __visible void __init start_k - page_alloc_init(); - - pr_notice("Kernel command line: %s\n", boot_command_line); -+ -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+ //Show bootloader's original command line for reference -+ if(of_chosen) { -+ const char *prop = of_get_property(of_chosen, "bootloader-args", NULL); -+ if(prop) -+ pr_notice("Bootloader command line (ignored): %s\n", prop); -+ else -+ pr_notice("Bootloader command line not present\n"); -+ } -+#endif -+ - parse_early_param(); - after_dashes = parse_args("Booting kernel", - static_command_line, __start___param, diff --git a/target/linux/oxnas/patches-4.4/999-libata-hacks.patch b/target/linux/oxnas/patches-4.4/999-libata-hacks.patch deleted file mode 100644 index ac278ab234..0000000000 --- a/target/linux/oxnas/patches-4.4/999-libata-hacks.patch +++ /dev/null @@ -1,57 +0,0 @@ ---- a/drivers/ata/libata-core.c -+++ b/drivers/ata/libata-core.c -@@ -1589,6 +1589,14 @@ unsigned ata_exec_internal_sg(struct ata - return AC_ERR_SYSTEM; - } - -+ if (ap->ops->acquire_hw && !ap->ops->acquire_hw(ap, 0, 0)) { -+ spin_unlock_irqrestore(ap->lock, flags); -+ if (!ap->ops->acquire_hw(ap, 1, (2*HZ))) { -+ return AC_ERR_TIMEOUT; -+ } -+ spin_lock_irqsave(ap->lock, flags); -+ } -+ - /* initialize internal qc */ - - /* XXX: Tag 0 is used for drivers with legacy EH as some -@@ -4788,6 +4796,9 @@ struct ata_queued_cmd *ata_qc_new_init(s - if (unlikely(ap->pflags & ATA_PFLAG_FROZEN)) - return NULL; - -+ if (ap->ops->qc_new && ap->ops->qc_new(ap)) -+ return NULL; -+ - /* libsas case */ - if (ap->flags & ATA_FLAG_SAS_HOST) { - tag = ata_sas_allocate_tag(ap); -@@ -4833,6 +4844,8 @@ void ata_qc_free(struct ata_queued_cmd * - qc->tag = ATA_TAG_POISON; - if (ap->flags & ATA_FLAG_SAS_HOST) - ata_sas_free_tag(tag, ap); -+ if (ap->ops->qc_free) -+ ap->ops->qc_free(qc); - } - } - ---- a/include/linux/libata.h -+++ b/include/linux/libata.h -@@ -906,6 +906,8 @@ struct ata_port_operations { - void (*qc_prep)(struct ata_queued_cmd *qc); - unsigned int (*qc_issue)(struct ata_queued_cmd *qc); - bool (*qc_fill_rtf)(struct ata_queued_cmd *qc); -+ int (*qc_new)(struct ata_port *ap); -+ void (*qc_free)(struct ata_queued_cmd *qc); - - /* - * Configuration and exception handling -@@ -996,6 +998,9 @@ struct ata_port_operations { - void (*phy_reset)(struct ata_port *ap); - void (*eng_timeout)(struct ata_port *ap); - -+ int (*acquire_hw)(struct ata_port *ap, int may_sleep, -+ int timeout_jiffies); -+ - /* - * ->inherits must be the last field and all the preceding - * fields must be pointers. diff --git a/target/linux/oxnas/profiles/00-default.mk b/target/linux/oxnas/profiles/00-default.mk deleted file mode 100644 index fedf730088..0000000000 --- a/target/linux/oxnas/profiles/00-default.mk +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright (C) 2016 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -define Profile/Default - NAME:=Default Profile - PRIORITY:=1 - PACKAGES:=\ - kmod-i2c-gpio kmod-gpio-beeper kmod-hwmon-core \ - kmod-hwmon-gpiofan kmod-rtc-pcf8563 kmod-rtc-ds1307 \ - kmod-usb3 -endef - -define Profile/Default/Description - Default package set compatible with most boards. -endef - -$(eval $(call Profile,Default)) |