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authorLuis Araneda <luaraneda@gmail.com>2018-08-24 00:40:26 -0300
committerHauke Mehrtens <hauke@hauke-m.de>2018-08-25 15:33:51 +0200
commit64f4c3ef357815e5d8c780a0d02924b9176db794 (patch)
tree356d9909d26ed1f692b9c042001656f418ccdae0 /target/linux
parent43dedd0661e3f83405c71b80e1f8d4b4a1e7ac00 (diff)
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zynq: add support for the Zybo Z7 board
The board is manufactured by Digilent Main features: - Soc: XC7Z010 (Z7-10) or XC7Z020 (Z7-20) - RAM: 1 GB DDR3L - FLASH: 16 MB QSPI - 1 Gbps Ethernet - USB 2.0 - microSD slot - Pcam camera connector - HDMI Tx and Rx - Audio codec: stereo out, stereo in, mic - 5 (Z7-10) or 6 (Z7-20) Pmod ports - 6 push-buttons, 4 switches, 5 LEDs - 1 (Z7-10) or 2 (Z7-20) RGB LEDs Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Diffstat (limited to 'target/linux')
-rwxr-xr-xtarget/linux/zynq/base-files/etc/board.d/02_network1
-rw-r--r--target/linux/zynq/image/Makefile7
-rw-r--r--target/linux/zynq/patches-4.14/020-v4.17-add-digilent-zybo-z7-board.patch94
-rw-r--r--target/linux/zynq/patches-4.14/025-v4.19-update-digilent-zybo-z7-dts.patch52
4 files changed, 154 insertions, 0 deletions
diff --git a/target/linux/zynq/base-files/etc/board.d/02_network b/target/linux/zynq/base-files/etc/board.d/02_network
index 90731b68dc..68ff80788a 100755
--- a/target/linux/zynq/base-files/etc/board.d/02_network
+++ b/target/linux/zynq/base-files/etc/board.d/02_network
@@ -7,6 +7,7 @@ board_config_update
case "$(board_name)" in
digilent,zynq-zybo | \
+digilent,zynq-zybo-z7 | \
xlnx,zynq-zc702 | \
xlnx,zynq-zed)
ucidef_set_interface_lan 'eth0'
diff --git a/target/linux/zynq/image/Makefile b/target/linux/zynq/image/Makefile
index 70fb00be69..aa98f4bf3b 100644
--- a/target/linux/zynq/image/Makefile
+++ b/target/linux/zynq/image/Makefile
@@ -36,6 +36,13 @@ define Device/digilent_zynq-zybo
endef
TARGET_DEVICES += digilent_zynq-zybo
+define Device/digilent_zynq-zybo-z7
+ $(call Device/FitImageGzip)
+ DEVICE_TITLE := Digilent Zybo Z7 board
+ DEVICE_DTS := zynq-zybo-z7
+endef
+TARGET_DEVICES += digilent_zynq-zybo-z7
+
define Device/xlnx_zynq-zc702
$(call Device/FitImageGzip)
DEVICE_TITLE := ZC702 Development Board
diff --git a/target/linux/zynq/patches-4.14/020-v4.17-add-digilent-zybo-z7-board.patch b/target/linux/zynq/patches-4.14/020-v4.17-add-digilent-zybo-z7-board.patch
new file mode 100644
index 0000000000..7ff31e374f
--- /dev/null
+++ b/target/linux/zynq/patches-4.14/020-v4.17-add-digilent-zybo-z7-board.patch
@@ -0,0 +1,94 @@
+From ba5c7a032c2ae66d5467820daab898e5f9048405 Mon Sep 17 00:00:00 2001
+From: Nobuhiro Iwamatsu <nobuhiro.iwamatsu@cybertrust.co.jp>
+Date: Wed, 28 Feb 2018 11:25:52 +0900
+Subject: [PATCH] arm: dts: zynq: Add Digilent Zybo Z7 board
+
+This add a DTS for the Digilent Zybo Z7 board.
+This board is the successor board of Zybo, these are almost the same except
+for ps-clk-frequency specifications.
+
+Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu@cybertrust.co.jp>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Michal Simek <michal.simek@xilinx.com>
+---
+Modifications:
+- Removed changes to file Documentation/devicetree/bindings/arm/xilinx.txt
+---
+ arch/arm/boot/dts/Makefile | 3 +-
+ arch/arm/boot/dts/zynq-zybo-z7.dts | 58 +++++++++++++++++++
+ 2 files changed, 60 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm/boot/dts/zynq-zybo-z7.dts
+
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -1006,7 +1006,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
+ zynq-zc702.dtb \
+ zynq-zc706.dtb \
+ zynq-zed.dtb \
+- zynq-zybo.dtb
++ zynq-zybo.dtb \
++ zynq-zybo-z7.dtb
+ dtb-$(CONFIG_MACH_ARMADA_370) += \
+ armada-370-db.dtb \
+ armada-370-dlink-dns327l.dtb \
+--- /dev/null
++++ b/arch/arm/boot/dts/zynq-zybo-z7.dts
+@@ -0,0 +1,58 @@
++// SPDX-License-Identifier: GPL-2.0+
++/dts-v1/;
++#include "zynq-7000.dtsi"
++
++/ {
++ model = "Zynq ZYBO Z7 Development Board";
++ compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000";
++
++ aliases {
++ ethernet0 = &gem0;
++ serial0 = &uart1;
++ };
++
++ memory@0 {
++ device_type = "memory";
++ reg = <0x0 0x20000000>;
++ };
++
++ chosen {
++ bootargs = "";
++ stdout-path = "serial0:115200n8";
++ };
++
++ usb_phy0: phy0 {
++ #phy-cells = <0>;
++ compatible = "usb-nop-xceiv";
++ reset-gpios = <&gpio0 46 1>;
++ };
++};
++
++&clkc {
++ ps-clk-frequency = <33333333>;
++};
++
++&gem0 {
++ status = "okay";
++ phy-mode = "rgmii-id";
++ phy-handle = <&ethernet_phy>;
++
++ ethernet_phy: ethernet-phy@0 {
++ reg = <0>;
++ device_type = "ethernet-phy";
++ };
++};
++
++&sdhci0 {
++ status = "okay";
++};
++
++&uart1 {
++ status = "okay";
++};
++
++&usb0 {
++ status = "okay";
++ dr_mode = "host";
++ usb-phy = <&usb_phy0>;
++};
diff --git a/target/linux/zynq/patches-4.14/025-v4.19-update-digilent-zybo-z7-dts.patch b/target/linux/zynq/patches-4.14/025-v4.19-update-digilent-zybo-z7-dts.patch
new file mode 100644
index 0000000000..d4726498d2
--- /dev/null
+++ b/target/linux/zynq/patches-4.14/025-v4.19-update-digilent-zybo-z7-dts.patch
@@ -0,0 +1,52 @@
+From 7d90ca6f19199a54d3f8417c5f36c50dfa0accc8 Mon Sep 17 00:00:00 2001
+From: Luis Araneda <luaraneda@gmail.com>
+Date: Thu, 12 Jul 2018 01:50:46 -0400
+Subject: [PATCH] v4.19: Backport dts updates to the Digilent Zybo Z7 board
+
+- 7d90ca6: Fix memory size (512 MiB -> 1 GiB)
+- edd62b9: Use GPIO constants
+- a2b7baf: Add gpio-leds node
+
+Signed-off-by: Luis Araneda <luaraneda@gmail.com>
+---
+
+--- a/arch/arm/boot/dts/zynq-zybo-z7.dts
++++ b/arch/arm/boot/dts/zynq-zybo-z7.dts
+@@ -1,6 +1,7 @@
+ // SPDX-License-Identifier: GPL-2.0+
+ /dts-v1/;
+ #include "zynq-7000.dtsi"
++#include <dt-bindings/gpio/gpio.h>
+
+ / {
+ model = "Zynq ZYBO Z7 Development Board";
+@@ -13,7 +14,7 @@
+
+ memory@0 {
+ device_type = "memory";
+- reg = <0x0 0x20000000>;
++ reg = <0x0 0x40000000>;
+ };
+
+ chosen {
+@@ -21,10 +22,19 @@
+ stdout-path = "serial0:115200n8";
+ };
+
++ gpio-leds {
++ compatible = "gpio-leds";
++
++ ld4 {
++ label = "zynq-zybo-z7:green:ld4";
++ gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
++ };
++ };
++
+ usb_phy0: phy0 {
+ #phy-cells = <0>;
+ compatible = "usb-nop-xceiv";
+- reset-gpios = <&gpio0 46 1>;
++ reset-gpios = <&gpio0 46 GPIO_ACTIVE_LOW>;
+ };
+ };
+