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| author | Gabor Juhos <juhosg@openwrt.org> | 2012-11-20 07:19:10 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2012-11-20 07:19:10 +0000 |
| commit | dd092fd10cb1b5e4ef5414952ee0180e2e616886 (patch) | |
| tree | fb4dba7fc5e7dd47341592e311995df40beca9f2 /target/linux | |
| parent | 6c1fbb2d5cd6b2b3f583611cc7cf2f567bec3eb5 (diff) | |
| download | upstream-dd092fd10cb1b5e4ef5414952ee0180e2e616886.tar.gz upstream-dd092fd10cb1b5e4ef5414952ee0180e2e616886.tar.bz2 upstream-dd092fd10cb1b5e4ef5414952ee0180e2e616886.zip | |
ramips: set clk_is_20mhz for rt2x00 on RT3352/RT5350
Signed-off-by: Daniel Golle <dgolle@allnet.de>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 34270
Diffstat (limited to 'target/linux')
| -rw-r--r-- | target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h | 2 | ||||
| -rw-r--r-- | target/linux/ramips/files/arch/mips/ralink/rt305x/devices.c | 8 |
2 files changed, 10 insertions, 0 deletions
diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h index 949232dbd2..943facb6de 100644 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h +++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h @@ -111,6 +111,8 @@ #define RT5350_SYSCFG0_DRAM_SIZE_32M 3 #define RT5350_SYSCFG0_DRAM_SIZE_64M 4 +#define RT3352_SYSCFG0_XTAL_SEL BIT(20) + #define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10) #define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18) diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/devices.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/devices.c index 92ae56d3be..56eae8a9dc 100644 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/devices.c +++ b/target/linux/ramips/files/arch/mips/ralink/rt305x/devices.c @@ -215,7 +215,15 @@ static struct platform_device rt305x_wifi_device = { void __init rt305x_register_wifi(void) { + u32 t; rt305x_wifi_data.eeprom_file_name = "RT305X.eeprom"; + + if (soc_is_rt3352() || soc_is_rt5350()) { + t = rt305x_sysc_rr(SYSC_REG_SYSTEM_CONFIG); + t &= RT3352_SYSCFG0_XTAL_SEL; + if (!t) + rt305x_wifi_data.clk_is_20mhz = 1; + } platform_device_register(&rt305x_wifi_device); } |