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author | Ansuel Smith <ansuelsmth@gmail.com> | 2021-04-02 23:51:11 +0200 |
---|---|---|
committer | Petr Štetiar <ynezz@true.cz> | 2021-07-19 14:51:22 +0200 |
commit | 293d4e61c2f500222d971fbc4b45133604638c66 (patch) | |
tree | 003b287eb9e63bad4c5649660b33967c0f7a95fe /target/linux | |
parent | 06bb4a5018cd84dc4553e71c273e2daae2c996ab (diff) | |
download | upstream-293d4e61c2f500222d971fbc4b45133604638c66.tar.gz upstream-293d4e61c2f500222d971fbc4b45133604638c66.tar.bz2 upstream-293d4e61c2f500222d971fbc4b45133604638c66.zip |
octeon: convert mtd-mac-address to nvmem implementation
Define nvmem-cells and convert mtd-mac-address to nvmem implementation.
The conversion is done with an automated script.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Diffstat (limited to 'target/linux')
3 files changed, 46 insertions, 9 deletions
diff --git a/target/linux/octeon/files/arch/mips/boot/dts/cavium-octeon/cn7130_ubnt_edgerouter-4.dts b/target/linux/octeon/files/arch/mips/boot/dts/cavium-octeon/cn7130_ubnt_edgerouter-4.dts index d8dabfc370..75e2c794b9 100644 --- a/target/linux/octeon/files/arch/mips/boot/dts/cavium-octeon/cn7130_ubnt_edgerouter-4.dts +++ b/target/linux/octeon/files/arch/mips/boot/dts/cavium-octeon/cn7130_ubnt_edgerouter-4.dts @@ -14,7 +14,18 @@ status = "okay"; phy-mode = "sgmii"; phy-handle = <&phy4>; - mtd-mac-address = <&eeprom 0>; + nvmem-cells = <&macaddr_eeprom_0>; + nvmem-cell-names = "mac-address"; }; }; }; + +&eeprom { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_eeprom_0: macaddr@0 { + reg = <0x0 0x6>; + }; +}; diff --git a/target/linux/octeon/files/arch/mips/boot/dts/cavium-octeon/cn7130_ubnt_edgerouter-6p.dts b/target/linux/octeon/files/arch/mips/boot/dts/cavium-octeon/cn7130_ubnt_edgerouter-6p.dts index 7d31885928..c1a41cbf70 100644 --- a/target/linux/octeon/files/arch/mips/boot/dts/cavium-octeon/cn7130_ubnt_edgerouter-6p.dts +++ b/target/linux/octeon/files/arch/mips/boot/dts/cavium-octeon/cn7130_ubnt_edgerouter-6p.dts @@ -32,7 +32,8 @@ status = "okay"; phy-mode = "sgmii"; phy-handle = <&phy4>; - mtd-mac-address = <&eeprom 0>; + nvmem-cells = <&macaddr_eeprom_0>; + nvmem-cell-names = "mac-address"; }; }; @@ -44,8 +45,9 @@ status = "okay"; phy-mode = "sgmii"; phy-handle = <&phy8>; - mtd-mac-address = <&eeprom 0>; - mtd-mac-address-increment = <(4)>; + nvmem-cells = <&macaddr_eeprom_0>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <(4)>; }; ethernet@1 { @@ -53,8 +55,19 @@ status = "okay"; phy-mode = "sgmii"; phy-handle = <&phy9>; - mtd-mac-address = <&eeprom 0>; - mtd-mac-address-increment = <(5)>; + nvmem-cells = <&macaddr_eeprom_0>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <(5)>; }; }; }; + +&eeprom { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_eeprom_0: macaddr@0 { + reg = <0x0 0x6>; + }; +}; diff --git a/target/linux/octeon/files/arch/mips/boot/dts/cavium-octeon/cn7130_ubnt_edgerouter-e300.dtsi b/target/linux/octeon/files/arch/mips/boot/dts/cavium-octeon/cn7130_ubnt_edgerouter-e300.dtsi index 7a4d2e6683..7eafa32cf6 100644 --- a/target/linux/octeon/files/arch/mips/boot/dts/cavium-octeon/cn7130_ubnt_edgerouter-e300.dtsi +++ b/target/linux/octeon/files/arch/mips/boot/dts/cavium-octeon/cn7130_ubnt_edgerouter-e300.dtsi @@ -180,7 +180,8 @@ status = "okay"; phy-mode = "sgmii"; phy-handle = <&phy5>; - mtd-mac-address = <&eeprom 0>; + nvmem-cells = <&macaddr_eeprom_0>; + nvmem-cell-names = "mac-address"; mac-address-increment = <(1)>; }; @@ -189,7 +190,8 @@ status = "okay"; phy-mode = "sgmii"; phy-handle = <&phy6>; - mtd-mac-address = <&eeprom 0>; + nvmem-cells = <&macaddr_eeprom_0>; + nvmem-cell-names = "mac-address"; mac-address-increment = <(2)>; }; @@ -198,8 +200,19 @@ status = "okay"; phy-mode = "sgmii"; phy-handle = <&phy7>; - mtd-mac-address = <&eeprom 0>; + nvmem-cells = <&macaddr_eeprom_0>; + nvmem-cell-names = "mac-address"; mac-address-increment = <(3)>; }; }; }; + +&eeprom { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_eeprom_0: macaddr@0 { + reg = <0x0 0x6>; + }; +}; |