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authorMichael Pratt <mcpratt@pm.me>2021-05-01 14:17:11 -0400
committerPetr Štetiar <ynezz@true.cz>2022-04-19 14:48:21 +0200
commit3f976d0225c7ba6e645a89ff17e101aede6625b3 (patch)
treea371a77a72bd22d1ee93a68803205df6ff91443c /target/linux
parent6685eb29e507ee3e6f913290c54767ba63e2ce80 (diff)
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ramips: mt7620: fix RGMII TXID PHY mode
the register bits for TX delay and RX delay are opposites: when TX delay bit is set, delay is enabled when RX delay bit is set, delay is disabled So, when both bits are unset, it is RX delay and when both bits are set, it is TX delay Note: TXID is the default RGMII mode of the SOC Fixes: 5410a8e2959a ("ramips: mt7620: add rgmii delays support") Signed-off-by: Michael Pratt <mcpratt@pm.me> (cherry picked from commit 26c84b2e46caba1ae17bc82a533c99eee65e7004)
Diffstat (limited to 'target/linux')
-rw-r--r--target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c
index d06e9da586..c596de76bd 100644
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c
@@ -196,7 +196,7 @@ static void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
break;
case PHY_INTERFACE_MODE_RGMII_TXID:
mask = 0;
- val_delay &= ~GSW_REG_GPCx_TXDELAY;
+ val_delay |= GSW_REG_GPCx_TXDELAY;
val_delay |= GSW_REG_GPCx_RXDELAY;
break;
case PHY_INTERFACE_MODE_MII: