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| author | Gabor Juhos <juhosg@openwrt.org> | 2011-11-14 11:49:49 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2011-11-14 11:49:49 +0000 |
| commit | 42e8ae09b553a9867ea9de0c28a0d2528bdf49e7 (patch) | |
| tree | 193b12822a22dce41c6df0a164fe97c379ef8ae9 /target/linux | |
| parent | c15caea360424bf4abb5fa534e0625b9ed043879 (diff) | |
| download | upstream-42e8ae09b553a9867ea9de0c28a0d2528bdf49e7.tar.gz upstream-42e8ae09b553a9867ea9de0c28a0d2528bdf49e7.tar.bz2 upstream-42e8ae09b553a9867ea9de0c28a0d2528bdf49e7.zip | |
ar71xx: add AR934X_RESET_REG_PCIE_WMAC_INT_STATUS defines
SVN-Revision: 29106
Diffstat (limited to 'target/linux')
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h index db5bac7a01..46346648fa 100644 --- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h +++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h @@ -623,6 +623,26 @@ void ar71xx_ddr_flush(u32 reg); #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) #define AR934X_RESET_REG_RESET_MODULE 0x1c + +#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac +#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) +#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) +#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) +#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) +#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4) +#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) +#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) +#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) +#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) +#define AR934X_PCIE_WMAC_INT_WMAC_ALL \ + (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \ + AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP) + +#define AR934X_PCIE_WMAC_INT_PCIE_ALL \ + (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \ + AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ + AR934X_PCIE_WMAC_INT_PCIE_RC3) + #define AR934X_RESET_REG_BOOTSTRAP 0xb0 #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) #define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22) |