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| author | David Bauer <mail@david-bauer.net> | 2021-06-06 19:45:24 +0200 |
|---|---|---|
| committer | Petr Štetiar <ynezz@true.cz> | 2022-04-19 14:48:21 +0200 |
| commit | 08ec622c465e2c6c0cc4ca577a794342882a0abd (patch) | |
| tree | 55e3ad51d47e39a3d3511ef129a90dfe65643c9b /target/linux | |
| parent | 4123f177f969f6510c4bf92b37f66c55e94bd0ef (diff) | |
| download | upstream-08ec622c465e2c6c0cc4ca577a794342882a0abd.tar.gz upstream-08ec622c465e2c6c0cc4ca577a794342882a0abd.tar.bz2 upstream-08ec622c465e2c6c0cc4ca577a794342882a0abd.zip | |
ramips: make PHY initialization more descriptive
The basic mode control register of the ESW PHYs is modified in this
codeblock. Use the respective macros to make this code more readable.
Signed-off-by: David Bauer <mail@david-bauer.net>
(cherry picked from commit 6a15abbc753ca728d798cec9153fc532fce3791d)
Diffstat (limited to 'target/linux')
| -rw-r--r-- | target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c index bd379e6c7d..451881fc73 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c @@ -13,6 +13,7 @@ */ #include <linux/module.h> +#include <linux/mii.h> #include <linux/kernel.h> #include <linux/types.h> #include <linux/platform_device.h> @@ -168,9 +169,9 @@ static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode) /* turn on all PHYs */ for (i = 0; i <= 4; i++) { - val = _mt7620_mii_read(gsw, gsw->ephy_base + i, 0); - val &= ~BIT(11); - _mt7620_mii_write(gsw, gsw->ephy_base + i, 0, val); + val = _mt7620_mii_read(gsw, gsw->ephy_base + i, MII_BMCR); + val &= ~BMCR_PDOWN; + _mt7620_mii_write(gsw, gsw->ephy_base + i, MII_BMCR, val); } } |