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authorJonas Gorski <jogo@openwrt.org>2015-02-28 19:59:34 +0000
committerJonas Gorski <jogo@openwrt.org>2015-02-28 19:59:34 +0000
commit6df9324642268722c5634e490b7952161cd256cb (patch)
treeee90d7986eb1f98c9059c39238eb1c2d2b200f44 /target/linux
parentc2a89871c29da6399c76796dc7d28eda8298f0bc (diff)
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brcm63xx: fix BCM63268 interrupt register locations for legacy probe
Legacy probe passed the IRQSTAT registers instead of the IRQMASK registers causing all register accesses to be offset by 16 bytes. Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 44575
Diffstat (limited to 'target/linux')
-rw-r--r--target/linux/brcm63xx/patches-3.14/339-MIPS-BCM63XX-add-support-for-BCM63268.patch4
-rw-r--r--target/linux/brcm63xx/patches-3.18/339-MIPS-BCM63XX-add-support-for-BCM63268.patch4
2 files changed, 4 insertions, 4 deletions
diff --git a/target/linux/brcm63xx/patches-3.14/339-MIPS-BCM63XX-add-support-for-BCM63268.patch b/target/linux/brcm63xx/patches-3.14/339-MIPS-BCM63XX-add-support-for-BCM63268.patch
index 51f5d943db..9a0ee204fd 100644
--- a/target/linux/brcm63xx/patches-3.14/339-MIPS-BCM63XX-add-support-for-BCM63268.patch
+++ b/target/linux/brcm63xx/patches-3.14/339-MIPS-BCM63XX-add-support-for-BCM63268.patch
@@ -289,8 +289,8 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
ext_shift = 4;
break;
+ case BCM63268_CPU_ID:
-+ periph_bases[0] += PERF_IRQSTAT_63268_REG(0);
-+ periph_bases[1] += PERF_IRQSTAT_63268_REG(1);
++ periph_bases[0] += PERF_IRQMASK_63268_REG(0);
++ periph_bases[1] += PERF_IRQMASK_63268_REG(1);
+ periph_irq_count = 2;
+ periph_width = 4;
+
diff --git a/target/linux/brcm63xx/patches-3.18/339-MIPS-BCM63XX-add-support-for-BCM63268.patch b/target/linux/brcm63xx/patches-3.18/339-MIPS-BCM63XX-add-support-for-BCM63268.patch
index 7c424cc22a..22ceeea1c7 100644
--- a/target/linux/brcm63xx/patches-3.18/339-MIPS-BCM63XX-add-support-for-BCM63268.patch
+++ b/target/linux/brcm63xx/patches-3.18/339-MIPS-BCM63XX-add-support-for-BCM63268.patch
@@ -289,8 +289,8 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
ext_shift = 4;
break;
+ case BCM63268_CPU_ID:
-+ periph_bases[0] += PERF_IRQSTAT_63268_REG(0);
-+ periph_bases[1] += PERF_IRQSTAT_63268_REG(1);
++ periph_bases[0] += PERF_IRQMASK_63268_REG(0);
++ periph_bases[1] += PERF_IRQMASK_63268_REG(1);
+ periph_irq_count = 2;
+ periph_width = 4;
+