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| author | John Crispin <john@openwrt.org> | 2015-01-17 14:50:59 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2015-01-17 14:50:59 +0000 |
| commit | 50a5cd829c8df8f2a60c7478c457f6deba6f6e7a (patch) | |
| tree | 7a042fb3e520f63c13310f6dbb80fcb38ca76cc9 /target/linux | |
| parent | 8698398a6ee4780c235a06a3f9f6ce651b874909 (diff) | |
| download | upstream-50a5cd829c8df8f2a60c7478c457f6deba6f6e7a.tar.gz upstream-50a5cd829c8df8f2a60c7478c457f6deba6f6e7a.tar.bz2 upstream-50a5cd829c8df8f2a60c7478c457f6deba6f6e7a.zip | |
ralink: sync mt7621 pcie driver with latest SDK
fixes newer ECO versions and a hang on reboot bug
Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 44008
Diffstat (limited to 'target/linux')
| -rw-r--r-- | target/linux/ramips/patches-3.14/0016-MIPS-ralink-add-MT7621-pcie-driver.patch | 44 |
1 files changed, 19 insertions, 25 deletions
diff --git a/target/linux/ramips/patches-3.14/0016-MIPS-ralink-add-MT7621-pcie-driver.patch b/target/linux/ramips/patches-3.14/0016-MIPS-ralink-add-MT7621-pcie-driver.patch index 1ff4ed8668..0d0bd09f84 100644 --- a/target/linux/ramips/patches-3.14/0016-MIPS-ralink-add-MT7621-pcie-driver.patch +++ b/target/linux/ramips/patches-3.14/0016-MIPS-ralink-add-MT7621-pcie-driver.patch @@ -12,7 +12,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org> --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile -@@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1 +@@ -41,6 +41,7 @@ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o obj-$(CONFIG_LANTIQ) += fixup-lantiq.o obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o @@ -22,7 +22,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org> obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o --- /dev/null +++ b/arch/mips/pci/pci-mt7621.c -@@ -0,0 +1,797 @@ +@@ -0,0 +1,791 @@ +/************************************************************************** + * + * BRIEF MODULE DESCRIPTION @@ -597,11 +597,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org> +#if defined (CONFIG_PCIE_PORT2) + val |= RALINK_PCIE2_RST; +#endif -+ DEASSERT_SYSRST_PCIE(val); -+ printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL); -+ -+ bypass_pipe_rst(); -+ set_phy_for_ssc(); + ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST); + printk("pull PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL); +#if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/ @@ -627,24 +622,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org> +#endif + DEASSERT_SYSRST_PCIE(val); + printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL); -+#if defined (CONFIG_PCIE_PORT0) -+ read_config(0, 0, 0, 0x70c, &val); -+ val &= ~(0xff)<<8; -+ val |= 0x50<<8; -+ write_config(0, 0, 0, 0x70c, val); -+#endif -+#if defined (CONFIG_PCIE_PORT1) -+ read_config(0, 1, 0, 0x70c, &val); -+ val &= ~(0xff)<<8; -+ val |= 0x50<<8; -+ write_config(0, 1, 0, 0x70c, val); -+#endif -+#if defined (CONFIG_PCIE_PORT2) -+ read_config(0, 2, 0, 0x70c, &val); -+ val &= ~(0xff)<<8; -+ val |= 0x50<<8; -+ write_config(0, 2, 0, 0x70c, val); -+#endif ++ ++ if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2 ++ bypass_pipe_rst(); ++ set_phy_for_ssc(); ++ printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL); + +#if defined (CONFIG_PCIE_PORT0) + read_config(0, 0, 0, 0x70c, &val); @@ -799,16 +781,28 @@ Signed-off-by: John Crispin <blogic@openwrt.org> + read_config(0, 2, 0, 0x4, &val); + write_config(0, 2, 0, 0x4, val|0x4); + // write_config(0, 1, 0, 0x4, val|0x7); ++ read_config(0, 2, 0, 0x70c, &val); ++ val &= ~(0xff)<<8; ++ val |= 0x50<<8; ++ write_config(0, 2, 0, 0x70c, val); + case 3: + case 5: + case 6: + read_config(0, 1, 0, 0x4, &val); + write_config(0, 1, 0, 0x4, val|0x4); + // write_config(0, 1, 0, 0x4, val|0x7); ++ read_config(0, 1, 0, 0x70c, &val); ++ val &= ~(0xff)<<8; ++ val |= 0x50<<8; ++ write_config(0, 1, 0, 0x70c, val); + default: + read_config(0, 0, 0, 0x4, &val); + write_config(0, 0, 0, 0x4, val|0x4); //bus master enable + // write_config(0, 0, 0, 0x4, val|0x7); //bus master enable ++ read_config(0, 0, 0, 0x70c, &val); ++ val &= ~(0xff)<<8; ++ val |= 0x50<<8; ++ write_config(0, 0, 0, 0x70c, val); + } + register_pci_controller(&rt2880_controller); + return 0; |