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| author | Gabor Juhos <juhosg@openwrt.org> | 2009-10-07 11:36:53 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2009-10-07 11:36:53 +0000 |
| commit | ca82f139708be2d12e10e952fd1cc4f2112d67bb (patch) | |
| tree | 80ffa5a43a2507f0b0e244cadf33407927da312b /target/linux | |
| parent | 6a54d033fc2759cb0540ccca4afe77b4fd85cc0c (diff) | |
| download | upstream-ca82f139708be2d12e10e952fd1cc4f2112d67bb.tar.gz upstream-ca82f139708be2d12e10e952fd1cc4f2112d67bb.tar.bz2 upstream-ca82f139708be2d12e10e952fd1cc4f2112d67bb.zip | |
ramips: define some magic values in the rt288x pci code
SVN-Revision: 17969
Diffstat (limited to 'target/linux')
| -rw-r--r-- | target/linux/ramips/files/arch/mips/pci/pci-rt288x.c | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c b/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c index 8ec50d6e4c..333f64fe60 100644 --- a/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c +++ b/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c @@ -19,7 +19,10 @@ #include <asm/mach-ralink/rt288x.h> #include <asm/mach-ralink/rt288x_regs.h> -#define RT2880_PCI_SLOT1_BASE 0x20000000 +#define RT2880_PCI_MEM_BASE 0x20000000 +#define RT2880_PCI_MEM_SIZE 0x10000000 +#define RT2880_PCI_IO_BASE 0x00460000 +#define RT2880_PCI_IO_SIZE 0x00010000 #define RT2880_PCI_REG_PCICFG_ADDR 0x00 #define RT2880_PCI_REG_PCIMSK_ADDR 0x0c @@ -112,15 +115,15 @@ static struct pci_ops rt2880_pci_ops = { static struct resource rt2880_pci_io_resource = { .name = "PCI MEM space", - .start = 0x20000000, - .end = 0x2FFFFFFF, + .start = RT2880_PCI_MEM_BASE, + .end = RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1, .flags = IORESOURCE_MEM, }; static struct resource rt2880_pci_mem_resource = { .name = "PCI IO space", - .start = 0x00460000, - .end = 0x0046FFFF, + .start = RT2880_PCI_IO_BASE, + .end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1, .flags = IORESOURCE_IO, }; @@ -202,8 +205,8 @@ static int __init rt2880_pci_init(void) rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL); rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR); - rt2880_pci_reg_write(RT2880_PCI_SLOT1_BASE, RT2880_PCI_REG_MEMBASE); - rt2880_pci_reg_write(0x00460000, RT2880_PCI_REG_IOBASE); + rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE); + rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE); rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR); rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID); rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS); |