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authorPavel Kubelun <be.dissent@gmail.com>2017-07-06 17:20:18 +0300
committerFelix Fietkau <nbd@nbd.name>2018-01-17 11:02:05 +0100
commit83499bef73cc67b9290360cf76c345a7b3c29f08 (patch)
tree62a2fd8e3903847e90087e030a4ba37482415c3b /target/linux
parent36a96a449303560395e9566faee58afbfdab745d (diff)
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ipq806x: force 2nd pci slot into gen1 mode
According to QSDK and OEM tarballs (checked c2600, r7500v2, r7800) 2nd pci slot (pci1, 2,4 GHz card)) on ap148 based boards should operate in gen1 mode. EA8500 is an exception and according to GPL pcie0 should operate in gen1 mode. In previous commit we've added the support for this option, so enable it in DT for affected devices. QSDK ref: https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-msm/commit/?h=release/endive_preview_cc&id=f3b07fe309027c52fc163149500cedddd707c506 While at it move the phy transmit termination offset value into dtsi file as it's platform specific. Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
Diffstat (limited to 'target/linux')
-rw-r--r--target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-ap148.dts3
-rw-r--r--target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-c2600.dts3
-rw-r--r--target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-d7800.dts1
-rw-r--r--target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts8
-rw-r--r--target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-r7500.dts1
-rw-r--r--target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts1
-rw-r--r--target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts3
-rw-r--r--target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064.dtsi6
-rw-r--r--target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts1
-rw-r--r--target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8065-r7800.dts3
10 files changed, 17 insertions, 13 deletions
diff --git a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
index fa4f05bdbe..39a0d96563 100644
--- a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -161,12 +161,11 @@
pcie0: pci@1b500000 {
status = "ok";
- phy-tx0-term-offset = <7>;
};
pcie1: pci@1b700000 {
status = "ok";
- phy-tx0-term-offset = <7>;
+ force_gen1 = <1>;
};
nand@1ac00000 {
diff --git a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-c2600.dts b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-c2600.dts
index 80bc5dfa04..a4fd13429c 100644
--- a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-c2600.dts
+++ b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-c2600.dts
@@ -346,12 +346,11 @@
pcie0: pci@1b500000 {
status = "ok";
- phy-tx0-term-offset = <7>;
};
pcie1: pci@1b700000 {
status = "ok";
- phy-tx0-term-offset = <7>;
+ force_gen1 = <1>;
};
mdio0: mdio {
diff --git a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-d7800.dts b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-d7800.dts
index c1a4c82a28..b7c49cc816 100644
--- a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-d7800.dts
+++ b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-d7800.dts
@@ -193,6 +193,7 @@
reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
+ force_gen1 = <1>;
};
nand@1ac00000 {
diff --git a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts
index 761fa43179..a8628ff938 100644
--- a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts
+++ b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts
@@ -157,19 +157,17 @@
pcie0: pci@1b500000 {
status = "ok";
- phy-tx0-term-offset = <7>;
+ force_gen1 = <1>;
};
pcie1: pci@1b700000 {
status = "ok";
- phy-tx0-term-offset = <7>;
};
-
+
pcie2: pci@1b900000 {
status = "ok";
- phy-tx0-term-offset = <7>;
};
-
+
nand@1ac00000 {
status = "ok";
diff --git a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-r7500.dts b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-r7500.dts
index 2ea856d88b..3445a79251 100644
--- a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-r7500.dts
+++ b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-r7500.dts
@@ -168,6 +168,7 @@
pcie1: pci@1b700000 {
status = "ok";
+ force_gen1 = <1>;
};
nand@1ac00000 {
diff --git a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts
index a21cf18bee..c4b0c4b5a7 100644
--- a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts
+++ b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts
@@ -198,6 +198,7 @@
reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
+ force_gen1 = <1>;
};
nand@1ac00000 {
diff --git a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts
index b55a98d229..561c49aaa6 100644
--- a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts
+++ b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts
@@ -259,12 +259,11 @@
pcie0: pci@1b500000 {
status = "ok";
- phy-tx0-term-offset = <7>;
};
pcie1: pci@1b700000 {
status = "ok";
- phy-tx0-term-offset = <7>;
+ force_gen1 = <1>;
};
mdio0: mdio {
diff --git a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064.dtsi b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 9996bd7415..4b93fea98a 100644
--- a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -1051,6 +1051,8 @@
perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
+ phy-tx0-term-offset = <7>;
+
status = "disabled";
};
@@ -1103,6 +1105,8 @@
perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
+ phy-tx0-term-offset = <7>;
+
status = "disabled";
};
@@ -1155,6 +1159,8 @@
perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
+ phy-tx0-term-offset = <7>;
+
status = "disabled";
};
diff --git a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts
index 15165b9b72..987ee852cc 100644
--- a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts
+++ b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts
@@ -229,6 +229,7 @@
reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
+ force_gen1 = <1>;
};
mdio0: mdio {
diff --git a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8065-r7800.dts b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8065-r7800.dts
index 403054cc97..4c89dcf76f 100644
--- a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8065-r7800.dts
+++ b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8065-r7800.dts
@@ -299,12 +299,11 @@
pcie0: pci@1b500000 {
status = "ok";
- phy-tx0-term-offset = <7>;
};
pcie1: pci@1b700000 {
status = "ok";
- phy-tx0-term-offset = <7>;
+ force_gen1 = <1>;
};
nand@1ac00000 {