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authorGabor Juhos <juhosg@openwrt.org>2009-05-28 13:00:08 +0000
committerGabor Juhos <juhosg@openwrt.org>2009-05-28 13:00:08 +0000
commitc2c496868e73e78b766af3ed943e5e1b1efb20bb (patch)
tree881ca189a4d4afe55cfbacf4f7f733aa11838ad3 /target/linux
parent7adb67f18469e51cecb83a0c2efbf22494acb244 (diff)
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add support for board specific PLL settings
SVN-Revision: 16133
Diffstat (limited to 'target/linux')
-rw-r--r--target/linux/ar71xx/files/arch/mips/ar71xx/devices.c106
-rw-r--r--target/linux/ar71xx/files/arch/mips/ar71xx/devices.h9
-rw-r--r--target/linux/ar71xx/files/arch/mips/ar71xx/mach-ap83.c2
-rw-r--r--target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/platform.h2
-rw-r--r--target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c17
5 files changed, 115 insertions, 21 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c b/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c
index fbe8c1078b..f76dad5a9f 100644
--- a/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c
+++ b/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c
@@ -237,26 +237,70 @@ static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
iounmap(base);
}
-static void ar71xx_set_pll_ge0(u32 val)
+struct ar71xx_eth_pll_data ar71xx_eth0_pll_data;
+struct ar71xx_eth_pll_data ar71xx_eth1_pll_data;
+
+static u32 ar71xx_get_eth_pll(unsigned int mac, int speed)
{
+ struct ar71xx_eth_pll_data *pll_data;
+ u32 pll_val;
+
+ switch (mac) {
+ case 0:
+ pll_data = &ar71xx_eth0_pll_data;
+ break;
+ case 1:
+ pll_data = &ar71xx_eth1_pll_data;
+ break;
+ default:
+ BUG();
+ }
+
+ switch (speed) {
+ case SPEED_10:
+ pll_val = pll_data->pll_10;
+ break;
+ case SPEED_100:
+ pll_val = pll_data->pll_100;
+ break;
+ case SPEED_1000:
+ pll_val = pll_data->pll_1000;
+ break;
+ default:
+ BUG();
+ }
+
+ return pll_val;
+}
+
+static void ar71xx_set_pll_ge0(int speed)
+{
+ u32 val = ar71xx_get_eth_pll(0, speed);
+
ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
val, AR71XX_ETH0_PLL_SHIFT);
}
-static void ar71xx_set_pll_ge1(u32 val)
+static void ar71xx_set_pll_ge1(int speed)
{
+ u32 val = ar71xx_get_eth_pll(1, speed);
+
ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
val, AR71XX_ETH1_PLL_SHIFT);
}
-static void ar91xx_set_pll_ge0(u32 val)
+static void ar91xx_set_pll_ge0(int speed)
{
+ u32 val = ar71xx_get_eth_pll(0, speed);
+
ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK,
val, AR91XX_ETH0_PLL_SHIFT);
}
-static void ar91xx_set_pll_ge1(u32 val)
+static void ar91xx_set_pll_ge1(int speed)
{
+ u32 val = ar71xx_get_eth_pll(1, speed);
+
ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK,
val, AR91XX_ETH1_PLL_SHIFT);
}
@@ -357,12 +401,66 @@ static struct platform_device ar71xx_eth1_device = {
},
};
+#define AR71XX_PLL_VAL_1000 0x00110000
+#define AR71XX_PLL_VAL_100 0x00001099
+#define AR71XX_PLL_VAL_10 0x00991099
+
+#define AR91XX_PLL_VAL_1000 0x1a000000
+#define AR91XX_PLL_VAL_100 0x13000a44
+#define AR91XX_PLL_VAL_10 0x00441099
+
+static void __init ar71xx_init_eth_pll_data(unsigned int id)
+{
+ struct ar71xx_eth_pll_data *pll_data;
+ u32 pll_10, pll_100, pll_1000;
+
+ switch (id) {
+ case 0:
+ pll_data = &ar71xx_eth0_pll_data;
+ break;
+ case 1:
+ pll_data = &ar71xx_eth1_pll_data;
+ break;
+ default:
+ BUG();
+ }
+
+ switch (ar71xx_soc) {
+ case AR71XX_SOC_AR7130:
+ case AR71XX_SOC_AR7141:
+ case AR71XX_SOC_AR7161:
+ pll_10 = AR71XX_PLL_VAL_10;
+ pll_100 = AR71XX_PLL_VAL_100;
+ pll_1000 = AR71XX_PLL_VAL_1000;
+ break;
+ case AR71XX_SOC_AR9130:
+ case AR71XX_SOC_AR9132:
+ pll_10 = AR91XX_PLL_VAL_10;
+ pll_100 = AR91XX_PLL_VAL_100;
+ pll_1000 = AR91XX_PLL_VAL_1000;
+ break;
+ default:
+ BUG();
+ }
+
+ if (!pll_data->pll_10)
+ pll_data->pll_10 = pll_10;
+
+ if (!pll_data->pll_100)
+ pll_data->pll_100 = pll_100;
+
+ if (!pll_data->pll_1000)
+ pll_data->pll_1000 = pll_1000;
+}
+
static int ar71xx_eth_instance __initdata;
void __init ar71xx_add_device_eth(unsigned int id)
{
struct platform_device *pdev;
struct ag71xx_platform_data *pdata;
+ ar71xx_init_eth_pll_data(id);
+
switch (id) {
case 0:
switch (ar71xx_eth0_data.phy_if_mode) {
diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/devices.h b/target/linux/ar71xx/files/arch/mips/ar71xx/devices.h
index b0119753db..ec75ac1e8c 100644
--- a/target/linux/ar71xx/files/arch/mips/ar71xx/devices.h
+++ b/target/linux/ar71xx/files/arch/mips/ar71xx/devices.h
@@ -25,6 +25,15 @@ void ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata,
void ar71xx_set_mac_base(unsigned char *mac) __init;
void ar71xx_parse_mac_addr(char *mac_str) __init;
+struct ar71xx_eth_pll_data {
+ u32 pll_10;
+ u32 pll_100;
+ u32 pll_1000;
+};
+
+extern struct ar71xx_eth_pll_data ar71xx_eth0_pll_data;
+extern struct ar71xx_eth_pll_data ar71xx_eth1_pll_data;
+
extern struct ag71xx_platform_data ar71xx_eth0_data;
extern struct ag71xx_platform_data ar71xx_eth1_data;
void ar71xx_add_device_eth(unsigned int id) __init;
diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/mach-ap83.c b/target/linux/ar71xx/files/arch/mips/ar71xx/mach-ap83.c
index 4ebdc61ce5..8b5dbca34b 100644
--- a/target/linux/ar71xx/files/arch/mips/ar71xx/mach-ap83.c
+++ b/target/linux/ar71xx/files/arch/mips/ar71xx/mach-ap83.c
@@ -93,6 +93,8 @@ static void __init ap83_setup(void)
ar71xx_eth1_data.speed = SPEED_1000;
ar71xx_eth1_data.duplex = DUPLEX_FULL;
+ ar71xx_eth1_pll_data.pll_1000 = 0x1f000000;
+
ar71xx_add_device_eth(1);
ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ap83_leds_gpio),
diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/platform.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/platform.h
index 672da31c83..55c62b7130 100644
--- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/platform.h
+++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/platform.h
@@ -31,7 +31,7 @@ struct ag71xx_platform_data {
u8 has_ar8216:1;
void (* ddr_flush)(void);
- void (* set_pll)(u32 pll);
+ void (* set_pll)(int speed);
};
struct ag71xx_mdio_platform_data {
diff --git a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c
index ab76a48415..004d886f0c 100644
--- a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c
+++ b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c
@@ -27,20 +27,11 @@ static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
return "?";
}
-#define AR71XX_PLL_VAL_1000 0x00110000
-#define AR71XX_PLL_VAL_100 0x00001099
-#define AR71XX_PLL_VAL_10 0x00991099
-
-#define AR91XX_PLL_VAL_1000 0x1a000000
-#define AR91XX_PLL_VAL_100 0x13000a44
-#define AR91XX_PLL_VAL_10 0x00441099
-
static void ag71xx_phy_link_update(struct ag71xx *ag)
{
struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
u32 cfg2;
u32 ifctl;
- u32 pll;
u32 fifo5;
u32 mii_speed;
@@ -65,22 +56,16 @@ static void ag71xx_phy_link_update(struct ag71xx *ag)
case SPEED_1000:
mii_speed = MII_CTRL_SPEED_1000;
cfg2 |= MAC_CFG2_IF_1000;
- pll = pdata->is_ar91xx ? AR91XX_PLL_VAL_1000
- : AR71XX_PLL_VAL_1000;
fifo5 |= FIFO_CFG5_BM;
break;
case SPEED_100:
mii_speed = MII_CTRL_SPEED_100;
cfg2 |= MAC_CFG2_IF_10_100;
ifctl |= MAC_IFCTL_SPEED;
- pll = pdata->is_ar91xx ? AR91XX_PLL_VAL_100
- : AR71XX_PLL_VAL_100;
break;
case SPEED_10:
mii_speed = MII_CTRL_SPEED_10;
cfg2 |= MAC_CFG2_IF_10_100;
- pll = pdata->is_ar91xx ? AR91XX_PLL_VAL_10
- : AR71XX_PLL_VAL_10;
break;
default:
BUG();
@@ -89,7 +74,7 @@ static void ag71xx_phy_link_update(struct ag71xx *ag)
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3,
pdata->is_ar91xx ? 0x780fff : 0x008001ff);
- pdata->set_pll(pll);
+ pdata->set_pll(ag->speed);
ag71xx_mii_ctrl_set_speed(ag, mii_speed);
ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);