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authorFelix Fietkau <nbd@openwrt.org>2015-12-12 11:27:51 +0000
committerFelix Fietkau <nbd@openwrt.org>2015-12-12 11:27:51 +0000
commitbb52e2e1ef15c7b933f1d548ccee96536b21f84a (patch)
tree95be4cda87c4044514e9e8df4e9b19741f166ec9 /target/linux
parent4e31b2e8697c21f9bd6493bb3d78a4a41c6a9a52 (diff)
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ar71xx: add rx/tx delay definitons for qca955x's MAC
This patch adds the rx/tx register offsets for the qca955x SoC. Signed-off-by: Chris R Blake <chrisrblake93@gmail.com> SVN-Revision: 47882
Diffstat (limited to 'target/linux')
-rw-r--r--target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay-defs.patch14
1 files changed, 14 insertions, 0 deletions
diff --git a/target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay-defs.patch b/target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay-defs.patch
new file mode 100644
index 0000000000..2d89fd8a92
--- /dev/null
+++ b/target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay-defs.patch
@@ -0,0 +1,14 @@
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -1098,5 +1098,11 @@
+
+ #define QCA955X_ETH_CFG_RGMII_EN BIT(0)
+ #define QCA955X_ETH_CFG_GE0_SGMII BIT(6)
++#define QCA955X_ETH_CFG_RXD_DELAY BIT(14)
++#define QCA955X_ETH_CFG_RXD_DELAY_MASK 0x3
++#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT 14
++#define QCA955X_ETH_CFG_RDV_DELAY BIT(16)
++#define QCA955X_ETH_CFG_RDV_DELAY_MASK 0x3
++#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT 16
+
+ #endif /* __ASM_MACH_AR71XX_REGS_H */